2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
83 #define SERIAL_ATMEL_MAJOR 204
84 #define MINOR_START 154
85 #define ATMEL_DEVICENAME "ttyAT"
89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
92 #define MINOR_START 64
93 #define ATMEL_DEVICENAME "ttyS"
97 #define ATMEL_ISR_PASS_LIMIT 256
99 struct atmel_dma_buffer {
102 unsigned int dma_size;
106 struct atmel_uart_char {
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
117 #define ATMEL_SERIAL_RINGSIZE 1024
120 * at91: 6 USARTs and one DBGU port (SAM9260)
123 #define ATMEL_MAX_UART 7
126 * We wrap our port structure around the generic uart_port.
128 struct atmel_uart_port {
129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
133 int break_active; /* break being received */
135 bool use_dma_rx; /* enable DMA receiver */
136 bool use_pdc_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140 bool use_dma_tx; /* enable DMA transmitter */
141 bool use_pdc_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144 spinlock_t lock_tx; /* port lock */
145 spinlock_t lock_rx; /* port lock */
146 struct dma_chan *chan_tx;
147 struct dma_chan *chan_rx;
148 struct dma_async_tx_descriptor *desc_tx;
149 struct dma_async_tx_descriptor *desc_rx;
150 dma_cookie_t cookie_tx;
151 dma_cookie_t cookie_rx;
152 struct scatterlist sg_tx;
153 struct scatterlist sg_rx;
154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
156 atomic_t tasklet_shutdown;
157 unsigned int irq_status_prev;
160 struct circ_buf rx_ring;
162 struct mctrl_gpios *gpios;
163 unsigned int tx_done_mask;
168 u32 rtor; /* address of receiver timeout register if it exists */
169 bool has_frac_baudrate;
171 struct timer_list uart_timer;
174 unsigned int pending;
175 unsigned int pending_status;
176 spinlock_t lock_suspended;
178 bool hd_start_rx; /* can start RX during half-duplex operation */
180 int (*prepare_rx)(struct uart_port *port);
181 int (*prepare_tx)(struct uart_port *port);
182 void (*schedule_rx)(struct uart_port *port);
183 void (*schedule_tx)(struct uart_port *port);
184 void (*release_rx)(struct uart_port *port);
185 void (*release_tx)(struct uart_port *port);
188 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
189 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
192 static struct console atmel_console;
195 #if defined(CONFIG_OF)
196 static const struct of_device_id atmel_serial_dt_ids[] = {
197 { .compatible = "atmel,at91rm9200-usart" },
198 { .compatible = "atmel,at91sam9260-usart" },
203 static inline struct atmel_uart_port *
204 to_atmel_uart_port(struct uart_port *uart)
206 return container_of(uart, struct atmel_uart_port, uart);
209 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
211 return __raw_readl(port->membase + reg);
214 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
216 __raw_writel(value, port->membase + reg);
221 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
222 static inline u8 atmel_uart_read_char(struct uart_port *port)
224 return __raw_readl(port->membase + ATMEL_US_RHR);
227 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
229 __raw_writel(value, port->membase + ATMEL_US_THR);
234 static inline u8 atmel_uart_read_char(struct uart_port *port)
236 return __raw_readb(port->membase + ATMEL_US_RHR);
239 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
241 __raw_writeb(value, port->membase + ATMEL_US_THR);
246 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
248 return (port->rs485.flags & SER_RS485_ENABLED) &&
249 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
252 #ifdef CONFIG_SERIAL_ATMEL_PDC
253 static bool atmel_use_pdc_rx(struct uart_port *port)
255 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
257 return atmel_port->use_pdc_rx;
260 static bool atmel_use_pdc_tx(struct uart_port *port)
262 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
264 return atmel_port->use_pdc_tx;
267 static bool atmel_use_pdc_rx(struct uart_port *port)
272 static bool atmel_use_pdc_tx(struct uart_port *port)
278 static bool atmel_use_dma_tx(struct uart_port *port)
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
282 return atmel_port->use_dma_tx;
285 static bool atmel_use_dma_rx(struct uart_port *port)
287 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
289 return atmel_port->use_dma_rx;
292 static bool atmel_use_fifo(struct uart_port *port)
294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
296 return atmel_port->fifo_size;
299 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
300 struct tasklet_struct *t)
302 if (!atomic_read(&atmel_port->tasklet_shutdown))
306 static unsigned int atmel_get_lines_status(struct uart_port *port)
308 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
309 unsigned int status, ret = 0;
311 status = atmel_uart_readl(port, ATMEL_US_CSR);
313 mctrl_gpio_get(atmel_port->gpios, &ret);
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
318 status &= ~ATMEL_US_CTS;
320 status |= ATMEL_US_CTS;
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
326 status &= ~ATMEL_US_DSR;
328 status |= ATMEL_US_DSR;
331 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
334 status &= ~ATMEL_US_RI;
336 status |= ATMEL_US_RI;
339 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
342 status &= ~ATMEL_US_DCD;
344 status |= ATMEL_US_DCD;
350 /* Enable or disable the rs485 support */
351 static int atmel_config_rs485(struct uart_port *port,
352 struct serial_rs485 *rs485conf)
354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
357 /* Disable interrupts */
358 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
360 mode = atmel_uart_readl(port, ATMEL_US_MR);
362 /* Resetting serial mode to RS232 (0x0) */
363 mode &= ~ATMEL_US_USMODE;
365 port->rs485 = *rs485conf;
367 if (rs485conf->flags & SER_RS485_ENABLED) {
368 dev_dbg(port->dev, "Setting UART to RS485\n");
369 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
370 atmel_uart_writel(port, ATMEL_US_TTGR,
371 rs485conf->delay_rts_after_send);
372 mode |= ATMEL_US_USMODE_RS485;
374 dev_dbg(port->dev, "Setting UART to RS232\n");
375 if (atmel_use_pdc_tx(port))
376 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
379 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
381 atmel_uart_writel(port, ATMEL_US_MR, mode);
383 /* Enable interrupts */
384 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
390 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
392 static u_int atmel_tx_empty(struct uart_port *port)
394 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
400 * Set state of the modem control output lines
402 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
404 unsigned int control = 0;
405 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
406 unsigned int rts_paused, rts_ready;
407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
409 /* override mode to RS485 if needed, otherwise keep the current mode */
410 if (port->rs485.flags & SER_RS485_ENABLED) {
411 atmel_uart_writel(port, ATMEL_US_TTGR,
412 port->rs485.delay_rts_after_send);
413 mode &= ~ATMEL_US_USMODE;
414 mode |= ATMEL_US_USMODE_RS485;
417 /* set the RTS line state according to the mode */
418 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
419 /* force RTS line to high level */
420 rts_paused = ATMEL_US_RTSEN;
422 /* give the control of the RTS line back to the hardware */
423 rts_ready = ATMEL_US_RTSDIS;
425 /* force RTS line to high level */
426 rts_paused = ATMEL_US_RTSDIS;
428 /* force RTS line to low level */
429 rts_ready = ATMEL_US_RTSEN;
432 if (mctrl & TIOCM_RTS)
433 control |= rts_ready;
435 control |= rts_paused;
437 if (mctrl & TIOCM_DTR)
438 control |= ATMEL_US_DTREN;
440 control |= ATMEL_US_DTRDIS;
442 atmel_uart_writel(port, ATMEL_US_CR, control);
444 mctrl_gpio_set(atmel_port->gpios, mctrl);
446 /* Local loopback mode? */
447 mode &= ~ATMEL_US_CHMODE;
448 if (mctrl & TIOCM_LOOP)
449 mode |= ATMEL_US_CHMODE_LOC_LOOP;
451 mode |= ATMEL_US_CHMODE_NORMAL;
453 atmel_uart_writel(port, ATMEL_US_MR, mode);
457 * Get state of the modem control input lines
459 static u_int atmel_get_mctrl(struct uart_port *port)
461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
462 unsigned int ret = 0, status;
464 status = atmel_uart_readl(port, ATMEL_US_CSR);
467 * The control signals are active low.
469 if (!(status & ATMEL_US_DCD))
471 if (!(status & ATMEL_US_CTS))
473 if (!(status & ATMEL_US_DSR))
475 if (!(status & ATMEL_US_RI))
478 return mctrl_gpio_get(atmel_port->gpios, &ret);
484 static void atmel_stop_tx(struct uart_port *port)
486 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
488 if (atmel_use_pdc_tx(port)) {
489 /* disable PDC transmit */
490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
494 * Disable the transmitter.
495 * This is mandatory when DMA is used, otherwise the DMA buffer
496 * is fully transmitted.
498 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
500 /* Disable interrupts */
501 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
503 if (atmel_uart_is_half_duplex(port))
504 atmel_start_rx(port);
509 * Start transmitting.
511 static void atmel_start_tx(struct uart_port *port)
513 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
515 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
517 /* The transmitter is already running. Yes, we
521 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
522 if (atmel_uart_is_half_duplex(port))
525 if (atmel_use_pdc_tx(port))
526 /* re-enable PDC transmit */
527 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
529 /* Enable interrupts */
530 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
532 /* re-enable the transmitter */
533 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
537 * start receiving - port is in process of being opened.
539 static void atmel_start_rx(struct uart_port *port)
541 /* reset status and receiver */
542 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
544 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
546 if (atmel_use_pdc_rx(port)) {
547 /* enable PDC controller */
548 atmel_uart_writel(port, ATMEL_US_IER,
549 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
550 port->read_status_mask);
551 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
553 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
558 * Stop receiving - port is in process of being closed.
560 static void atmel_stop_rx(struct uart_port *port)
562 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
564 if (atmel_use_pdc_rx(port)) {
565 /* disable PDC receive */
566 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
567 atmel_uart_writel(port, ATMEL_US_IDR,
568 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
569 port->read_status_mask);
571 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
576 * Enable modem status interrupts
578 static void atmel_enable_ms(struct uart_port *port)
580 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
584 * Interrupt should not be enabled twice
586 if (atmel_port->ms_irq_enabled)
589 atmel_port->ms_irq_enabled = true;
591 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
592 ier |= ATMEL_US_CTSIC;
594 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
595 ier |= ATMEL_US_DSRIC;
597 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
598 ier |= ATMEL_US_RIIC;
600 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
601 ier |= ATMEL_US_DCDIC;
603 atmel_uart_writel(port, ATMEL_US_IER, ier);
605 mctrl_gpio_enable_ms(atmel_port->gpios);
609 * Disable modem status interrupts
611 static void atmel_disable_ms(struct uart_port *port)
613 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
617 * Interrupt should not be disabled twice
619 if (!atmel_port->ms_irq_enabled)
622 atmel_port->ms_irq_enabled = false;
624 mctrl_gpio_disable_ms(atmel_port->gpios);
626 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
627 idr |= ATMEL_US_CTSIC;
629 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
630 idr |= ATMEL_US_DSRIC;
632 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
633 idr |= ATMEL_US_RIIC;
635 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
636 idr |= ATMEL_US_DCDIC;
638 atmel_uart_writel(port, ATMEL_US_IDR, idr);
642 * Control the transmission of a break signal
644 static void atmel_break_ctl(struct uart_port *port, int break_state)
646 if (break_state != 0)
648 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
651 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
655 * Stores the incoming character in the ring buffer
658 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
661 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
662 struct circ_buf *ring = &atmel_port->rx_ring;
663 struct atmel_uart_char *c;
665 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
666 /* Buffer overflow, ignore char */
669 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
673 /* Make sure the character is stored before we update head. */
676 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
680 * Deal with parity, framing and overrun errors.
682 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
685 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
687 if (status & ATMEL_US_RXBRK) {
688 /* ignore side-effect */
689 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
692 if (status & ATMEL_US_PARE)
693 port->icount.parity++;
694 if (status & ATMEL_US_FRAME)
695 port->icount.frame++;
696 if (status & ATMEL_US_OVRE)
697 port->icount.overrun++;
701 * Characters received (called from interrupt handler)
703 static void atmel_rx_chars(struct uart_port *port)
705 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
706 unsigned int status, ch;
708 status = atmel_uart_readl(port, ATMEL_US_CSR);
709 while (status & ATMEL_US_RXRDY) {
710 ch = atmel_uart_read_char(port);
713 * note that the error handling code is
714 * out of the main execution path
716 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
717 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
718 || atmel_port->break_active)) {
721 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
723 if (status & ATMEL_US_RXBRK
724 && !atmel_port->break_active) {
725 atmel_port->break_active = 1;
726 atmel_uart_writel(port, ATMEL_US_IER,
730 * This is either the end-of-break
731 * condition or we've received at
732 * least one character without RXBRK
733 * being set. In both cases, the next
734 * RXBRK will indicate start-of-break.
736 atmel_uart_writel(port, ATMEL_US_IDR,
738 status &= ~ATMEL_US_RXBRK;
739 atmel_port->break_active = 0;
743 atmel_buffer_rx_char(port, status, ch);
744 status = atmel_uart_readl(port, ATMEL_US_CSR);
747 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
751 * Transmit characters (called from tasklet with TXRDY interrupt
754 static void atmel_tx_chars(struct uart_port *port)
756 struct circ_buf *xmit = &port->state->xmit;
757 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
760 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
761 atmel_uart_write_char(port, port->x_char);
765 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
768 while (atmel_uart_readl(port, ATMEL_US_CSR) &
769 atmel_port->tx_done_mask) {
770 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
771 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
773 if (uart_circ_empty(xmit))
777 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
778 uart_write_wakeup(port);
780 if (!uart_circ_empty(xmit))
781 /* Enable interrupts */
782 atmel_uart_writel(port, ATMEL_US_IER,
783 atmel_port->tx_done_mask);
786 static void atmel_complete_tx_dma(void *arg)
788 struct atmel_uart_port *atmel_port = arg;
789 struct uart_port *port = &atmel_port->uart;
790 struct circ_buf *xmit = &port->state->xmit;
791 struct dma_chan *chan = atmel_port->chan_tx;
794 spin_lock_irqsave(&port->lock, flags);
797 dmaengine_terminate_all(chan);
798 xmit->tail += atmel_port->tx_len;
799 xmit->tail &= UART_XMIT_SIZE - 1;
801 port->icount.tx += atmel_port->tx_len;
803 spin_lock_irq(&atmel_port->lock_tx);
804 async_tx_ack(atmel_port->desc_tx);
805 atmel_port->cookie_tx = -EINVAL;
806 atmel_port->desc_tx = NULL;
807 spin_unlock_irq(&atmel_port->lock_tx);
809 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
810 uart_write_wakeup(port);
813 * xmit is a circular buffer so, if we have just send data from
814 * xmit->tail to the end of xmit->buf, now we have to transmit the
815 * remaining data from the beginning of xmit->buf to xmit->head.
817 if (!uart_circ_empty(xmit))
818 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
819 else if (atmel_uart_is_half_duplex(port)) {
821 * DMA done, re-enable TXEMPTY and signal that we can stop
822 * TX and start RX for RS485
824 atmel_port->hd_start_rx = true;
825 atmel_uart_writel(port, ATMEL_US_IER,
826 atmel_port->tx_done_mask);
829 spin_unlock_irqrestore(&port->lock, flags);
832 static void atmel_release_tx_dma(struct uart_port *port)
834 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
835 struct dma_chan *chan = atmel_port->chan_tx;
838 dmaengine_terminate_all(chan);
839 dma_release_channel(chan);
840 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
844 atmel_port->desc_tx = NULL;
845 atmel_port->chan_tx = NULL;
846 atmel_port->cookie_tx = -EINVAL;
850 * Called from tasklet with TXRDY interrupt is disabled.
852 static void atmel_tx_dma(struct uart_port *port)
854 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
855 struct circ_buf *xmit = &port->state->xmit;
856 struct dma_chan *chan = atmel_port->chan_tx;
857 struct dma_async_tx_descriptor *desc;
858 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
859 unsigned int tx_len, part1_len, part2_len, sg_len;
860 dma_addr_t phys_addr;
862 /* Make sure we have an idle channel */
863 if (atmel_port->desc_tx != NULL)
866 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
869 * Port xmit buffer is already mapped,
870 * and it is one page... Just adjust
871 * offsets and lengths. Since it is a circular buffer,
872 * we have to transmit till the end, and then the rest.
873 * Take the port lock to get a
874 * consistent xmit buffer state.
876 tx_len = CIRC_CNT_TO_END(xmit->head,
880 if (atmel_port->fifo_size) {
881 /* multi data mode */
882 part1_len = (tx_len & ~0x3); /* DWORD access */
883 part2_len = (tx_len & 0x3); /* BYTE access */
885 /* single data (legacy) mode */
887 part2_len = tx_len; /* BYTE access only */
890 sg_init_table(sgl, 2);
892 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
895 sg_dma_address(sg) = phys_addr;
896 sg_dma_len(sg) = part1_len;
898 phys_addr += part1_len;
903 sg_dma_address(sg) = phys_addr;
904 sg_dma_len(sg) = part2_len;
908 * save tx_len so atmel_complete_tx_dma() will increase
909 * xmit->tail correctly
911 atmel_port->tx_len = tx_len;
913 desc = dmaengine_prep_slave_sg(chan,
920 dev_err(port->dev, "Failed to send via dma!\n");
924 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
926 atmel_port->desc_tx = desc;
927 desc->callback = atmel_complete_tx_dma;
928 desc->callback_param = atmel_port;
929 atmel_port->cookie_tx = dmaengine_submit(desc);
932 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
933 uart_write_wakeup(port);
936 static int atmel_prepare_tx_dma(struct uart_port *port)
938 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
940 struct dma_slave_config config;
944 dma_cap_set(DMA_SLAVE, mask);
946 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
947 if (atmel_port->chan_tx == NULL)
949 dev_info(port->dev, "using %s for tx DMA transfers\n",
950 dma_chan_name(atmel_port->chan_tx));
952 spin_lock_init(&atmel_port->lock_tx);
953 sg_init_table(&atmel_port->sg_tx, 1);
954 /* UART circular tx buffer is an aligned page. */
955 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
956 sg_set_page(&atmel_port->sg_tx,
957 virt_to_page(port->state->xmit.buf),
959 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
960 nent = dma_map_sg(port->dev,
966 dev_dbg(port->dev, "need to release resource of dma\n");
969 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
970 sg_dma_len(&atmel_port->sg_tx),
971 port->state->xmit.buf,
972 &sg_dma_address(&atmel_port->sg_tx));
975 /* Configure the slave DMA */
976 memset(&config, 0, sizeof(config));
977 config.direction = DMA_MEM_TO_DEV;
978 config.dst_addr_width = (atmel_port->fifo_size) ?
979 DMA_SLAVE_BUSWIDTH_4_BYTES :
980 DMA_SLAVE_BUSWIDTH_1_BYTE;
981 config.dst_addr = port->mapbase + ATMEL_US_THR;
982 config.dst_maxburst = 1;
984 ret = dmaengine_slave_config(atmel_port->chan_tx,
987 dev_err(port->dev, "DMA tx slave configuration failed\n");
994 dev_err(port->dev, "TX channel not available, switch to pio\n");
995 atmel_port->use_dma_tx = 0;
996 if (atmel_port->chan_tx)
997 atmel_release_tx_dma(port);
1001 static void atmel_complete_rx_dma(void *arg)
1003 struct uart_port *port = arg;
1004 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1006 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1009 static void atmel_release_rx_dma(struct uart_port *port)
1011 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1012 struct dma_chan *chan = atmel_port->chan_rx;
1015 dmaengine_terminate_all(chan);
1016 dma_release_channel(chan);
1017 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1021 atmel_port->desc_rx = NULL;
1022 atmel_port->chan_rx = NULL;
1023 atmel_port->cookie_rx = -EINVAL;
1026 static void atmel_rx_from_dma(struct uart_port *port)
1028 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1029 struct tty_port *tport = &port->state->port;
1030 struct circ_buf *ring = &atmel_port->rx_ring;
1031 struct dma_chan *chan = atmel_port->chan_rx;
1032 struct dma_tx_state state;
1033 enum dma_status dmastat;
1037 /* Reset the UART timeout early so that we don't miss one */
1038 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1039 dmastat = dmaengine_tx_status(chan,
1040 atmel_port->cookie_rx,
1042 /* Restart a new tasklet if DMA status is error */
1043 if (dmastat == DMA_ERROR) {
1044 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1045 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1046 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1050 /* CPU claims ownership of RX DMA buffer */
1051 dma_sync_sg_for_cpu(port->dev,
1057 * ring->head points to the end of data already written by the DMA.
1058 * ring->tail points to the beginning of data to be read by the
1060 * The current transfer size should not be larger than the dma buffer
1063 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1064 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1066 * At this point ring->head may point to the first byte right after the
1067 * last byte of the dma buffer:
1068 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1070 * However ring->tail must always points inside the dma buffer:
1071 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1073 * Since we use a ring buffer, we have to handle the case
1074 * where head is lower than tail. In such a case, we first read from
1075 * tail to the end of the buffer then reset tail.
1077 if (ring->head < ring->tail) {
1078 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1080 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1082 port->icount.rx += count;
1085 /* Finally we read data from tail to head */
1086 if (ring->tail < ring->head) {
1087 count = ring->head - ring->tail;
1089 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1090 /* Wrap ring->head if needed */
1091 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1093 ring->tail = ring->head;
1094 port->icount.rx += count;
1097 /* USART retreives ownership of RX DMA buffer */
1098 dma_sync_sg_for_device(port->dev,
1104 * Drop the lock here since it might end up calling
1105 * uart_start(), which takes the lock.
1107 spin_unlock(&port->lock);
1108 tty_flip_buffer_push(tport);
1109 spin_lock(&port->lock);
1111 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1114 static int atmel_prepare_rx_dma(struct uart_port *port)
1116 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1117 struct dma_async_tx_descriptor *desc;
1118 dma_cap_mask_t mask;
1119 struct dma_slave_config config;
1120 struct circ_buf *ring;
1123 ring = &atmel_port->rx_ring;
1126 dma_cap_set(DMA_CYCLIC, mask);
1128 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1129 if (atmel_port->chan_rx == NULL)
1131 dev_info(port->dev, "using %s for rx DMA transfers\n",
1132 dma_chan_name(atmel_port->chan_rx));
1134 spin_lock_init(&atmel_port->lock_rx);
1135 sg_init_table(&atmel_port->sg_rx, 1);
1136 /* UART circular rx buffer is an aligned page. */
1137 BUG_ON(!PAGE_ALIGNED(ring->buf));
1138 sg_set_page(&atmel_port->sg_rx,
1139 virt_to_page(ring->buf),
1140 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1141 (unsigned long)ring->buf & ~PAGE_MASK);
1142 nent = dma_map_sg(port->dev,
1148 dev_dbg(port->dev, "need to release resource of dma\n");
1151 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1152 sg_dma_len(&atmel_port->sg_rx),
1154 &sg_dma_address(&atmel_port->sg_rx));
1157 /* Configure the slave DMA */
1158 memset(&config, 0, sizeof(config));
1159 config.direction = DMA_DEV_TO_MEM;
1160 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1161 config.src_addr = port->mapbase + ATMEL_US_RHR;
1162 config.src_maxburst = 1;
1164 ret = dmaengine_slave_config(atmel_port->chan_rx,
1167 dev_err(port->dev, "DMA rx slave configuration failed\n");
1171 * Prepare a cyclic dma transfer, assign 2 descriptors,
1172 * each one is half ring buffer size
1174 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1175 sg_dma_address(&atmel_port->sg_rx),
1176 sg_dma_len(&atmel_port->sg_rx),
1177 sg_dma_len(&atmel_port->sg_rx)/2,
1179 DMA_PREP_INTERRUPT);
1181 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1184 desc->callback = atmel_complete_rx_dma;
1185 desc->callback_param = port;
1186 atmel_port->desc_rx = desc;
1187 atmel_port->cookie_rx = dmaengine_submit(desc);
1192 dev_err(port->dev, "RX channel not available, switch to pio\n");
1193 atmel_port->use_dma_rx = 0;
1194 if (atmel_port->chan_rx)
1195 atmel_release_rx_dma(port);
1199 static void atmel_uart_timer_callback(unsigned long data)
1201 struct uart_port *port = (void *)data;
1202 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1204 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1205 tasklet_schedule(&atmel_port->tasklet_rx);
1206 mod_timer(&atmel_port->uart_timer,
1207 jiffies + uart_poll_timeout(port));
1212 * receive interrupt handler.
1215 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1219 if (atmel_use_pdc_rx(port)) {
1221 * PDC receive. Just schedule the tasklet and let it
1222 * figure out the details.
1224 * TODO: We're not handling error flags correctly at
1227 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1228 atmel_uart_writel(port, ATMEL_US_IDR,
1229 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1230 atmel_tasklet_schedule(atmel_port,
1231 &atmel_port->tasklet_rx);
1234 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1235 ATMEL_US_FRAME | ATMEL_US_PARE))
1236 atmel_pdc_rxerr(port, pending);
1239 if (atmel_use_dma_rx(port)) {
1240 if (pending & ATMEL_US_TIMEOUT) {
1241 atmel_uart_writel(port, ATMEL_US_IDR,
1243 atmel_tasklet_schedule(atmel_port,
1244 &atmel_port->tasklet_rx);
1248 /* Interrupt receive */
1249 if (pending & ATMEL_US_RXRDY)
1250 atmel_rx_chars(port);
1251 else if (pending & ATMEL_US_RXBRK) {
1253 * End of break detected. If it came along with a
1254 * character, atmel_rx_chars will handle it.
1256 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1257 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1258 atmel_port->break_active = 0;
1263 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1266 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1268 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1270 if (pending & atmel_port->tx_done_mask) {
1271 atmel_uart_writel(port, ATMEL_US_IDR,
1272 atmel_port->tx_done_mask);
1274 /* Start RX if flag was set and FIFO is empty */
1275 if (atmel_port->hd_start_rx) {
1276 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1277 & ATMEL_US_TXEMPTY))
1278 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1280 atmel_port->hd_start_rx = false;
1281 atmel_start_rx(port);
1284 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1289 * status flags interrupt handler.
1292 atmel_handle_status(struct uart_port *port, unsigned int pending,
1293 unsigned int status)
1295 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1296 unsigned int status_change;
1298 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1299 | ATMEL_US_CTSIC)) {
1300 status_change = status ^ atmel_port->irq_status_prev;
1301 atmel_port->irq_status_prev = status;
1303 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1304 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1305 /* TODO: All reads to CSR will clear these interrupts! */
1306 if (status_change & ATMEL_US_RI)
1308 if (status_change & ATMEL_US_DSR)
1310 if (status_change & ATMEL_US_DCD)
1311 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1312 if (status_change & ATMEL_US_CTS)
1313 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1315 wake_up_interruptible(&port->state->port.delta_msr_wait);
1323 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1325 struct uart_port *port = dev_id;
1326 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1327 unsigned int status, pending, mask, pass_counter = 0;
1329 spin_lock(&atmel_port->lock_suspended);
1332 status = atmel_get_lines_status(port);
1333 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1334 pending = status & mask;
1338 if (atmel_port->suspended) {
1339 atmel_port->pending |= pending;
1340 atmel_port->pending_status = status;
1341 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1346 atmel_handle_receive(port, pending);
1347 atmel_handle_status(port, pending, status);
1348 atmel_handle_transmit(port, pending);
1349 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1351 spin_unlock(&atmel_port->lock_suspended);
1353 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1356 static void atmel_release_tx_pdc(struct uart_port *port)
1358 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1359 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1361 dma_unmap_single(port->dev,
1368 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1370 static void atmel_tx_pdc(struct uart_port *port)
1372 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1373 struct circ_buf *xmit = &port->state->xmit;
1374 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1377 /* nothing left to transmit? */
1378 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1381 xmit->tail += pdc->ofs;
1382 xmit->tail &= UART_XMIT_SIZE - 1;
1384 port->icount.tx += pdc->ofs;
1387 /* more to transmit - setup next transfer */
1389 /* disable PDC transmit */
1390 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1392 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1393 dma_sync_single_for_device(port->dev,
1398 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1401 atmel_uart_writel(port, ATMEL_PDC_TPR,
1402 pdc->dma_addr + xmit->tail);
1403 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1404 /* re-enable PDC transmit */
1405 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1406 /* Enable interrupts */
1407 atmel_uart_writel(port, ATMEL_US_IER,
1408 atmel_port->tx_done_mask);
1410 if (atmel_uart_is_half_duplex(port)) {
1411 /* DMA done, stop TX, start RX for RS485 */
1412 atmel_start_rx(port);
1416 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1417 uart_write_wakeup(port);
1420 static int atmel_prepare_tx_pdc(struct uart_port *port)
1422 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1423 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1424 struct circ_buf *xmit = &port->state->xmit;
1426 pdc->buf = xmit->buf;
1427 pdc->dma_addr = dma_map_single(port->dev,
1431 pdc->dma_size = UART_XMIT_SIZE;
1437 static void atmel_rx_from_ring(struct uart_port *port)
1439 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1440 struct circ_buf *ring = &atmel_port->rx_ring;
1442 unsigned int status;
1444 while (ring->head != ring->tail) {
1445 struct atmel_uart_char c;
1447 /* Make sure c is loaded after head. */
1450 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1452 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1459 * note that the error handling code is
1460 * out of the main execution path
1462 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1463 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1464 if (status & ATMEL_US_RXBRK) {
1465 /* ignore side-effect */
1466 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1469 if (uart_handle_break(port))
1472 if (status & ATMEL_US_PARE)
1473 port->icount.parity++;
1474 if (status & ATMEL_US_FRAME)
1475 port->icount.frame++;
1476 if (status & ATMEL_US_OVRE)
1477 port->icount.overrun++;
1479 status &= port->read_status_mask;
1481 if (status & ATMEL_US_RXBRK)
1483 else if (status & ATMEL_US_PARE)
1485 else if (status & ATMEL_US_FRAME)
1490 if (uart_handle_sysrq_char(port, c.ch))
1493 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1497 * Drop the lock here since it might end up calling
1498 * uart_start(), which takes the lock.
1500 spin_unlock(&port->lock);
1501 tty_flip_buffer_push(&port->state->port);
1502 spin_lock(&port->lock);
1505 static void atmel_release_rx_pdc(struct uart_port *port)
1507 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1510 for (i = 0; i < 2; i++) {
1511 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1513 dma_unmap_single(port->dev,
1521 static void atmel_rx_from_pdc(struct uart_port *port)
1523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1524 struct tty_port *tport = &port->state->port;
1525 struct atmel_dma_buffer *pdc;
1526 int rx_idx = atmel_port->pdc_rx_idx;
1532 /* Reset the UART timeout early so that we don't miss one */
1533 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1535 pdc = &atmel_port->pdc_rx[rx_idx];
1536 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1539 /* If the PDC has switched buffers, RPR won't contain
1540 * any address within the current buffer. Since head
1541 * is unsigned, we just need a one-way comparison to
1544 * In this case, we just need to consume the entire
1545 * buffer and resubmit it for DMA. This will clear the
1546 * ENDRX bit as well, so that we can safely re-enable
1547 * all interrupts below.
1549 head = min(head, pdc->dma_size);
1551 if (likely(head != tail)) {
1552 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1553 pdc->dma_size, DMA_FROM_DEVICE);
1556 * head will only wrap around when we recycle
1557 * the DMA buffer, and when that happens, we
1558 * explicitly set tail to 0. So head will
1559 * always be greater than tail.
1561 count = head - tail;
1563 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1566 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1567 pdc->dma_size, DMA_FROM_DEVICE);
1569 port->icount.rx += count;
1574 * If the current buffer is full, we need to check if
1575 * the next one contains any additional data.
1577 if (head >= pdc->dma_size) {
1579 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1580 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1583 atmel_port->pdc_rx_idx = rx_idx;
1585 } while (head >= pdc->dma_size);
1588 * Drop the lock here since it might end up calling
1589 * uart_start(), which takes the lock.
1591 spin_unlock(&port->lock);
1592 tty_flip_buffer_push(tport);
1593 spin_lock(&port->lock);
1595 atmel_uart_writel(port, ATMEL_US_IER,
1596 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1599 static int atmel_prepare_rx_pdc(struct uart_port *port)
1601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1604 for (i = 0; i < 2; i++) {
1605 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1607 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1608 if (pdc->buf == NULL) {
1610 dma_unmap_single(port->dev,
1611 atmel_port->pdc_rx[0].dma_addr,
1614 kfree(atmel_port->pdc_rx[0].buf);
1616 atmel_port->use_pdc_rx = 0;
1619 pdc->dma_addr = dma_map_single(port->dev,
1623 pdc->dma_size = PDC_BUFFER_SIZE;
1627 atmel_port->pdc_rx_idx = 0;
1629 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1630 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1632 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1633 atmel_port->pdc_rx[1].dma_addr);
1634 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1640 * tasklet handling tty stuff outside the interrupt handler.
1642 static void atmel_tasklet_rx_func(unsigned long data)
1644 struct uart_port *port = (struct uart_port *)data;
1645 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1647 /* The interrupt handler does not take the lock */
1648 spin_lock(&port->lock);
1649 atmel_port->schedule_rx(port);
1650 spin_unlock(&port->lock);
1653 static void atmel_tasklet_tx_func(unsigned long data)
1655 struct uart_port *port = (struct uart_port *)data;
1656 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1658 /* The interrupt handler does not take the lock */
1659 spin_lock(&port->lock);
1660 atmel_port->schedule_tx(port);
1661 spin_unlock(&port->lock);
1664 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1665 struct platform_device *pdev)
1667 struct device_node *np = pdev->dev.of_node;
1668 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1671 /* DMA/PDC usage specification */
1672 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1673 if (of_property_read_bool(np, "dmas")) {
1674 atmel_port->use_dma_rx = true;
1675 atmel_port->use_pdc_rx = false;
1677 atmel_port->use_dma_rx = false;
1678 atmel_port->use_pdc_rx = true;
1681 atmel_port->use_dma_rx = false;
1682 atmel_port->use_pdc_rx = false;
1685 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1686 if (of_property_read_bool(np, "dmas")) {
1687 atmel_port->use_dma_tx = true;
1688 atmel_port->use_pdc_tx = false;
1690 atmel_port->use_dma_tx = false;
1691 atmel_port->use_pdc_tx = true;
1694 atmel_port->use_dma_tx = false;
1695 atmel_port->use_pdc_tx = false;
1699 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1700 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1701 atmel_port->use_dma_rx = false;
1702 atmel_port->use_dma_tx = false;
1707 static void atmel_init_rs485(struct uart_port *port,
1708 struct platform_device *pdev)
1710 struct device_node *np = pdev->dev.of_node;
1711 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1714 struct serial_rs485 *rs485conf = &port->rs485;
1716 /* rs485 properties */
1717 if (of_property_read_u32_array(np, "rs485-rts-delay",
1718 rs485_delay, 2) == 0) {
1719 rs485conf->delay_rts_before_send = rs485_delay[0];
1720 rs485conf->delay_rts_after_send = rs485_delay[1];
1721 rs485conf->flags = 0;
1724 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1725 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1727 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1729 rs485conf->flags |= SER_RS485_ENABLED;
1731 port->rs485 = pdata->rs485;
1736 static void atmel_set_ops(struct uart_port *port)
1738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1740 if (atmel_use_dma_rx(port)) {
1741 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1742 atmel_port->schedule_rx = &atmel_rx_from_dma;
1743 atmel_port->release_rx = &atmel_release_rx_dma;
1744 } else if (atmel_use_pdc_rx(port)) {
1745 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1746 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1747 atmel_port->release_rx = &atmel_release_rx_pdc;
1749 atmel_port->prepare_rx = NULL;
1750 atmel_port->schedule_rx = &atmel_rx_from_ring;
1751 atmel_port->release_rx = NULL;
1754 if (atmel_use_dma_tx(port)) {
1755 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1756 atmel_port->schedule_tx = &atmel_tx_dma;
1757 atmel_port->release_tx = &atmel_release_tx_dma;
1758 } else if (atmel_use_pdc_tx(port)) {
1759 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1760 atmel_port->schedule_tx = &atmel_tx_pdc;
1761 atmel_port->release_tx = &atmel_release_tx_pdc;
1763 atmel_port->prepare_tx = NULL;
1764 atmel_port->schedule_tx = &atmel_tx_chars;
1765 atmel_port->release_tx = NULL;
1770 * Get ip name usart or uart
1772 static void atmel_get_ip_name(struct uart_port *port)
1774 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1775 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1777 u32 usart, dbgu_uart, new_uart;
1778 /* ASCII decoding for IP version */
1779 usart = 0x55534152; /* USAR(T) */
1780 dbgu_uart = 0x44424755; /* DBGU */
1781 new_uart = 0x55415254; /* UART */
1784 * Only USART devices from at91sam9260 SOC implement fractional
1787 atmel_port->has_frac_baudrate = false;
1788 atmel_port->has_hw_timer = false;
1790 if (name == new_uart) {
1791 dev_dbg(port->dev, "Uart with hw timer");
1792 atmel_port->has_hw_timer = true;
1793 atmel_port->rtor = ATMEL_UA_RTOR;
1794 } else if (name == usart) {
1795 dev_dbg(port->dev, "Usart\n");
1796 atmel_port->has_frac_baudrate = true;
1797 atmel_port->has_hw_timer = true;
1798 atmel_port->rtor = ATMEL_US_RTOR;
1799 } else if (name == dbgu_uart) {
1800 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1802 /* fallback for older SoCs: use version field */
1803 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1808 dev_dbg(port->dev, "This version is usart\n");
1809 atmel_port->has_frac_baudrate = true;
1810 atmel_port->has_hw_timer = true;
1811 atmel_port->rtor = ATMEL_US_RTOR;
1815 dev_dbg(port->dev, "This version is uart\n");
1818 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1824 * Perform initialization and enable port for reception
1826 static int atmel_startup(struct uart_port *port)
1828 struct platform_device *pdev = to_platform_device(port->dev);
1829 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1833 * Ensure that no interrupts are enabled otherwise when
1834 * request_irq() is called we could get stuck trying to
1835 * handle an unexpected interrupt
1837 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1838 atmel_port->ms_irq_enabled = false;
1843 retval = request_irq(port->irq, atmel_interrupt,
1844 IRQF_SHARED | IRQF_COND_SUSPEND,
1845 dev_name(&pdev->dev), port);
1847 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1851 atomic_set(&atmel_port->tasklet_shutdown, 0);
1852 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1853 (unsigned long)port);
1854 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1855 (unsigned long)port);
1858 * Initialize DMA (if necessary)
1860 atmel_init_property(atmel_port, pdev);
1861 atmel_set_ops(port);
1863 if (atmel_port->prepare_rx) {
1864 retval = atmel_port->prepare_rx(port);
1866 atmel_set_ops(port);
1869 if (atmel_port->prepare_tx) {
1870 retval = atmel_port->prepare_tx(port);
1872 atmel_set_ops(port);
1876 * Enable FIFO when available
1878 if (atmel_port->fifo_size) {
1879 unsigned int txrdym = ATMEL_US_ONE_DATA;
1880 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1883 atmel_uart_writel(port, ATMEL_US_CR,
1888 if (atmel_use_dma_tx(port))
1889 txrdym = ATMEL_US_FOUR_DATA;
1891 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1892 if (atmel_port->rts_high &&
1893 atmel_port->rts_low)
1894 fmr |= ATMEL_US_FRTSC |
1895 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1896 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1898 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1901 /* Save current CSR for comparison in atmel_tasklet_func() */
1902 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1905 * Finally, enable the serial port
1907 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1908 /* enable xmit & rcvr */
1909 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1911 setup_timer(&atmel_port->uart_timer,
1912 atmel_uart_timer_callback,
1913 (unsigned long)port);
1915 if (atmel_use_pdc_rx(port)) {
1916 /* set UART timeout */
1917 if (!atmel_port->has_hw_timer) {
1918 mod_timer(&atmel_port->uart_timer,
1919 jiffies + uart_poll_timeout(port));
1920 /* set USART timeout */
1922 atmel_uart_writel(port, atmel_port->rtor,
1924 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1926 atmel_uart_writel(port, ATMEL_US_IER,
1927 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1929 /* enable PDC controller */
1930 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1931 } else if (atmel_use_dma_rx(port)) {
1932 /* set UART timeout */
1933 if (!atmel_port->has_hw_timer) {
1934 mod_timer(&atmel_port->uart_timer,
1935 jiffies + uart_poll_timeout(port));
1936 /* set USART timeout */
1938 atmel_uart_writel(port, atmel_port->rtor,
1940 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1942 atmel_uart_writel(port, ATMEL_US_IER,
1946 /* enable receive only */
1947 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1954 * Flush any TX data submitted for DMA. Called when the TX circular
1957 static void atmel_flush_buffer(struct uart_port *port)
1959 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1961 if (atmel_use_pdc_tx(port)) {
1962 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1963 atmel_port->pdc_tx.ofs = 0;
1966 * in uart_flush_buffer(), the xmit circular buffer has just
1967 * been cleared, so we have to reset tx_len accordingly.
1969 atmel_port->tx_len = 0;
1975 static void atmel_shutdown(struct uart_port *port)
1977 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1979 /* Disable modem control lines interrupts */
1980 atmel_disable_ms(port);
1982 /* Disable interrupts at device level */
1983 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1985 /* Prevent spurious interrupts from scheduling the tasklet */
1986 atomic_inc(&atmel_port->tasklet_shutdown);
1989 * Prevent any tasklets being scheduled during
1992 del_timer_sync(&atmel_port->uart_timer);
1994 /* Make sure that no interrupt is on the fly */
1995 synchronize_irq(port->irq);
1998 * Clear out any scheduled tasklets before
1999 * we destroy the buffers
2001 tasklet_kill(&atmel_port->tasklet_rx);
2002 tasklet_kill(&atmel_port->tasklet_tx);
2005 * Ensure everything is stopped and
2006 * disable port and break condition.
2008 atmel_stop_rx(port);
2009 atmel_stop_tx(port);
2011 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2014 * Shut-down the DMA.
2016 if (atmel_port->release_rx)
2017 atmel_port->release_rx(port);
2018 if (atmel_port->release_tx)
2019 atmel_port->release_tx(port);
2022 * Reset ring buffer pointers
2024 atmel_port->rx_ring.head = 0;
2025 atmel_port->rx_ring.tail = 0;
2028 * Free the interrupts
2030 free_irq(port->irq, port);
2032 atmel_flush_buffer(port);
2036 * Power / Clock management.
2038 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2039 unsigned int oldstate)
2041 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2046 * Enable the peripheral clock for this serial port.
2047 * This is called on uart_open() or a resume event.
2049 clk_prepare_enable(atmel_port->clk);
2051 /* re-enable interrupts if we disabled some on suspend */
2052 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2055 /* Back up the interrupt mask and disable all interrupts */
2056 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2057 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2060 * Disable the peripheral clock for this serial port.
2061 * This is called on uart_close() or a suspend event.
2063 clk_disable_unprepare(atmel_port->clk);
2066 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2071 * Change the port parameters
2073 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2074 struct ktermios *old)
2076 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2077 unsigned long flags;
2078 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2080 /* save the current mode register */
2081 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2083 /* reset the mode, clock divisor, parity, stop bits and data size */
2084 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2085 ATMEL_US_PAR | ATMEL_US_USMODE);
2087 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2090 switch (termios->c_cflag & CSIZE) {
2092 mode |= ATMEL_US_CHRL_5;
2095 mode |= ATMEL_US_CHRL_6;
2098 mode |= ATMEL_US_CHRL_7;
2101 mode |= ATMEL_US_CHRL_8;
2106 if (termios->c_cflag & CSTOPB)
2107 mode |= ATMEL_US_NBSTOP_2;
2110 if (termios->c_cflag & PARENB) {
2111 /* Mark or Space parity */
2112 if (termios->c_cflag & CMSPAR) {
2113 if (termios->c_cflag & PARODD)
2114 mode |= ATMEL_US_PAR_MARK;
2116 mode |= ATMEL_US_PAR_SPACE;
2117 } else if (termios->c_cflag & PARODD)
2118 mode |= ATMEL_US_PAR_ODD;
2120 mode |= ATMEL_US_PAR_EVEN;
2122 mode |= ATMEL_US_PAR_NONE;
2124 spin_lock_irqsave(&port->lock, flags);
2126 port->read_status_mask = ATMEL_US_OVRE;
2127 if (termios->c_iflag & INPCK)
2128 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2129 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2130 port->read_status_mask |= ATMEL_US_RXBRK;
2132 if (atmel_use_pdc_rx(port))
2133 /* need to enable error interrupts */
2134 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2137 * Characters to ignore
2139 port->ignore_status_mask = 0;
2140 if (termios->c_iflag & IGNPAR)
2141 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2142 if (termios->c_iflag & IGNBRK) {
2143 port->ignore_status_mask |= ATMEL_US_RXBRK;
2145 * If we're ignoring parity and break indicators,
2146 * ignore overruns too (for real raw support).
2148 if (termios->c_iflag & IGNPAR)
2149 port->ignore_status_mask |= ATMEL_US_OVRE;
2151 /* TODO: Ignore all characters if CREAD is set.*/
2153 /* update the per-port timeout */
2154 uart_update_timeout(port, termios->c_cflag, baud);
2157 * save/disable interrupts. The tty layer will ensure that the
2158 * transmitter is empty if requested by the caller, so there's
2159 * no need to wait for it here.
2161 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2162 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2164 /* disable receiver and transmitter */
2165 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2168 if (port->rs485.flags & SER_RS485_ENABLED) {
2169 atmel_uart_writel(port, ATMEL_US_TTGR,
2170 port->rs485.delay_rts_after_send);
2171 mode |= ATMEL_US_USMODE_RS485;
2172 } else if (termios->c_cflag & CRTSCTS) {
2173 /* RS232 with hardware handshake (RTS/CTS) */
2174 if (atmel_use_fifo(port) &&
2175 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2177 * with ATMEL_US_USMODE_HWHS set, the controller will
2178 * be able to drive the RTS pin high/low when the RX
2179 * FIFO is above RXFTHRES/below RXFTHRES2.
2180 * It will also disable the transmitter when the CTS
2182 * This mode is not activated if CTS pin is a GPIO
2183 * because in this case, the transmitter is always
2184 * disabled (there must be an internal pull-up
2185 * responsible for this behaviour).
2186 * If the RTS pin is a GPIO, the controller won't be
2187 * able to drive it according to the FIFO thresholds,
2188 * but it will be handled by the driver.
2190 mode |= ATMEL_US_USMODE_HWHS;
2193 * For platforms without FIFO, the flow control is
2194 * handled by the driver.
2196 mode |= ATMEL_US_USMODE_NORMAL;
2199 /* RS232 without hadware handshake */
2200 mode |= ATMEL_US_USMODE_NORMAL;
2203 /* set the mode, clock divisor, parity, stop bits and data size */
2204 atmel_uart_writel(port, ATMEL_US_MR, mode);
2207 * when switching the mode, set the RTS line state according to the
2208 * new mode, otherwise keep the former state
2210 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2211 unsigned int rts_state;
2213 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2214 /* let the hardware control the RTS line */
2215 rts_state = ATMEL_US_RTSDIS;
2217 /* force RTS line to low level */
2218 rts_state = ATMEL_US_RTSEN;
2221 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2225 * Set the baud rate:
2226 * Fractional baudrate allows to setup output frequency more
2227 * accurately. This feature is enabled only when using normal mode.
2228 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2229 * Currently, OVER is always set to 0 so we get
2230 * baudrate = selected clock / (16 * (CD + FP / 8))
2232 * 8 CD + FP = selected clock / (2 * baudrate)
2234 if (atmel_port->has_frac_baudrate &&
2235 (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
2236 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2238 fp = div & ATMEL_US_FP_MASK;
2240 cd = uart_get_divisor(port, baud);
2243 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2245 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2247 quot = cd | fp << ATMEL_US_FP_OFFSET;
2249 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2250 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2251 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2253 /* restore interrupts */
2254 atmel_uart_writel(port, ATMEL_US_IER, imr);
2256 /* CTS flow-control and modem-status interrupts */
2257 if (UART_ENABLE_MS(port, termios->c_cflag))
2258 atmel_enable_ms(port);
2260 atmel_disable_ms(port);
2262 spin_unlock_irqrestore(&port->lock, flags);
2265 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2267 if (termios->c_line == N_PPS) {
2268 port->flags |= UPF_HARDPPS_CD;
2269 spin_lock_irq(&port->lock);
2270 atmel_enable_ms(port);
2271 spin_unlock_irq(&port->lock);
2273 port->flags &= ~UPF_HARDPPS_CD;
2274 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2275 spin_lock_irq(&port->lock);
2276 atmel_disable_ms(port);
2277 spin_unlock_irq(&port->lock);
2283 * Return string describing the specified port
2285 static const char *atmel_type(struct uart_port *port)
2287 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2291 * Release the memory region(s) being used by 'port'.
2293 static void atmel_release_port(struct uart_port *port)
2295 struct platform_device *pdev = to_platform_device(port->dev);
2296 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2298 release_mem_region(port->mapbase, size);
2300 if (port->flags & UPF_IOREMAP) {
2301 iounmap(port->membase);
2302 port->membase = NULL;
2307 * Request the memory region(s) being used by 'port'.
2309 static int atmel_request_port(struct uart_port *port)
2311 struct platform_device *pdev = to_platform_device(port->dev);
2312 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2314 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2317 if (port->flags & UPF_IOREMAP) {
2318 port->membase = ioremap(port->mapbase, size);
2319 if (port->membase == NULL) {
2320 release_mem_region(port->mapbase, size);
2329 * Configure/autoconfigure the port.
2331 static void atmel_config_port(struct uart_port *port, int flags)
2333 if (flags & UART_CONFIG_TYPE) {
2334 port->type = PORT_ATMEL;
2335 atmel_request_port(port);
2340 * Verify the new serial_struct (for TIOCSSERIAL).
2342 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2345 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2347 if (port->irq != ser->irq)
2349 if (ser->io_type != SERIAL_IO_MEM)
2351 if (port->uartclk / 16 != ser->baud_base)
2353 if (port->mapbase != (unsigned long)ser->iomem_base)
2355 if (port->iobase != ser->port)
2362 #ifdef CONFIG_CONSOLE_POLL
2363 static int atmel_poll_get_char(struct uart_port *port)
2365 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2368 return atmel_uart_read_char(port);
2371 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2373 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2376 atmel_uart_write_char(port, ch);
2380 static const struct uart_ops atmel_pops = {
2381 .tx_empty = atmel_tx_empty,
2382 .set_mctrl = atmel_set_mctrl,
2383 .get_mctrl = atmel_get_mctrl,
2384 .stop_tx = atmel_stop_tx,
2385 .start_tx = atmel_start_tx,
2386 .stop_rx = atmel_stop_rx,
2387 .enable_ms = atmel_enable_ms,
2388 .break_ctl = atmel_break_ctl,
2389 .startup = atmel_startup,
2390 .shutdown = atmel_shutdown,
2391 .flush_buffer = atmel_flush_buffer,
2392 .set_termios = atmel_set_termios,
2393 .set_ldisc = atmel_set_ldisc,
2395 .release_port = atmel_release_port,
2396 .request_port = atmel_request_port,
2397 .config_port = atmel_config_port,
2398 .verify_port = atmel_verify_port,
2399 .pm = atmel_serial_pm,
2400 #ifdef CONFIG_CONSOLE_POLL
2401 .poll_get_char = atmel_poll_get_char,
2402 .poll_put_char = atmel_poll_put_char,
2407 * Configure the port from the platform device resource info.
2409 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2410 struct platform_device *pdev)
2413 struct uart_port *port = &atmel_port->uart;
2414 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2416 atmel_init_property(atmel_port, pdev);
2417 atmel_set_ops(port);
2419 atmel_init_rs485(port, pdev);
2421 port->iotype = UPIO_MEM;
2422 port->flags = UPF_BOOT_AUTOCONF;
2423 port->ops = &atmel_pops;
2425 port->dev = &pdev->dev;
2426 port->mapbase = pdev->resource[0].start;
2427 port->irq = pdev->resource[1].start;
2428 port->rs485_config = atmel_config_rs485;
2430 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2432 if (pdata && pdata->regs) {
2433 /* Already mapped by setup code */
2434 port->membase = pdata->regs;
2436 port->flags |= UPF_IOREMAP;
2437 port->membase = NULL;
2440 /* for console, the clock could already be configured */
2441 if (!atmel_port->clk) {
2442 atmel_port->clk = clk_get(&pdev->dev, "usart");
2443 if (IS_ERR(atmel_port->clk)) {
2444 ret = PTR_ERR(atmel_port->clk);
2445 atmel_port->clk = NULL;
2448 ret = clk_prepare_enable(atmel_port->clk);
2450 clk_put(atmel_port->clk);
2451 atmel_port->clk = NULL;
2454 port->uartclk = clk_get_rate(atmel_port->clk);
2455 clk_disable_unprepare(atmel_port->clk);
2456 /* only enable clock when USART is in use */
2459 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2460 if (port->rs485.flags & SER_RS485_ENABLED)
2461 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2462 else if (atmel_use_pdc_tx(port)) {
2463 port->fifosize = PDC_BUFFER_SIZE;
2464 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2466 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2472 struct platform_device *atmel_default_console_device; /* the serial console device */
2474 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2475 static void atmel_console_putchar(struct uart_port *port, int ch)
2477 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2479 atmel_uart_write_char(port, ch);
2483 * Interrupts are disabled on entering
2485 static void atmel_console_write(struct console *co, const char *s, u_int count)
2487 struct uart_port *port = &atmel_ports[co->index].uart;
2488 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2489 unsigned int status, imr;
2490 unsigned int pdc_tx;
2493 * First, save IMR and then disable interrupts
2495 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2496 atmel_uart_writel(port, ATMEL_US_IDR,
2497 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2499 /* Store PDC transmit status and disable it */
2500 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2501 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2503 /* Make sure that tx path is actually able to send characters */
2504 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2506 uart_console_write(port, s, count, atmel_console_putchar);
2509 * Finally, wait for transmitter to become empty
2513 status = atmel_uart_readl(port, ATMEL_US_CSR);
2514 } while (!(status & ATMEL_US_TXRDY));
2516 /* Restore PDC transmit status */
2518 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2520 /* set interrupts back the way they were */
2521 atmel_uart_writel(port, ATMEL_US_IER, imr);
2525 * If the port was already initialised (eg, by a boot loader),
2526 * try to determine the current setup.
2528 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2529 int *parity, int *bits)
2531 unsigned int mr, quot;
2534 * If the baud rate generator isn't running, the port wasn't
2535 * initialized by the boot loader.
2537 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2541 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2542 if (mr == ATMEL_US_CHRL_8)
2547 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2548 if (mr == ATMEL_US_PAR_EVEN)
2550 else if (mr == ATMEL_US_PAR_ODD)
2554 * The serial core only rounds down when matching this to a
2555 * supported baud rate. Make sure we don't end up slightly
2556 * lower than one of those, as it would make us fall through
2557 * to a much lower baud rate than we really want.
2559 *baud = port->uartclk / (16 * (quot - 1));
2562 static int __init atmel_console_setup(struct console *co, char *options)
2565 struct uart_port *port = &atmel_ports[co->index].uart;
2571 if (port->membase == NULL) {
2572 /* Port not initialized yet - delay setup */
2576 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2580 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2581 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2582 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2585 uart_parse_options(options, &baud, &parity, &bits, &flow);
2587 atmel_console_get_options(port, &baud, &parity, &bits);
2589 return uart_set_options(port, co, baud, parity, bits, flow);
2592 static struct uart_driver atmel_uart;
2594 static struct console atmel_console = {
2595 .name = ATMEL_DEVICENAME,
2596 .write = atmel_console_write,
2597 .device = uart_console_device,
2598 .setup = atmel_console_setup,
2599 .flags = CON_PRINTBUFFER,
2601 .data = &atmel_uart,
2604 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2607 * Early console initialization (before VM subsystem initialized).
2609 static int __init atmel_console_init(void)
2612 if (atmel_default_console_device) {
2613 struct atmel_uart_data *pdata =
2614 dev_get_platdata(&atmel_default_console_device->dev);
2615 int id = pdata->num;
2616 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2618 atmel_port->backup_imr = 0;
2619 atmel_port->uart.line = id;
2621 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2622 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2625 register_console(&atmel_console);
2631 console_initcall(atmel_console_init);
2634 * Late console initialization.
2636 static int __init atmel_late_console_init(void)
2638 if (atmel_default_console_device
2639 && !(atmel_console.flags & CON_ENABLED))
2640 register_console(&atmel_console);
2645 core_initcall(atmel_late_console_init);
2647 static inline bool atmel_is_console_port(struct uart_port *port)
2649 return port->cons && port->cons->index == port->line;
2653 #define ATMEL_CONSOLE_DEVICE NULL
2655 static inline bool atmel_is_console_port(struct uart_port *port)
2661 static struct uart_driver atmel_uart = {
2662 .owner = THIS_MODULE,
2663 .driver_name = "atmel_serial",
2664 .dev_name = ATMEL_DEVICENAME,
2665 .major = SERIAL_ATMEL_MAJOR,
2666 .minor = MINOR_START,
2667 .nr = ATMEL_MAX_UART,
2668 .cons = ATMEL_CONSOLE_DEVICE,
2672 static bool atmel_serial_clk_will_stop(void)
2674 #ifdef CONFIG_ARCH_AT91
2675 return at91_suspend_entering_slow_clock();
2681 static int atmel_serial_suspend(struct platform_device *pdev,
2684 struct uart_port *port = platform_get_drvdata(pdev);
2685 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2687 if (atmel_is_console_port(port) && console_suspend_enabled) {
2688 /* Drain the TX shifter */
2689 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2694 /* we can not wake up if we're running on slow clock */
2695 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2696 if (atmel_serial_clk_will_stop()) {
2697 unsigned long flags;
2699 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2700 atmel_port->suspended = true;
2701 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2702 device_set_wakeup_enable(&pdev->dev, 0);
2705 uart_suspend_port(&atmel_uart, port);
2710 static int atmel_serial_resume(struct platform_device *pdev)
2712 struct uart_port *port = platform_get_drvdata(pdev);
2713 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2714 unsigned long flags;
2716 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2717 if (atmel_port->pending) {
2718 atmel_handle_receive(port, atmel_port->pending);
2719 atmel_handle_status(port, atmel_port->pending,
2720 atmel_port->pending_status);
2721 atmel_handle_transmit(port, atmel_port->pending);
2722 atmel_port->pending = 0;
2724 atmel_port->suspended = false;
2725 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2727 uart_resume_port(&atmel_uart, port);
2728 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2733 #define atmel_serial_suspend NULL
2734 #define atmel_serial_resume NULL
2737 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2738 struct platform_device *pdev)
2740 atmel_port->fifo_size = 0;
2741 atmel_port->rts_low = 0;
2742 atmel_port->rts_high = 0;
2744 if (of_property_read_u32(pdev->dev.of_node,
2746 &atmel_port->fifo_size))
2749 if (!atmel_port->fifo_size)
2752 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2753 atmel_port->fifo_size = 0;
2754 dev_err(&pdev->dev, "Invalid FIFO size\n");
2759 * 0 <= rts_low <= rts_high <= fifo_size
2760 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2761 * to flush their internal TX FIFO, commonly up to 16 data, before
2762 * actually stopping to send new data. So we try to set the RTS High
2763 * Threshold to a reasonably high value respecting this 16 data
2764 * empirical rule when possible.
2766 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2767 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2768 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2769 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2771 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2772 atmel_port->fifo_size);
2773 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2774 atmel_port->rts_high);
2775 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2776 atmel_port->rts_low);
2779 static int atmel_serial_probe(struct platform_device *pdev)
2781 struct atmel_uart_port *atmel_port;
2782 struct device_node *np = pdev->dev.of_node;
2783 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2788 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2791 ret = of_alias_get_id(np, "serial");
2797 /* port id not found in platform data nor device-tree aliases:
2798 * auto-enumerate it */
2799 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2801 if (ret >= ATMEL_MAX_UART) {
2806 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2807 /* port already in use */
2812 atmel_port = &atmel_ports[ret];
2813 atmel_port->backup_imr = 0;
2814 atmel_port->uart.line = ret;
2815 atmel_serial_probe_fifos(atmel_port, pdev);
2817 atomic_set(&atmel_port->tasklet_shutdown, 0);
2818 spin_lock_init(&atmel_port->lock_suspended);
2820 ret = atmel_init_port(atmel_port, pdev);
2824 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2825 if (IS_ERR(atmel_port->gpios)) {
2826 ret = PTR_ERR(atmel_port->gpios);
2830 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2832 data = kmalloc(sizeof(struct atmel_uart_char)
2833 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2835 goto err_alloc_ring;
2836 atmel_port->rx_ring.buf = data;
2839 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2841 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2845 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2846 if (atmel_is_console_port(&atmel_port->uart)
2847 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2849 * The serial core enabled the clock for us, so undo
2850 * the clk_prepare_enable() in atmel_console_setup()
2852 clk_disable_unprepare(atmel_port->clk);
2856 device_init_wakeup(&pdev->dev, 1);
2857 platform_set_drvdata(pdev, atmel_port);
2860 * The peripheral clock has been disabled by atmel_init_port():
2861 * enable it before accessing I/O registers
2863 clk_prepare_enable(atmel_port->clk);
2865 if (rs485_enabled) {
2866 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2867 ATMEL_US_USMODE_NORMAL);
2868 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2873 * Get port name of usart or uart
2875 atmel_get_ip_name(&atmel_port->uart);
2878 * The peripheral clock can now safely be disabled till the port
2881 clk_disable_unprepare(atmel_port->clk);
2886 kfree(atmel_port->rx_ring.buf);
2887 atmel_port->rx_ring.buf = NULL;
2889 if (!atmel_is_console_port(&atmel_port->uart)) {
2890 clk_put(atmel_port->clk);
2891 atmel_port->clk = NULL;
2894 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2900 * Even if the driver is not modular, it makes sense to be able to
2901 * unbind a device: there can be many bound devices, and there are
2902 * situations where dynamic binding and unbinding can be useful.
2904 * For example, a connected device can require a specific firmware update
2905 * protocol that needs bitbanging on IO lines, but use the regular serial
2906 * port in the normal case.
2908 static int atmel_serial_remove(struct platform_device *pdev)
2910 struct uart_port *port = platform_get_drvdata(pdev);
2911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2914 tasklet_kill(&atmel_port->tasklet_rx);
2915 tasklet_kill(&atmel_port->tasklet_tx);
2917 device_init_wakeup(&pdev->dev, 0);
2919 ret = uart_remove_one_port(&atmel_uart, port);
2921 kfree(atmel_port->rx_ring.buf);
2923 /* "port" is allocated statically, so we shouldn't free it */
2925 clear_bit(port->line, atmel_ports_in_use);
2927 clk_put(atmel_port->clk);
2928 atmel_port->clk = NULL;
2933 static struct platform_driver atmel_serial_driver = {
2934 .probe = atmel_serial_probe,
2935 .remove = atmel_serial_remove,
2936 .suspend = atmel_serial_suspend,
2937 .resume = atmel_serial_resume,
2939 .name = "atmel_usart",
2940 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2944 static int __init atmel_serial_init(void)
2948 ret = uart_register_driver(&atmel_uart);
2952 ret = platform_driver_register(&atmel_serial_driver);
2954 uart_unregister_driver(&atmel_uart);
2958 device_initcall(atmel_serial_init);