x86/intel: force tsc to be reliable on Cherrytrail

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 9f2c6fc..c5ec676 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -131,6 +131,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
        /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
        if (c->x86 == 6) {
                switch (c->x86_model) {
+               case 0x4c:      /* CherryView */
                case 0x37:      /* ValleyView */
                        set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
                case 0x27:      /* Penwell */