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pinctrl: tegra20: Provide CDEV1/2 clock muxes
authorDmitry Osipenko <digetx@gmail.com>
Thu, 3 May 2018 22:55:34 +0000 (01:55 +0300)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 16 May 2018 12:21:32 +0000 (14:21 +0200)
Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
that main clk-controller driver could get an actual parent clock for the
CDEV1/2 clocks.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/tegra/pinctrl-tegra.c
drivers/pinctrl/tegra/pinctrl-tegra.h
drivers/pinctrl/tegra/pinctrl-tegra20.c

index 72c718e..49c7c14 100644 (file)
 #include "../pinctrl-utils.h"
 #include "pinctrl-tegra.h"
 
-struct tegra_pmx {
-       struct device *dev;
-       struct pinctrl_dev *pctl;
-
-       const struct tegra_pinctrl_soc_data *soc;
-       const char **group_pins;
-
-       int nbanks;
-       void __iomem **regs;
-};
-
 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
 {
        return readl(pmx->regs[bank] + reg);
index 33b17cb..aa33c20 100644 (file)
 #ifndef __PINMUX_TEGRA_H__
 #define __PINMUX_TEGRA_H__
 
+struct tegra_pmx {
+       struct device *dev;
+       struct pinctrl_dev *pctl;
+
+       const struct tegra_pinctrl_soc_data *soc;
+       const char **group_pins;
+
+       int nbanks;
+       void __iomem **regs;
+};
+
 enum tegra_pinconf_param {
        /* argument: tegra_pinconf_pull */
        TEGRA_PINCONF_PARAM_PULL,
index 7e38ee9..b6dd939 100644 (file)
@@ -19,6 +19,7 @@
  * more details.
  */
 
+#include <linux/clk-provider.h>
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
@@ -2231,9 +2232,36 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
        .drvtype_in_mux = false,
 };
 
+static const char *cdev1_parents[] = {
+       "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
+};
+
+static const char *cdev2_parents[] = {
+       "dev2_osc_div", "hclk", "pclk", "pll_p_out4",
+};
+
+static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
+{
+       struct tegra_pmx *pmx = platform_get_drvdata(pdev);
+
+       clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
+                        pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
+
+       clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
+                        pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
+}
+
 static int tegra20_pinctrl_probe(struct platform_device *pdev)
 {
-       return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
+       int err;
+
+       err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
+       if (err)
+               return err;
+
+       tegra20_pinctrl_register_clock_muxes(pdev);
+
+       return 0;
 }
 
 static const struct of_device_id tegra20_pinctrl_of_match[] = {