1 /****************************************************************************
2 ****************************************************************************
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
10 ****************************************************************************
11 ****************************************************************************/
12 #ifndef __ASM_ARCH_DMA_H
13 #define __ASM_ARCH_DMA_H
15 #define OMAP_DMA_BASE (0xfffed800)
16 #define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
17 #define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
18 #define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
19 #define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
20 #define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
21 #define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
22 #define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
23 #define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
24 #define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
25 #define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
26 #define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
27 #define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
28 #define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
29 #define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
30 #define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
31 #define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
32 #define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
33 #define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
34 #define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
35 #define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
37 #define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
38 #define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
39 #define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
40 #define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
41 #define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
42 #define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
43 #define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
44 #define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
45 #define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
46 #define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
47 #define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
48 #define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
49 #define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
50 #define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
51 #define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
52 #define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
54 #define OMAP_LOGICAL_DMA_CH_COUNT 32
56 #define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
57 #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
58 #define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
59 #define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
60 #define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
61 #define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
62 #define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
63 #define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
64 #define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
65 #define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
66 #define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
67 #define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
68 #define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
70 #define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
71 #define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
72 #define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
73 #define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
74 #define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
75 #define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
76 #define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
77 #define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
79 #define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
80 #define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
81 #define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
82 #define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
83 #define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
85 #define OMAP_DMA_NO_DEVICE 0
86 #define OMAP_DMA_MCSI1_TX 1
87 #define OMAP_DMA_MCSI1_RX 2
88 #define OMAP_DMA_I2C_RX 3
89 #define OMAP_DMA_I2C_TX 4
90 #define OMAP_DMA_EXT_NDMA_REQ 5
91 #define OMAP_DMA_EXT_NDMA_REQ2 6
92 #define OMAP_DMA_UWIRE_TX 7
93 #define OMAP_DMA_MCBSP1_TX 8
94 #define OMAP_DMA_MCBSP1_RX 9
95 #define OMAP_DMA_MCBSP3_TX 10
96 #define OMAP_DMA_MCBSP3_RX 11
97 #define OMAP_DMA_UART1_TX 12
98 #define OMAP_DMA_UART1_RX 13
99 #define OMAP_DMA_UART2_TX 14
100 #define OMAP_DMA_UART2_RX 15
101 #define OMAP_DMA_MCBSP2_TX 16
102 #define OMAP_DMA_MCBSP2_RX 17
103 #define OMAP_DMA_UART3_TX 18
104 #define OMAP_DMA_UART3_RX 19
105 #define OMAP_DMA_CAMERA_IF_RX 20
106 #define OMAP_DMA_MMC_TX 21
107 #define OMAP_DMA_MMC_RX 22
108 #define OMAP_DMA_NAND 23
109 #define OMAP_DMA_IRQ_LCD_LINE 24
110 #define OMAP_DMA_MEMORY_STICK 25
111 #define OMAP_DMA_USB_W2FC_RX0 26
112 #define OMAP_DMA_USB_W2FC_RX1 27
113 #define OMAP_DMA_USB_W2FC_RX2 28
114 #define OMAP_DMA_USB_W2FC_TX0 29
115 #define OMAP_DMA_USB_W2FC_TX1 30
116 #define OMAP_DMA_USB_W2FC_TX2 31
118 #define OMAP_DMA_CRYPTO_DES_IN 32
119 #define OMAP_DMA_SPI_TX 33
120 #define OMAP_DMA_SPI_RX 34
121 #define OMAP_DMA_CRYPTO_HASH 35
122 #define OMAP_DMA_CCP_ATTN 36
123 #define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
124 #define OMAP_DMA_CMT_APE_TX_CHAN_0 38
125 #define OMAP_DMA_CMT_APE_RV_CHAN_0 39
126 #define OMAP_DMA_CMT_APE_TX_CHAN_1 40
127 #define OMAP_DMA_CMT_APE_RV_CHAN_1 41
128 #define OMAP_DMA_CMT_APE_TX_CHAN_2 42
129 #define OMAP_DMA_CMT_APE_RV_CHAN_2 43
130 #define OMAP_DMA_CMT_APE_TX_CHAN_3 44
131 #define OMAP_DMA_CMT_APE_RV_CHAN_3 45
132 #define OMAP_DMA_CMT_APE_TX_CHAN_4 46
133 #define OMAP_DMA_CMT_APE_RV_CHAN_4 47
134 #define OMAP_DMA_CMT_APE_TX_CHAN_5 48
135 #define OMAP_DMA_CMT_APE_RV_CHAN_5 49
136 #define OMAP_DMA_CMT_APE_TX_CHAN_6 50
137 #define OMAP_DMA_CMT_APE_RV_CHAN_6 51
138 #define OMAP_DMA_CMT_APE_TX_CHAN_7 52
139 #define OMAP_DMA_CMT_APE_RV_CHAN_7 53
140 #define OMAP_DMA_MMC2_TX 54
141 #define OMAP_DMA_MMC2_RX 55
142 #define OMAP_DMA_CRYPTO_DES_OUT 56
144 #define OMAP24XX_DMA_NO_DEVICE 0
145 #define OMAP24XX_DMA_XTI_DMA 1
146 #define OMAP24XX_DMA_EXT_DMAREQ0 2
147 #define OMAP24XX_DMA_EXT_DMAREQ1 3
148 #define OMAP24XX_DMA_GPMC 4
149 #define OMAP24XX_DMA_GFX 5
150 #define OMAP24XX_DMA_DSS 6
151 #define OMAP24XX_DMA_VLYNQ_TX 7
152 #define OMAP24XX_DMA_CWT 8
153 #define OMAP24XX_DMA_AES_TX 9
154 #define OMAP24XX_DMA_AES_RX 10
155 #define OMAP24XX_DMA_DES_TX 11
156 #define OMAP24XX_DMA_DES_RX 12
157 #define OMAP24XX_DMA_SHA1MD5_RX 13
158 #define OMAP24XX_DMA_EXT_DMAREQ2 14
159 #define OMAP24XX_DMA_EXT_DMAREQ3 15
160 #define OMAP24XX_DMA_EXT_DMAREQ4 16
161 #define OMAP24XX_DMA_EAC_AC_RD 17
162 #define OMAP24XX_DMA_EAC_AC_WR 18
163 #define OMAP24XX_DMA_EAC_MD_UL_RD 19
164 #define OMAP24XX_DMA_EAC_MD_UL_WR 20
165 #define OMAP24XX_DMA_EAC_MD_DL_RD 21
166 #define OMAP24XX_DMA_EAC_MD_DL_WR 22
167 #define OMAP24XX_DMA_EAC_BT_UL_RD 23
168 #define OMAP24XX_DMA_EAC_BT_UL_WR 24
169 #define OMAP24XX_DMA_EAC_BT_DL_RD 25
170 #define OMAP24XX_DMA_EAC_BT_DL_WR 26
171 #define OMAP24XX_DMA_I2C1_TX 27
172 #define OMAP24XX_DMA_I2C1_RX 28
173 #define OMAP24XX_DMA_I2C2_TX 29
174 #define OMAP24XX_DMA_I2C2_RX 30
175 #define OMAP24XX_DMA_MCBSP1_TX 31
176 #define OMAP24XX_DMA_MCBSP1_RX 32
177 #define OMAP24XX_DMA_MCBSP2_TX 33
178 #define OMAP24XX_DMA_MCBSP2_RX 34
179 #define OMAP24XX_DMA_SPI1_TX0 35
180 #define OMAP24XX_DMA_SPI1_RX0 36
181 #define OMAP24XX_DMA_SPI1_TX1 37
182 #define OMAP24XX_DMA_SPI1_RX1 38
183 #define OMAP24XX_DMA_SPI1_TX2 39
184 #define OMAP24XX_DMA_SPI1_RX2 40
185 #define OMAP24XX_DMA_SPI1_TX3 41
186 #define OMAP24XX_DMA_SPI1_RX3 42
187 #define OMAP24XX_DMA_SPI2_TX0 43
188 #define OMAP24XX_DMA_SPI2_RX0 44
189 #define OMAP24XX_DMA_SPI2_TX1 45
190 #define OMAP24XX_DMA_SPI2_RX1 46
192 #define OMAP24XX_DMA_UART1_TX 49
193 #define OMAP24XX_DMA_UART1_RX 50
194 #define OMAP24XX_DMA_UART2_TX 51
195 #define OMAP24XX_DMA_UART2_RX 52
196 #define OMAP24XX_DMA_UART3_TX 53
197 #define OMAP24XX_DMA_UART3_RX 54
198 #define OMAP24XX_DMA_USB_W2FC_TX0 55
199 #define OMAP24XX_DMA_USB_W2FC_RX0 56
200 #define OMAP24XX_DMA_USB_W2FC_TX1 57
201 #define OMAP24XX_DMA_USB_W2FC_RX1 58
202 #define OMAP24XX_DMA_USB_W2FC_TX2 59
203 #define OMAP24XX_DMA_USB_W2FC_RX2 60
204 #define OMAP24XX_DMA_MMC1_TX 61
205 #define OMAP24XX_DMA_MMC1_RX 62
206 #define OMAP24XX_DMA_MS 63
207 #define OMAP24XX_DMA_EXT_DMAREQ5 64
209 #define OMAP1510_DMA_LCD_BASE (0xfffedb00)
210 #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
211 #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
212 #define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
213 #define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
214 #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
216 #define OMAP1610_DMA_LCD_BASE (0xfffee300)
217 #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
218 #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
219 #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
220 #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
221 #define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
222 #define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
223 #define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
224 #define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
225 #define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
226 #define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
227 #define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
228 #define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
229 #define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
230 #define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
231 #define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
232 #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
233 #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
235 #define OMAP1_DMA_TOUT_IRQ (1 << 0)
236 #define OMAP_DMA_DROP_IRQ (1 << 1)
237 #define OMAP_DMA_HALF_IRQ (1 << 2)
238 #define OMAP_DMA_FRAME_IRQ (1 << 3)
239 #define OMAP_DMA_LAST_IRQ (1 << 4)
240 #define OMAP_DMA_BLOCK_IRQ (1 << 5)
241 #define OMAP1_DMA_SYNC_IRQ (1 << 6)
242 #define OMAP2_DMA_PKT_IRQ (1 << 7)
243 #define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
244 #define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
245 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
246 #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
248 #define OMAP_DMA_DATA_TYPE_S8 0x00
249 #define OMAP_DMA_DATA_TYPE_S16 0x01
250 #define OMAP_DMA_DATA_TYPE_S32 0x02
252 #define OMAP_DMA_SYNC_ELEMENT 0x00
253 #define OMAP_DMA_SYNC_FRAME 0x01
254 #define OMAP_DMA_SYNC_BLOCK 0x02
256 #define OMAP_DMA_PORT_EMIFF 0x00
257 #define OMAP_DMA_PORT_EMIFS 0x01
258 #define OMAP_DMA_PORT_OCP_T1 0x02
259 #define OMAP_DMA_PORT_TIPB 0x03
260 #define OMAP_DMA_PORT_OCP_T2 0x04
261 #define OMAP_DMA_PORT_MPUI 0x05
263 #define OMAP_DMA_AMODE_CONSTANT 0x00
264 #define OMAP_DMA_AMODE_POST_INC 0x01
265 #define OMAP_DMA_AMODE_SINGLE_IDX 0x02
266 #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
270 OMAP_LCD_DMA_B1_BOTTOM,
272 OMAP_LCD_DMA_B2_BOTTOM
275 enum omap_dma_burst_mode {
276 OMAP_DMA_DATA_BURST_DIS = 0,
277 OMAP_DMA_DATA_BURST_4,
278 OMAP_DMA_DATA_BURST_8,
279 OMAP_DMA_DATA_BURST_16,
282 enum omap_dma_color_mode {
283 OMAP_DMA_COLOR_DIS = 0,
284 OMAP_DMA_CONSTANT_FILL,
285 OMAP_DMA_TRANSPARENT_COPY
288 enum omap_dma_write_mode {
289 OMAP_DMA_WRITE_NON_POSTED = 0,
290 OMAP_DMA_WRITE_POSTED,
291 OMAP_DMA_WRITE_LAST_NON_POSTED
294 struct omap_dma_channel_params {
301 unsigned long src_start;
307 unsigned long dst_start;
313 int src_or_dst_synch;