7 IRR
\81F
\83C
\83\93\83^
\83\89\83v
\83g
\83\8a\83N
\83G
\83X
\83g
\83\8c\83W
\83X
\83^
\r
8 .IRQ
\83s
\83\93\82Ì
\8fó
\91Ô
\82ð
\95\
\82·
\81B
\83|
\81[
\83g
\82ð
\93Ç
\82ñ
\82¾
\82Æ
\82«
\82É
\81AIRR
\82É
\82È
\82é
\82©ISR
\82É
\82È
\82é
\82©
\82Í
\81AOCW3
\82Å
\91I
\91ð
\82·
\82é
\81B
\r
9 .1
\82É
\82È
\82Á
\82Ä
\82¢
\82é
\83r
\83b
\83g
\82Í
\81A
\8c»
\8dÝ
\97v
\8b\81\82ª
\97\88\82Ä
\82¢
\82é
\81i
\82à
\82µ
\82
\82Í
\8f\88\97\9d\92\86\82Ì
\81j
\8a\84\82è
\8d\9e\82Ý
\81B
\r
10 ISR
\81F
\83C
\83\93\83T
\81[
\83r
\83X
\83\8c\83W
\83X
\83^
\r
11 .
\8c»
\8dÝ
\8f\88\97\9d\92\86\82Ì
\8a\84\82è
\8d\9e\82Ý
\82ª
\82Ç
\82ê
\82Å
\82 \82é
\82©
\82ð
\8e¦
\82·
\81B
\83|
\81[
\83g
\82ð
\93Ç
\82ñ
\82¾
\82Æ
\82«
\82É
\81AIRR
\82É
\82È
\82é
\82©ISR
\82É
\82È
\82é
\82©
\82Í
\81AOCW3
\82Å
\91I
\91ð
\82·
\82é
\81B
\r
12 .1
\82É
\82È
\82Á
\82Ä
\82¢
\82é
\83r
\83b
\83g
\82Í
\81A
\8c»
\8dÝ
\8f\88\97\9d\92\86\82Ì
\8a\84\82è
\8d\9e\82Ý
\81B
\8f\88\97\9d\92\86\82Æ
\82¢
\82¤
\82Ì
\82Í
\81ACPU
\82É
\91Î
\82µ
\82ÄINT
\96½
\97ß
\82ð
\94
\8ds
\82µ
\82½
\82ª
\81AEOI
\81i
\8a\84\82è
\8d\9e\82Ý
\8fI
\97¹
\96½
\97ß
\81j
\82ð
\8eó
\82¯
\8eæ
\82Á
\82Ä
\82¢
\82È
\82¢
\8a\84\82è
\8d\9e\82Ý
\81B
\r
13 IMR
\81F
\83C
\83\93\83^
\83\89\83v
\83g
\83}
\83X
\83N
\83\8c\83W
\83X
\83^
\r
14 .
\82±
\82ê
\82ª1
\82É
\82È
\82Á
\82Ä
\82¢
\82é
\8a\84\82è
\8d\9e\82Ý
\82Í
\81AIRR
\82ª1
\82É
\82È
\82Á
\82Ä
\82¢
\82Ä
\82à
\81A
\94½
\89\9e\82µ
\82È
\82¢
\81B
\r
17 io_out8(PIC0_IMR, 0xff); /*
\8a\84\82è
\8d\9e\82Ý
\91S
\95\94\96³
\8e\8b\81i
\83}
\83X
\83^
\81j*/
\r
18 io_out8(PIC1_IMR, 0xff); /*
\8a\84\82è
\8d\9e\82Ý
\91S
\95\94\96³
\8e\8b\81i
\83X
\83\8c\81[
\83u
\81j*/
\r
20 io_out8(PIC0_ICW1, 0x11); /*
\83G
\83b
\83W
\83g
\83\8a\83K
\83\82\81[
\83h
\82É
\90Ý
\92è
\81i
\83}
\83X
\83^
\81j*/
\r
21 io_out8(PIC0_ICW2, 0x20); /*
\8a\84\82è
\8d\9e\82Ý
\94Ô
\8d\86\82ð
\81A20~27
\82É
\90Ý
\92è
\81B
\81i
\83}
\83X
\83^
\81j*/
\r
22 io_out8(PIC0_ICW3, 1 << 2); /*00000100
\82Â
\82Ü
\82è
\81A
\83X
\83\8c\81[
\83u
\82ÍIRQ2
\82É
\82Â
\82È
\82ª
\82Á
\82Ä
\82Ü
\82·
\82æ
\82Æ
\82¢
\82¤
\82±
\82Æ
\81B*/
\r
23 io_out8(PIC0_ICW4, 0x01); /*
\83m
\83\93\83o
\83b
\83t
\83@
\83\82\81[
\83h
\81i
\83}
\83X
\83^
\81j*/
\r
25 io_out8(PIC1_ICW1, 0x11); /*
\83G
\83b
\83W
\83g
\83\8a\83K
\83\82\81[
\83h
\82É
\90Ý
\92è
\81i
\83X
\83\8c\81[
\83u
\81j*/
\r
26 io_out8(PIC1_ICW2, 0x28); /*
\8a\84\82è
\8d\9e\82Ý
\94Ô
\8d\86\82ð
\81A28~2f
\82É
\90Ý
\92è
\81B
\81i
\83X
\83\8c\81[
\83u
\81j*/
\r
27 io_out8(PIC1_ICW3, 2); /*
\8e©
\95ª
\82Í
\83}
\83X
\83^
\82ÌIRQ2
\94Ô
\82É
\82Â
\82È
\82ª
\82Á
\82Ä
\82Ü
\82·
\82Æ
\82¢
\82¤
\82±
\82Æ
\81B*/
\r
28 io_out8(PIC1_ICW4, 0x01); /*
\83m
\83\93\83o
\83b
\83t
\83@
\83\82\81[
\83h
\81i
\83X
\83\8c\81[
\83u
\81j*/
\r
30 io_out8(PIC0_IMR, 0xfb); /*11111011
\82Â
\82Ü
\82è
\81AIRQ2
\94Ô
\81i
\83X
\83\8c\81[
\83u
\81j
\82¾
\82¯
\8b\96\89Â
\81B
\82 \82Æ
\82Í
\96³
\8e\8b\81B
\81i
\83}
\83X
\83^
\81j*/
\r
31 io_out8(PIC1_IMR, 0xff); /*11111111
\82Â
\82Ü
\82è
\81A
\91S
\82Ä
\96³
\8e\8b*/
\r
33 set_gatedesc(system.io.interrupt.idt+0x27, (int)asm_inthandler27, 2 * 8, AR_INTGATE32);
\r
34 io_out8(PIC0_IMR, io_in8(PIC0_IMR) & 0x7f); /*IRQ-07
\91Î
\8dô*/
\r
39 void inthandler27(int *esp)
\r
41 io_out8(PIC0_OCW2, 0x67); /* IRQ-07
\8eó
\95t
\8a®
\97¹
\82ðPIC
\82É
\92Ê
\92m
\81B0x60+
\94Ô
\8d\86\81B*/
\r
46 char *cpu_exceptions[0x20] = {
\r
47 "Exception 0x00:\n\rDivided by zero.",
\r
48 "Exception 0x01:\n\rReserved.",
\r
49 "Exception 0x02:\n\rNonmaskable interrupt.",
\r
50 "Exception 0x03:\n\rBreakpoint.",
\r
51 "Exception 0x04:\n\rOverflow.",
\r
52 "Exception 0x05:\n\rOutside BOUND.",
\r
53 "Exception 0x06:\n\rInvalid opcode.",
\r
54 "Exception 0x07:\n\rDisable Device.",
\r
55 "Exception 0x08:\n\rDouble fault.",
\r
56 "Exception 0x09:\n\rCoprocessor Segment Overrun.",
\r
57 "Exception 0x0a:\n\rInvalid task status segment.",
\r
58 "Exception 0x0b:\n\rSegment absent.",
\r
59 "Exception 0x0c:\n\rStack Segment Fault.",
\r
60 "Exception 0x0d:\n\rGeneral Protection Exception.",
\r
61 "Exception 0x0e:\n\rPage fault.",
\r
62 "Exception 0x0f:\n\rReserved.",
\r
63 "Exception 0x10:\n\rFloating point error.",
\r
64 "Exception 0x11:\n\rAlignment Check.",
\r
65 "Exception 0x12:\n\rMachine Check.",
\r
66 "Exception 0x13:\n\rSIMD floating-point exception.",
\r
67 "Exception 0x14:\n\rReserved.",
\r
68 "Exception 0x15:\n\rReserved.",
\r
69 "Exception 0x16:\n\rReserved.",
\r
70 "Exception 0x17:\n\rReserved.",
\r
71 "Exception 0x18:\n\rReserved.",
\r
72 "Exception 0x19:\n\rReserved.",
\r
73 "Exception 0x1a:\n\rReserved.",
\r
74 "Exception 0x1b:\n\rReserved.",
\r
75 "Exception 0x1c:\n\rReserved.",
\r
76 "Exception 0x1d:\n\rReserved.",
\r
77 "Exception 0x1e:\n\rReserved.",
\r
78 "Exception 0x1f:\n\rReserved."
\r
81 char *cpu_exception_infos[16] = {
\r
100 void cpu_exception_abort(int exception, int *esp)
\r
105 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 0, 0xFFFFFF, (const uchar *)cpu_exceptions[exception]);
\r
106 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 16, 0xFFFFFF, "***registers info***");
\r
108 sprintf(s, "%s\n\r", (uchar *)cpu_exceptions[exception]);
\r
111 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 32, 0xFFFFFF, "#PUSHAD by _asm_inthandler");
\r
113 send_serial("#PUSHAD by _asm_inthandler\n\r");
\r
115 for(i = 0; i <= 7; i++){
\r
116 // sprintf(s, "%s:0x%08X", cpu_exception_infos[i], esp[i]);
\r
117 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 16 * (i + 3), 0xFFFFFF, s);
\r
119 sprintf(s, "%s:0x%08X\n\r", cpu_exception_infos[i], esp[i]);
\r
123 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 176, 0xFFFFFF, "#PUSH by _asm_inthandler");
\r
124 send_serial("#PUSH by _asm_inthandler\n\r");
\r
126 for(i = 8; i <= 9; i++){
\r
127 // sprintf(s, "%s:0x%08X", cpu_exception_infos[i], esp[i]);
\r
128 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 16 * (i + 4), 0xFFFFFF, s);
\r
130 sprintf(s, "%s:0x%08X\n\r", cpu_exception_infos[i], esp[i]);
\r
134 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 224, 0xFFFFFF, "#PUSH by CPU");
\r
136 send_serial("#PUSH by CPU\n\r");
\r
137 for(i = 10; i <= 15; i++){
\r
138 // sprintf(s, "%s:0x%08X", cpu_exception_infos[i], esp[i]);
\r
139 // putfonts32_asc(system.data.info.vesa.PhysBasePtr, system.data.info.boot.scrnx, 0, 16 * (i + 5), 0xFFFFFF, s);
\r
141 sprintf(s, "%s:0x%08X\n\r", cpu_exception_infos[i], esp[i]);
\r
145 send_serial("#Control Registers\n\r");
\r
146 sprintf(s, "CR0 = 0x%08X\n\r", load_cr0());
\r
148 sprintf(s, "CR2 = 0x%08X\n\r", load_cr2());
\r
150 sprintf(s, "CR3 = 0x%08X\n\r", load_cr3());
\r
158 uint cpu_exception_fault(int exception, int *esp)
\r
160 UI_Task *task = task_now();
\r
165 for(i = 0; i < MAX_CONSOLES; i++){
\r
166 if(system.ui.console.consoles[i].task == task)break;
\r
168 if(system.ui.console.consoles[i].task != task)cpu_exception_abort(exception, esp);
\r
169 cons = &system.ui.console.consoles[i];
\r
171 cons_put_str(cons, (uchar *)cpu_exceptions[exception]);
\r
172 sprintf(s, "\n%s:0x%08X", cpu_exception_infos[11], esp[11]);
\r
173 cons_put_str(cons, s);
\r
175 return (uint)&(task->tss.esp0);
\r
178 void inthandler00(int *esp)
\r
180 cpu_exception_abort(0x00, esp);
\r
183 void inthandler01(int *esp)
\r
185 cpu_exception_abort(0x01, esp);
\r
188 void inthandler02(int *esp)
\r
190 cpu_exception_abort(0x02, esp);
\r
193 void inthandler03(int *esp)
\r
195 cpu_exception_abort(0x03, esp);
\r
198 void inthandler04(int *esp)
\r
200 cpu_exception_abort(0x04, esp);
\r
203 void inthandler05(int *esp)
\r
205 cpu_exception_abort(0x05, esp);
\r
208 void inthandler06(int *esp)
\r
210 cpu_exception_abort(0x06, esp);
\r
213 void inthandler07(int *esp)
\r
215 cpu_exception_abort(0x07, esp);
\r
218 void inthandler08(int *esp)
\r
220 cpu_exception_abort(0x08, esp);
\r
223 void inthandler09(int *esp)
\r
225 cpu_exception_abort(0x09, esp);
\r
228 void inthandler0a(int *esp)
\r
230 cpu_exception_abort(0x0a, esp);
\r
233 void inthandler0b(int *esp)
\r
235 cpu_exception_abort(0x0b, esp);
\r
238 void inthandler0c(int *esp)
\r
240 cpu_exception_fault(0x0c, esp);
\r
243 void inthandler0d(int *esp)
\r
245 cpu_exception_fault(0x0d, esp);
\r
248 void inthandler0e(int *esp)
\r
250 cpu_exception_abort(0x0e, esp);
\r
253 void inthandler0f(int *esp)
\r
255 cpu_exception_abort(0x0f, esp);
\r
258 void inthandler10(int *esp)
\r
260 cpu_exception_abort(0x10, esp);
\r
263 void inthandler11(int *esp)
\r
265 cpu_exception_abort(0x11, esp);
\r
268 void inthandler12(int *esp)
\r
270 cpu_exception_abort(0x12, esp);
\r
273 void inthandler13(int *esp)
\r
275 cpu_exception_abort(0x13, esp);
\r
278 void inthandler14(int *esp)
\r
280 cpu_exception_abort(0x14, esp);
\r
283 void inthandler15(int *esp)
\r
285 cpu_exception_abort(0x15, esp);
\r
288 void inthandler16(int *esp)
\r
290 cpu_exception_abort(0x16, esp);
\r
293 void inthandler17(int *esp)
\r
295 cpu_exception_abort(0x17, esp);
\r
298 void inthandler18(int *esp)
\r
300 cpu_exception_abort(0x18, esp);
\r
303 void inthandler19(int *esp)
\r
305 cpu_exception_abort(0x19, esp);
\r
308 void inthandler1a(int *esp)
\r
310 cpu_exception_abort(0x1a, esp);
\r
313 void inthandler1b(int *esp)
\r
315 cpu_exception_abort(0x1b, esp);
\r
318 void inthandler1c(int *esp)
\r
320 cpu_exception_abort(0x1c, esp);
\r
323 void inthandler1d(int *esp)
\r
325 cpu_exception_abort(0x1d, esp);
\r
328 void inthandler1e(int *esp)
\r
330 cpu_exception_abort(0x1e, esp);
\r
333 void inthandler1f(int *esp)
\r
335 cpu_exception_abort(0x1f, esp);
\r