4 #define PORT_PCI_CONFIG_ADDRESS 0x0cf8 //32bit R/W
\r
5 #define PORT_PCI_CONFIG_DATA_BASE 0x0cfc //4ports anysize R/W
\r
7 typedef union PCI_CONFIG_ADDRESS_REGISTER {
\r
9 struct PCI_CONFIG_ADDRESS_REGISTER_BIT {
\r
10 unsigned reserved0 : 2; //0
\r
11 unsigned register_num : 6;
\r
12 unsigned function_num : 3;
\r
13 unsigned device_num : 5;
\r
14 unsigned bus_num : 8;
\r
15 unsigned reserved1 : 7; //0
\r
16 unsigned enable : 1; //PCI_CDRn
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\r
18 } PCI_ConfigurationAddressRegister;
\r
20 //
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\83^:
\r
21 //0x00:00-15:
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\83\93\83_ID(ReadOnly)
\r
22 //0x00:16-31:
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\83o
\83C
\83XID(ReadOnly)
\r
23 //0x04:00-15:
\83R
\83}
\83\93\83h
\83\8c\83W
\83X
\83^(R/W)
\r
24 // 00:I/O
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25 // 01:
\83\81\83\82\83\8a\8bó
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26 // 02:
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\83}
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\81[
\r
27 // 03:
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28 // 04:
\83\81\83\82\83\8a\83\89\83C
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29 // 05:VGA
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30 // 06:
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\r
31 // 07:
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\8cä
\r
32 // 08:SERR#
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\83\8b\r
33 // 09:
\8d\82\91¬
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\83N
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34 // 10-15:
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\r
35 //0x04:16-31:
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\83\8c\83W
\83X
\83^(R/W Write
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\83g
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\83N
\83\8a\83A
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\r
36 // 16-20:
\83\8a\83U
\81[
\83u
\r
37 // 21:66MHz
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\89\9e\89Â
\94\
\r
38 // 22:
\83\86\81[
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\81[
\92è
\8b`
\8b@
\94\
\82 \82è
\r
39 // 23:
\8d\82\91¬
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\83b
\83N
\83c
\81[
\83o
\83b
\83N
\89Â
\94\
\r
40 // 24:
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\83X
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\83X
\83^
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\8e\9e\82Ì
\83G
\83\89\81[)
\r
41 // 25-26:DEVSEL#
\83^
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\83\93\83O(0:
\8d\82\91¬ 1:
\92\86\91¬ 2:
\92á
\91¬ 3:
\97\
\96ñ)
\r
42 // 27:
\83^
\81[
\83Q
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\83g
\83A
\83{
\81[
\83g
\92Ê
\92m
\r
43 // 28:
\83^
\81[
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\83b
\83g
\83A
\83{
\81[
\83g
\8eó
\90M
\r
44 // 29:
\83}
\83X
\83^
\81[
\83A
\83{
\81[
\83g
\8eó
\90M
\r
45 // 30:
\83V
\83X
\83e
\83\80\83G
\83\89\81[
\92Ê
\92m
\r
46 // 31:
\83p
\83\8a\83e
\83B
\83G
\83\89\81[
\8c\9f\92m
\r
47 //0x08:00-07:
\83\8a\83r
\83W
\83\87\83\93ID(ReadOnly)
\r
48 //0x08:08-31:
\83N
\83\89\83X
\83R
\81[
\83h(ReadOnly)
\r
49 // 08-15:
\83v
\83\8d\83O
\83\89\83\80\83C
\83\93\83^
\81[
\83t
\83F
\81[
\83X
\r
50 // 16-23:
\83T
\83u
\83N
\83\89\83X
\r
51 // 24-31:
\83x
\81[
\83X
\83N
\83\89\83X
\r
52 //0x0c:00-07:
\83L
\83\83\83b
\83V
\83\85\83\89\83C
\83\93\83T
\83C
\83Y
\r
53 //0x0c:08-15:
\83}
\83X
\83^
\83\8c\83C
\83e
\83\93\83V
\83^
\83C
\83}
\r
54 //0x0c:16-23:
\83w
\83b
\83_
\83^
\83C
\83v(ReadOnly)
\r
55 // 16-22:
\83f
\83o
\83C
\83X
\83^
\83C
\83v(0:
\92Ê
\8fí
\82ÌPCI
\83f
\83o
\83C
\83X 1:PCI-PCI
\83u
\83\8a\83b
\83W 2:CardBus
\83u
\83\8a\83b
\83W)
\r
56 // 23:
\83}
\83\8b\83`
\83t
\83@
\83\93\83N
\83V
\83\87\83\93\83f
\83o
\83C
\83X
\r
57 //0x0c:24-31:BIST
\83\8c\83W
\83X
\83^
\r
59 typedef struct PCI_DEVICE_VENDOR {
\r
62 } PCI_Device_VendorID;
\r
64 typedef struct PCI_DEVICE_CLASS {
\r
69 typedef struct PCI_DEVICE_TYPE {
\r
74 PCI_Device_VendorID pci_device_vendor[] = {
\r
75 {0x10ec, "Realtek Semiconductor Corp."},
\r
77 {0xffff, "[Unknown]"},
\r
81 PCI_Device_Class pci_device_class[] = {
\r
82 {0x010100, "Ultra ATA storage controller"},
\r
83 {0x010180, "bus master IDE controller (UDMA33?)"},
\r
84 {0x020000, "ethernet adapter ?"},
\r
85 {0x030000, "VGA compatible controller"},
\r
86 {0x040100, "audio device"},
\r
87 {0x060000, "CPU to PCI bridge"},
\r
88 {0x060100, "PCI to ISA bridge"},
\r
89 {0x068000, "power management controller"},
\r
90 {0xff0000, "[Unknown]"},
\r
93 PCI_Device_Type pci_device_type[] = {
\r
94 {0, "Standard PCI Device"},
\r
95 {1, "PCI-PCI Bridge"},
\r
96 {2, "CardBus Bridge"},
\r
100 void Initialize_PCI(void)
\r
102 #ifdef CHNOSPROJECT_DEBUG_PCI
\r
103 uint data, bus, device, function;
\r
106 //PCICAR
\8f\89\8aú
\89»
\r
107 IO_Out32(PORT_PCI_CONFIG_ADDRESS, 0x00000000);
\r
109 #ifdef CHNOSPROJECT_DEBUG_PCI
\r
110 for(bus = 0; bus < 256; bus++){
\r
111 for(device = 0; device < 32; device++){
\r
112 for(function = 0; function < 8; function++){
\r
113 PCI_ConfigurationRegister_SelectDevice(bus, device, function);
\r
114 data = PCI_ConfigurationRegister_Read32(0x00);
\r
115 if(data != 0xffffffff){
\r
116 debug("PCI:Bus%d.Device%d.Function%d:\n", bus, device, function);
\r
117 debug("PCI: DeviceVendor:%s(0x%04X)\n", PCI_GetDeviceVendor(data & 0xffff), data & 0xffff);
\r
119 debug("PCI: DeviceID:0x%04X\n", data >> 16);
\r
121 data = PCI_ConfigurationRegister_Read32(0x08);
\r
122 data = CFunction_ExtractBits(data, 8, 31);
\r
123 debug("PCI: ClassCode:%s(0x%06X)\n", PCI_GetDeviceClass(data), data);
\r
125 data = PCI_ConfigurationRegister_Read32(0x0c);
\r
126 data = CFunction_ExtractBits(data, 16, 22);
\r
127 debug("PCI: DeviceType:%s(%d)\n", PCI_GetDeviceType(data), data);
\r
137 void PCI_ConfigurationRegister_SelectDevice(uint bus, uint device, uint function)
\r
139 PCI_ConfigurationAddressRegister pcicar;
\r
140 pcicar.reg = IO_In32(PORT_PCI_CONFIG_ADDRESS);
\r
141 pcicar.bit.bus_num = bus;
\r
142 pcicar.bit.device_num = device;
\r
143 pcicar.bit.function_num = function;
\r
144 IO_Out32(PORT_PCI_CONFIG_ADDRESS, pcicar.reg);
\r
149 uint PCI_ConfigurationRegister_Read32(uint addr)
\r
151 PCI_ConfigurationAddressRegister pcicar;
\r
154 pcicar.reg = IO_In32(PORT_PCI_CONFIG_ADDRESS);
\r
155 pcicar.bit.register_num = addr >> 2;
\r
156 pcicar.bit.enable = True;
\r
157 IO_Out32(PORT_PCI_CONFIG_ADDRESS, pcicar.reg);
\r
158 data = IO_In32(PORT_PCI_CONFIG_DATA_BASE + (addr & 0x03));
\r
159 pcicar.bit.enable = False;
\r
160 IO_Out32(PORT_PCI_CONFIG_ADDRESS, pcicar.reg);
\r
165 uchar *PCI_GetDeviceVendor(uint id)
\r
169 for(i = 0; pci_device_vendor[i].id != 0xffff; i++){
\r
170 if(pci_device_vendor[i].id == id){
\r
175 return pci_device_vendor[i].name;
\r
178 uchar *PCI_GetDeviceClass(uint id)
\r
182 for(i = 0; pci_device_class[i].id != 0xff0000; i++){
\r
183 if(pci_device_class[i].id == id){
\r
188 return pci_device_class[i].name;
\r
191 uchar *PCI_GetDeviceType(uint id)
\r
195 for(i = 0; pci_device_type[i].id != 3; i++){
\r
196 if(pci_device_type[i].id == id){
\r
201 return pci_device_type[i].name;
\r