source/src/vm/bubcom80/membus.cpp

   1 /*
   2         Systems Formulate BUBCOM80 Emulator 'eBUBCOM80'
   3
   4         Author : Takeda.Toshiya
   5         Date   : 2018.05.08-
   6
   7         [ memory bus ]
   8 */
   9
  10 #include "membus.h"
  11
  12 void MEMBUS::initialize()
  13 {
  14         MEMORY::initialize();
  15
  16         memset(ram, 0x00, sizeof(ram));
  17         memset(boot, 0xff, sizeof(boot));
  18         memset(basic, 0xff, sizeof(basic));
  19
  20         if(!read_bios(_T("IPL.ROM"), boot, sizeof(boot))) {
  21                 read_bios(_T("BOOT.ROM"), boot, sizeof(boot));
  22         }
  23         read_bios(_T("BASIC.ROM"), basic, sizeof(basic));
  24
  25         set_memory_rw(0x0000, 0xffff, ram);
  26 }
  27
  28 void MEMBUS::reset()
  29 {
  30         MEMORY::reset();
  31
  32         basic_addr.d = 0;
  33         ram_selected = false;
  34         update_bank();
  35 }
  36
  37 void MEMBUS::write_io8(uint32_t addr, uint32_t data)
  38 {
  39         switch(addr) {
  40         case 0x0c:
  41                 basic_addr.b.l = data;
  42                 break;
  43         case 0x0d:
  44                 basic_addr.b.h = data;
  45                 break;
  46         case 0x0e:
  47                 // error code ???
  48                 break;
  49         case 0x80:
  50                 ram_selected = ((data & 0x80) != 0);
  51                 update_bank();
  52                 break;
  53         }
  54 }
  55
  56 uint32_t MEMBUS::read_io8(uint32_t addr)
  57 {
  58         switch(addr) {
  59         case 0x0c:
  60                 return basic[basic_addr.w.l];
  61         }
  62         return 0xff;
  63 }
  64
  65 void MEMBUS::write_dma_data8(uint32_t addr, uint32_t data)
  66 {
  67         ram[addr & 0xffff] = data;
  68 }
  69
  70 uint32_t MEMBUS::read_dma_data8(uint32_t addr)
  71 {
  72         return ram[addr & 0xffff];
  73 }
  74
  75 void MEMBUS::update_bank()
  76 {
  77         set_memory_r(0x0000, 0x07ff, ram_selected ? ram : boot);
  78 }
  79
  80 #define STATE_VERSION   1
  81
  82 #include "../../statesub.h"
  83
  84 void MEMBUS::decl_state()
  85 {
  86         enter_decl_state(STATE_VERSION);
  87
  88         MEMORY::decl_state(); // ??
  89
  90         DECL_STATE_ENTRY_1D_ARRAY(ram, sizeof(ram));
  91         DECL_STATE_ENTRY_PAIR(basic_addr);
  92         DECL_STATE_ENTRY_BOOL(ram_selected);
  93
  94         leave_decl_state();
  95
  96 }
  97 void MEMBUS::save_state(FILEIO* state_fio)
  98 {
  99         if(state_entry != NULL) {
 100                 state_entry->save_state(state_fio);
 101         }
 102
 103 //      state_fio->FputUint32(STATE_VERSION);
 104 //      state_fio->FputInt32(this_device_id);
 105
 106 //      MEMORY::save_state(state_fio); // OK?
 107
 108 //      state_fio->Fwrite(ram, sizeof(ram), 1);
 109 //      state_fio->FputUint32(basic_addr.d);
 110 //      state_fio->FputBool(ram_selected);
 111 }
 112
 113 bool MEMBUS::load_state(FILEIO* state_fio)
 114 {
 115         bool mb = false;
 116         if(state_entry != NULL) {
 117                 mb = state_entry->load_state(state_fio);
 118         }
 119         if(!mb) {
 120                 return false;
 121         }
 122
 123 //      if(state_fio->FgetUint32() != STATE_VERSION) {
 124 //              return false;
 125 //      }
 126 //      if(state_fio->FgetInt32() != this_device_id) {
 127 //              return false;
 128 //      }
 129
 130 //      if(!MEMORY::load_state(state_fio)) {  // OK?
 131 //              return false;
 132 //      }
 133
 134 //      state_fio->Fread(ram, sizeof(ram), 1);
 135 //      basic_addr.d = state_fio->FgetUint32();
 136 //      ram_selected = state_fio->FgetBool();
 137
 138         // post process
 139         update_bank();
 140         return true;
 141 }