source/src/vm/device.h

   1 /*
   2         Skelton for retropc emulator
   3
   4         Author : Takeda.Toshiya
   5         Date   : 2006.08.18 -
   6
   7         [ device base class ]
   8 */
   9
  10 #ifndef _DEVICE_H_
  11 #define _DEVICE_H_
  12
  13 #include "vm.h"
  14 #include "../emu.h"
  15
  16 // max devices connected to the output port
  17 #define MAX_OUTPUT      16
  18
  19 // common signal id
  20 #define SIG_CPU_IRQ     101
  21 #define SIG_CPU_FIRQ    102
  22 #define SIG_CPU_NMI     103
  23 #define SIG_CPU_BUSREQ  104
  24 #define SIG_CPU_DEBUG   201
  25
  26 class DEVICE
  27 {
  28 protected:
  29         VM* vm;
  30         EMU* emu;
  31 public:
  32         DEVICE(VM* parent_vm, EMU* parent_emu) : vm(parent_vm), emu(parent_emu)
  33         {
  34                 prev_device = vm->last_device;
  35                 next_device = NULL;
  36                 if(vm->first_device == NULL) {
  37                         // this is the first device
  38                         vm->first_device = this;
  39                         this_device_id = 0;
  40                 } else {
  41                         // this is not the first device
  42                         vm->last_device->next_device = this;
  43                         this_device_id = vm->last_device->this_device_id + 1;
  44                 }
  45                 vm->last_device = this;
  46
  47                 // primary event manager
  48                 event_manager = NULL;
  49         }
  50         ~DEVICE(void) {}
  51
  52         virtual void initialize() {}
  53         virtual void release() {}
  54
  55         virtual void update_config() {}
  56         virtual void save_state(FILEIO* state_fio) {}
  57         virtual bool load_state(FILEIO* state_fio)
  58         {
  59                 return true;
  60         }
  61
  62         // control
  63         virtual void reset() {}
  64         virtual void special_reset()
  65         {
  66                 reset();
  67         }
  68
  69         // NOTE: the virtual bus interface functions for 16/32bit access invite the cpu is little endian.
  70         // if the cpu is big endian, you need to implement them in the virtual machine memory/io classes.
  71
  72         // memory bus
  73         virtual void write_data8(uint32 addr, uint32 data) {}
  74         virtual uint32 read_data8(uint32 addr)
  75         {
  76                 return 0xff;
  77         }
  78         virtual void write_data16(uint32 addr, uint32 data)
  79         {
  80                 write_data8(addr, data & 0xff);
  81                 write_data8(addr + 1, (data >> 8) & 0xff);
  82         }
  83         virtual uint32 read_data16(uint32 addr)
  84         {
  85                 uint32 val = read_data8(addr);
  86                 val |= read_data8(addr + 1) << 8;
  87                 return val;
  88         }
  89         virtual void write_data32(uint32 addr, uint32 data)
  90         {
  91                 write_data16(addr, data & 0xffff);
  92                 write_data16(addr + 2, (data >> 16) & 0xffff);
  93         }
  94         virtual uint32 read_data32(uint32 addr)
  95         {
  96                 uint32 val = read_data16(addr);
  97                 val |= read_data16(addr + 2) << 16;
  98                 return val;
  99         }
 100         virtual void write_data8w(uint32 addr, uint32 data, int* wait)
 101         {
 102                 *wait = 0;
 103                 write_data8(addr, data);
 104         }
 105         virtual uint32 read_data8w(uint32 addr, int* wait)
 106         {
 107                 *wait = 0;
 108                 return read_data8(addr);
 109         }
 110         virtual void write_data16w(uint32 addr, uint32 data, int* wait)
 111         {
 112                 int wait_l, wait_h;
 113                 write_data8w(addr, data & 0xff, &wait_l);
 114                 write_data8w(addr + 1, (data >> 8) & 0xff, &wait_h);
 115                 *wait = wait_l + wait_h;
 116         }
 117         virtual uint32 read_data16w(uint32 addr, int* wait)
 118         {
 119                 int wait_l, wait_h;
 120                 uint32 val = read_data8w(addr, &wait_l);
 121                 val |= read_data8w(addr + 1, &wait_h) << 8;
 122                 *wait = wait_l + wait_h;
 123                 return val;
 124         }
 125         virtual void write_data32w(uint32 addr, uint32 data, int* wait)
 126         {
 127                 int wait_l, wait_h;
 128                 write_data16w(addr, data & 0xffff, &wait_l);
 129                 write_data16w(addr + 2, (data >> 16) & 0xffff, &wait_h);
 130                 *wait = wait_l + wait_h;
 131         }
 132         virtual uint32 read_data32w(uint32 addr, int* wait)
 133         {
 134                 int wait_l, wait_h;
 135                 uint32 val = read_data16w(addr, &wait_l);
 136                 val |= read_data16w(addr + 2, &wait_h) << 16;
 137                 *wait = wait_l + wait_h;
 138                 return val;
 139         }
 140         virtual uint32 fetch_op(uint32 addr, int *wait)
 141         {
 142                 return read_data8w(addr, wait);
 143         }
 144         virtual void write_dma_data8(uint32 addr, uint32 data)
 145         {
 146                 write_data8(addr, data);
 147         }
 148         virtual uint32 read_dma_data8(uint32 addr)
 149         {
 150                 return read_data8(addr);
 151         }
 152         virtual void write_dma_data16(uint32 addr, uint32 data)
 153         {
 154                 write_data16(addr, data);
 155         }
 156         virtual uint32 read_dma_data16(uint32 addr)
 157         {
 158                 return read_data16(addr);
 159         }
 160         virtual void write_dma_data32(uint32 addr, uint32 data)
 161         {
 162                 write_data32(addr, data);
 163         }
 164         virtual uint32 read_dma_data32(uint32 addr)
 165         {
 166                 return read_data32(addr);
 167         }
 168         virtual void write_dma_data8w(uint32 addr, uint32 data, int* wait)
 169         {
 170                 write_data8w(addr, data, wait);
 171         }
 172         virtual uint32 read_dma_data8w(uint32 addr, int* wait)
 173         {
 174                 return read_data8w(addr, wait);
 175         }
 176         virtual void write_dma_data16w(uint32 addr, uint32 data, int* wait)
 177         {
 178                 write_data16w(addr, data, wait);
 179         }
 180         virtual uint32 read_dma_data16w(uint32 addr, int* wait)
 181         {
 182                 return read_data16w(addr, wait);
 183         }
 184         virtual void write_dma_data32w(uint32 addr, uint32 data, int* wait)
 185         {
 186                 write_data32w(addr, data, wait);
 187         }
 188         virtual uint32 read_dma_data32w(uint32 addr, int* wait)
 189         {
 190                 return read_data32w(addr, wait);
 191         }
 192
 193         // i/o bus
 194         virtual void write_io8(uint32 addr, uint32 data) {}
 195         virtual uint32 read_io8(uint32 addr)
 196         {
 197 #ifdef IOBUS_RETURN_ADDR
 198                 return (addr & 1 ? addr >> 8 : addr) & 0xff;
 199 #else
 200                 return 0xff;
 201 #endif
 202         }
 203         virtual void write_io16(uint32 addr, uint32 data)
 204         {
 205                 write_io8(addr, data & 0xff);
 206                 write_io8(addr + 1, (data >> 8) & 0xff);
 207         }
 208         virtual uint32 read_io16(uint32 addr)
 209         {
 210                 uint32 val = read_io8(addr);
 211                 val |= read_io8(addr + 1) << 8;
 212                 return val;
 213         }
 214         virtual void write_io32(uint32 addr, uint32 data)
 215         {
 216                 write_io16(addr, data & 0xffff);
 217                 write_io16(addr + 2, (data >> 16) & 0xffff);
 218         }
 219         virtual uint32 read_io32(uint32 addr)
 220         {
 221                 uint32 val = read_io16(addr);
 222                 val |= read_io16(addr + 2) << 16;
 223                 return val;
 224         }
 225         virtual void write_io8w(uint32 addr, uint32 data, int* wait)
 226         {
 227                 *wait = 0;
 228                 write_io8(addr, data);
 229         }
 230         virtual uint32 read_io8w(uint32 addr, int* wait)
 231         {
 232                 *wait = 0;
 233                 return read_io8(addr);
 234         }
 235         virtual void write_io16w(uint32 addr, uint32 data, int* wait)
 236         {
 237                 int wait_l, wait_h;
 238                 write_io8w(addr, data & 0xff, &wait_l);
 239                 write_io8w(addr + 1, (data >> 8) & 0xff, &wait_h);
 240                 *wait = wait_l + wait_h;
 241         }
 242         virtual uint32 read_io16w(uint32 addr, int* wait)
 243         {
 244                 int wait_l, wait_h;
 245                 uint32 val = read_io8w(addr, &wait_l);
 246                 val |= read_io8w(addr + 1, &wait_h) << 8;
 247                 *wait = wait_l + wait_h;
 248                 return val;
 249         }
 250         virtual void write_io32w(uint32 addr, uint32 data, int* wait)
 251         {
 252                 int wait_l, wait_h;
 253                 write_io16w(addr, data & 0xffff, &wait_l);
 254                 write_io16w(addr + 2, (data >> 16) & 0xffff, &wait_h);
 255                 *wait = wait_l + wait_h;
 256         }
 257         virtual uint32 read_io32w(uint32 addr, int* wait)
 258         {
 259                 int wait_l, wait_h;
 260                 uint32 val = read_io16w(addr, &wait_l);
 261                 val |= read_io16w(addr + 2, &wait_h) << 16;
 262                 *wait = wait_l + wait_h;
 263                 return val;
 264         }
 265         virtual void write_dma_io8(uint32 addr, uint32 data)
 266         {
 267                 write_io8(addr, data);
 268         }
 269         virtual uint32 read_dma_io8(uint32 addr)
 270         {
 271                 return read_io8(addr);
 272         }
 273         virtual void write_dma_io16(uint32 addr, uint32 data)
 274         {
 275                 write_io16(addr, data);
 276         }
 277         virtual uint32 read_dma_io16(uint32 addr)
 278         {
 279                 return read_io16(addr);
 280         }
 281         virtual void write_dma_io32(uint32 addr, uint32 data)
 282         {
 283                 write_io32(addr, data);
 284         }
 285         virtual uint32 read_dma_io32(uint32 addr)
 286         {
 287                 return read_io32(addr);
 288         }
 289         virtual void write_dma_io8w(uint32 addr, uint32 data, int* wait)
 290         {
 291                 write_io8w(addr, data, wait);
 292         }
 293         virtual uint32 read_dma_io8w(uint32 addr, int* wait)
 294         {
 295                 return read_io8w(addr, wait);
 296         }
 297         virtual void write_dma_io16w(uint32 addr, uint32 data, int* wait)
 298         {
 299                 write_io16w(addr, data, wait);
 300         }
 301         virtual uint32 read_dma_io16w(uint32 addr, int* wait)
 302         {
 303                 return read_io16w(addr, wait);
 304         }
 305         virtual void write_dma_io32w(uint32 addr, uint32 data, int* wait)
 306         {
 307                 write_io32w(addr, data, wait);
 308         }
 309         virtual uint32 read_dma_io32w(uint32 addr, int* wait)
 310         {
 311                 return read_io32w(addr, wait);
 312         }
 313
 314         // memory mapped i/o
 315         virtual void write_memory_mapped_io8(uint32 addr, uint32 data)
 316         {
 317                 write_io8(addr, data);
 318         }
 319         virtual uint32 read_memory_mapped_io8(uint32 addr)
 320         {
 321                 return read_io8(addr);
 322         }
 323         virtual void write_memory_mapped_io16(uint32 addr, uint32 data)
 324         {
 325                 write_memory_mapped_io8(addr, data & 0xff);
 326                 write_memory_mapped_io8(addr + 1, (data >> 8) & 0xff);
 327         }
 328         virtual uint32 read_memory_mapped_io16(uint32 addr)
 329         {
 330                 uint32 val = read_memory_mapped_io8(addr);
 331                 val |= read_memory_mapped_io8(addr + 1) << 8;
 332                 return val;
 333         }
 334         virtual void write_memory_mapped_io32(uint32 addr, uint32 data)
 335         {
 336                 write_memory_mapped_io16(addr, data & 0xffff);
 337                 write_memory_mapped_io16(addr + 2, (data >> 16) & 0xffff);
 338         }
 339         virtual uint32 read_memory_mapped_io32(uint32 addr)
 340         {
 341                 uint32 val = read_memory_mapped_io16(addr);
 342                 val |= read_memory_mapped_io16(addr + 2) << 16;
 343                 return val;
 344         }
 345         virtual void write_memory_mapped_io8w(uint32 addr, uint32 data, int* wait)
 346         {
 347                 *wait = 0;
 348                 write_memory_mapped_io8(addr, data);
 349         }
 350         virtual uint32 read_memory_mapped_io8w(uint32 addr, int* wait)
 351         {
 352                 *wait = 0;
 353                 return read_memory_mapped_io8(addr);
 354         }
 355         virtual void write_memory_mapped_io16w(uint32 addr, uint32 data, int* wait)
 356         {
 357                 int wait_l, wait_h;
 358                 write_memory_mapped_io8w(addr, data & 0xff, &wait_l);
 359                 write_memory_mapped_io8w(addr + 1, (data >> 8) & 0xff, &wait_h);
 360                 *wait = wait_l + wait_h;
 361         }
 362         virtual uint32 read_memory_mapped_io16w(uint32 addr, int* wait)
 363         {
 364                 int wait_l, wait_h;
 365                 uint32 val = read_memory_mapped_io8w(addr, &wait_l);
 366                 val |= read_memory_mapped_io8w(addr + 1, &wait_h) << 8;
 367                 *wait = wait_l + wait_h;
 368                 return val;
 369         }
 370         virtual void write_memory_mapped_io32w(uint32 addr, uint32 data, int* wait)
 371         {
 372                 int wait_l, wait_h;
 373                 write_memory_mapped_io16w(addr, data & 0xffff, &wait_l);
 374                 write_memory_mapped_io16w(addr + 2, (data >> 16) & 0xffff, &wait_h);
 375                 *wait = wait_l + wait_h;
 376         }
 377         virtual uint32 read_memory_mapped_io32w(uint32 addr, int* wait)
 378         {
 379                 int wait_l, wait_h;
 380                 uint32 val = read_memory_mapped_io16w(addr, &wait_l);
 381                 val |= read_memory_mapped_io16w(addr + 2, &wait_h) << 16;
 382                 *wait = wait_l + wait_h;
 383                 return val;
 384         }
 385
 386         // device to device
 387         typedef struct {
 388                 DEVICE *device;
 389                 int id;
 390                 uint32 mask;
 391                 int shift;
 392         } output_t;
 393
 394         typedef struct {
 395                 int count;
 396                 output_t item[MAX_OUTPUT];
 397         } outputs_t;
 398
 399         virtual void init_output_signals(outputs_t *items)
 400         {
 401                 items->count = 0;
 402         }
 403         virtual void register_output_signal(outputs_t *items, DEVICE *device, int id, uint32 mask, int shift)
 404         {
 405                 int c = items->count++;
 406                 items->item[c].device = device;
 407                 items->item[c].id = id;
 408                 items->item[c].mask = mask;
 409                 items->item[c].shift = shift;
 410         }
 411         virtual void register_output_signal(outputs_t *items, DEVICE *device, int id, uint32 mask)
 412         {
 413                 int c = items->count++;
 414                 items->item[c].device = device;
 415                 items->item[c].id = id;
 416                 items->item[c].mask = mask;
 417                 items->item[c].shift = 0;
 418         }
 419         virtual void write_signals(outputs_t *items, uint32 data)
 420         {
 421                 for(int i = 0; i < items->count; i++) {
 422                         output_t *item = &items->item[i];
 423                         int shift = item->shift;
 424                         uint32 val = (shift < 0) ? (data >> (-shift)) : (data << shift);
 425                         uint32 mask = (shift < 0) ? (item->mask >> (-shift)) : (item->mask << shift);
 426                         item->device->write_signal(item->id, val, mask);
 427                 }
 428         };
 429         virtual void write_signal(int id, uint32 data, uint32 mask) {}
 430         virtual uint32 read_signal(int ch)
 431         {
 432                 return 0;
 433         }
 434
 435         // z80 daisy chain
 436         virtual void set_context_intr(DEVICE* device, uint32 bit) {}
 437         virtual void set_context_child(DEVICE* device) {}
 438
 439         // interrupt device to device
 440         virtual void set_intr_iei(bool val) {}
 441
 442         // interrupt device to cpu
 443         virtual void set_intr_line(bool line, bool pending, uint32 bit) {}
 444
 445         // interrupt cpu to device
 446         virtual uint32 intr_ack()
 447         {
 448                 return 0xff;
 449         }
 450         virtual void intr_reti() {}
 451         virtual void intr_ei() {}
 452
 453         // dma
 454         virtual void do_dma() {}
 455
 456         // cpu
 457         virtual int run(int clock)
 458         {
 459                 // when clock == -1, run one opecode
 460                 return (clock == -1 ? 1 : clock);
 461         }
 462         virtual void set_extra_clock(int clock) {}
 463         virtual int get_extra_clock()
 464         {
 465                 return 0;
 466         }
 467         virtual uint32 get_pc()
 468         {
 469                 return 0;
 470         }
 471         virtual uint32 get_next_pc()
 472         {
 473                 return 0;
 474         }
 475
 476         // bios
 477         virtual bool bios_call_i86(uint32 PC, uint16 regs[], uint16 sregs[], int32* ZeroFlag, int32* CarryFlag)
 478         {
 479                 return false;
 480         }
 481         virtual bool bios_int_i86(int intnum, uint16 regs[], uint16 sregs[], int32* ZeroFlag, int32* CarryFlag)
 482         {
 483                 return false;
 484         }
 485         virtual bool bios_ret_z80(uint16 PC, pair* af, pair* bc, pair* de, pair* hl, pair* ix, pair* iy, uint8* iff1)
 486         {
 487                 return false;
 488         }
 489
 490         // event manager
 491         DEVICE* event_manager;
 492
 493         virtual void set_context_event_manager(DEVICE* device)
 494         {
 495                 event_manager = device;
 496         }
 497         virtual int event_manager_id()
 498         {
 499                 if(event_manager == NULL) {
 500                         event_manager = vm->first_device->next_device;
 501                 }
 502                 return event_manager->this_device_id;
 503         }
 504         virtual void register_event(DEVICE* device, int event_id, double usec, bool loop, int* register_id)
 505         {
 506                 if(event_manager == NULL) {
 507                         event_manager = vm->first_device->next_device;
 508                 }
 509                 event_manager->register_event(device, event_id, usec, loop, register_id);
 510         }
 511         virtual void register_event_by_clock(DEVICE* device, int event_id, uint64 clock, bool loop, int* register_id)
 512         {
 513                 if(event_manager == NULL) {
 514                         event_manager = vm->first_device->next_device;
 515                 }
 516                 event_manager->register_event_by_clock(device, event_id, clock, loop, register_id);
 517         }
 518         virtual void cancel_event(DEVICE* device, int register_id)
 519         {
 520                 if(event_manager == NULL) {
 521                         event_manager = vm->first_device->next_device;
 522                 }
 523                 event_manager->cancel_event(device, register_id);
 524         }
 525         virtual void register_frame_event(DEVICE* device)
 526         {
 527                 if(event_manager == NULL) {
 528                         event_manager = vm->first_device->next_device;
 529                 }
 530                 event_manager->register_frame_event(device);
 531         }
 532         virtual void register_vline_event(DEVICE* device)
 533         {
 534                 if(event_manager == NULL) {
 535                         event_manager = vm->first_device->next_device;
 536                 }
 537                 event_manager->register_vline_event(device);
 538         }
 539         virtual uint32 current_clock()
 540         {
 541                 if(event_manager == NULL) {
 542                         event_manager = vm->first_device->next_device;
 543                 }
 544                 return event_manager->current_clock();
 545         }
 546         virtual uint32 passed_clock(uint32 prev)
 547         {
 548                 if(event_manager == NULL) {
 549                         event_manager = vm->first_device->next_device;
 550                 }
 551                 return event_manager->passed_clock(prev);
 552         }
 553         virtual double passed_usec(uint32 prev)
 554         {
 555                 if(event_manager == NULL) {
 556                         event_manager = vm->first_device->next_device;
 557                 }
 558                 return event_manager->passed_usec(prev);
 559         }
 560         virtual uint32 get_cpu_pc(int index)
 561         {
 562                 if(event_manager == NULL) {
 563                         event_manager = vm->first_device->next_device;
 564                 }
 565                 return event_manager->get_cpu_pc(index);
 566         }
 567         virtual void request_skip_frames()
 568         {
 569                 if(event_manager == NULL) {
 570                         event_manager = vm->first_device->next_device;
 571                 }
 572                 event_manager->request_skip_frames();
 573         }
 574         virtual void set_frames_per_sec(double frames)
 575         {
 576                 if(event_manager == NULL) {
 577                         event_manager = vm->first_device->next_device;
 578                 }
 579                 event_manager->set_frames_per_sec(frames);
 580         }
 581         virtual void set_lines_per_frame(int lines)
 582         {
 583                 if(event_manager == NULL) {
 584                         event_manager = vm->first_device->next_device;
 585                 }
 586                 event_manager->set_lines_per_frame(lines);
 587         }
 588         virtual void update_timing(int new_clocks, double new_frames_per_sec, int new_lines_per_frame) {}
 589
 590         // event callback
 591         virtual void event_callback(int event_id, int err) {}
 592         virtual void event_pre_frame() {}       // this event is to update timing settings
 593         virtual void event_frame() {}
 594         virtual void event_vline(int v, int clock) {}
 595         virtual void event_hsync(int v, int h, int clock) {}
 596
 597         // sound
 598         virtual void mix(int32* buffer, int cnt) {}
 599
 600 #ifdef USE_DEBUGGER
 601         // debugger
 602         virtual void *get_debugger()
 603         {
 604                 return NULL;
 605         }
 606         virtual uint32 debug_prog_addr_mask()
 607         {
 608                 return 0;
 609         }
 610         virtual uint32 debug_data_addr_mask()
 611         {
 612                 return 0;
 613         }
 614         virtual void debug_write_data8(uint32 addr, uint32 data) {}
 615         virtual uint32 debug_read_data8(uint32 addr)
 616         {
 617                 return 0xff;
 618         }
 619         virtual void debug_write_data16(uint32 addr, uint32 data)
 620         {
 621                 debug_write_data8(addr, data & 0xff);
 622                 debug_write_data8(addr + 1, (data >> 8) & 0xff);
 623         }
 624         virtual uint32 debug_read_data16(uint32 addr)
 625         {
 626                 uint32 val = debug_read_data8(addr);
 627                 val |= debug_read_data8(addr + 1) << 8;
 628                 return val;
 629         }
 630         virtual void debug_write_data32(uint32 addr, uint32 data)
 631         {
 632                 debug_write_data16(addr, data & 0xffff);
 633                 debug_write_data16(addr + 2, (data >> 16) & 0xffff);
 634         }
 635         virtual uint32 debug_read_data32(uint32 addr)
 636         {
 637                 uint32 val = debug_read_data16(addr);
 638                 val |= debug_read_data16(addr + 2) << 16;
 639                 return val;
 640         }
 641         virtual void debug_write_io8(uint32 addr, uint32 data) {}
 642         virtual uint32 debug_read_io8(uint32 addr)
 643         {
 644                 return 0xff;
 645         }
 646         virtual void debug_write_io16(uint32 addr, uint32 data)
 647         {
 648                 debug_write_io8(addr, data & 0xff);
 649                 debug_write_io8(addr + 1, (data >> 8) & 0xff);
 650         }
 651         virtual uint32 debug_read_io16(uint32 addr)
 652         {
 653                 uint32 val = debug_read_io8(addr);
 654                 val |= debug_read_io8(addr + 1) << 8;
 655                 return val;
 656         }
 657         virtual void debug_write_io32(uint32 addr, uint32 data)
 658         {
 659                 debug_write_io16(addr, data & 0xffff);
 660                 debug_write_io16(addr + 2, (data >> 16) & 0xffff);
 661         }
 662         virtual uint32 debug_read_io32(uint32 addr)
 663         {
 664                 uint32 val = debug_read_io16(addr);
 665                 val |= debug_read_io16(addr + 2) << 16;
 666                 return val;
 667         }
 668         virtual bool debug_write_reg(const _TCHAR *reg, uint32 data)
 669         {
 670                 return false;
 671         }
 672         virtual void debug_regs_info(_TCHAR *buffer, size_t buffer_len) {}
 673         virtual int debug_dasm(uint32 pc, _TCHAR *buffer, size_t buffer_len)
 674         {
 675                 return 0;
 676         }
 677 #endif
 678
 679         DEVICE* prev_device;
 680         DEVICE* next_device;
 681         int this_device_id;
 682 };
 683
 684 #endif