2 * Main memory without MMR for FM-7 [FM7_MAINMEM]
8 #ifndef _FM7_MAINMEM_H_
9 #define _FM7_MAINMEM_H_
11 #include "fm7_common.h"
13 #include "../device.h"
14 #include "../mc6809.h"
16 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
17 #define ADDRESS_SPACE 0x100000
18 #elif defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
19 #define ADDRESS_SPACE 0x40000
21 #define ADDRESS_SPACE 0x10000
30 class FM7_MAINMEM : public DEVICE
35 uint8_t (FM7_MAINMEM::*read_func)(uint32_t, bool);
37 void (FM7_MAINMEM::*write_func)(uint32_t, uint32_t, bool);
40 data_func_table_t data_table[ADDRESS_SPACE / 0x80];
42 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
43 data_func_table_t mmr_update_table_ext[(0x80 * 0x1000) / 0x80];
44 uint32_t mmr_baseaddr_table_ext[(0x80 * 0x1000) / 0x80];
46 data_func_table_t mmr_update_table_nor[(0x80 * 0x1000) / 0x80];
47 uint32_t mmr_bank_table[(0x80 * 0x1000) / 0x80];
48 uint32_t mmr_baseaddr_table_nor[(0x80 * 0x1000) / 0x80];
64 uint16_t window_offset;
66 uint8_t mmr_map_data[0x80];
72 #ifdef _FM77AV_VARIANTS
73 uint32_t extcard_bank;
75 bool initiator_enabled;
77 #if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
84 uint8_t fm7_mainmem_omote[0x8000];
85 uint8_t fm7_mainmem_ura[0x7c00];
86 uint8_t fm7_mainmem_basicrom[0x7c00];
87 uint8_t fm7_mainmem_bioswork[0x80];
89 uint8_t *fm7_bootroms[8];
91 uint8_t fm7_mainmem_bootrom_vector[0x1e]; // Without
92 uint8_t fm7_mainmem_reset_vector[2]; // Without
93 uint8_t fm7_mainmem_null[1];
94 #if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
95 uint8_t fm7_bootram[0x200]; // $00000-$0ffff
98 bool diag_load_sm11_14;
99 bool diag_load_sm11_15;
100 # elif defined(_FM77_VARIANTS)
101 bool diag_load_wb11_12;
102 # elif defined(_FM7) || defined(_FMNEW7)
103 bool diag_load_tl11_11;
104 bool diag_load_tl11_12;
107 bool extram_connected;
109 # if defined(_FM77AV_VARIANTS)
110 bool diag_load_initrom;
111 bool diag_load_dictrom;
112 bool diag_load_learndata;
113 bool dictrom_connected;
114 bool dictrom_enabled;
115 bool dictram_enabled;
117 bool use_page2_extram;
118 uint8_t fm7_mainmem_initrom[0x2000]; // $00000-$0ffff
119 uint8_t fm77av_hidden_bootmmr[0x200];
120 uint8_t fm7_mainmem_mmrbank_0[0x10000]; // $00000-$0ffff
121 uint8_t fm7_mainmem_mmrbank_2[0x10000]; // $20000-$2ffff
122 # if defined(CAPABLE_DICTROM)
123 uint8_t fm7_mainmem_dictrom[0x40000]; // $00000-$3ffff, banked
124 uint8_t fm7_mainmem_learndata[0x2000];
126 # if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
127 bool diag_load_extrarom;
128 uint8_t fm7_mainmem_extrarom[0x10000]; // $20000-$2bfff, banked
130 uint32_t extram_size;
131 uint8_t *fm7_mainmem_extram; // $40000- : MAX 768KB ($c0000)
134 # if defined(_FM77_VARIANTS)
136 uint32_t extram_size;
137 uint8_t *fm7_mainmem_extram; // $00000-$2ffff
138 uint8_t fm77_shadowram[0x200];
141 #if defined(CAPABLE_DICTROM)
142 KANJIROM *kanjiclass1;
143 //KANJIROM *kanjiclass2;
149 bool diag_load_basicrom;
150 bool diag_load_bootrom_bas;
151 bool diag_load_bootrom_dos;
152 bool diag_load_bootrom_mmr;
153 bool diag_load_bootrom_bubble;
154 bool diag_load_bootrom_bubble_128k;
155 bool diag_load_bootrom_sfd8;
156 bool diag_load_bootrom_2hd;
158 uint32_t mem_waitfactor;
159 uint32_t mem_waitcount;
161 int check_extrom(uint32_t raddr, uint32_t *realaddr);
163 int window_convert(uint32_t addr, uint32_t *realaddr);
164 uint32_t read_bios(const _TCHAR *name, uint8_t *ptr, uint32_t size);
165 uint32_t write_bios(const _TCHAR *name, uint8_t *ptr, uint32_t size);
166 void setclock(int mode);
168 uint8_t read_shared_ram(uint32_t realaddr, bool dmamode);
169 void write_shared_ram(uint32_t realaddr, uint32_t data, bool dmamode);
170 uint8_t read_direct_access(uint32_t realaddr, bool dmamode);
171 void write_direct_access(uint32_t realaddr, uint32_t data, bool dmamode);
172 uint8_t read_kanjirom_level1(uint32_t realaddr, bool dmamode);
173 uint8_t read_kanji_dummyaddr(uint32_t realaddr, bool dmamode);
174 uint8_t read_ura_basicrom(uint32_t addr, bool dmamode);
175 void write_ura_basicrom(uint32_t addr, uint32_t data, bool dmamode);
176 uint8_t read_mmio(uint32_t addr, bool dmamode);
177 void write_mmio(uint32_t addr, uint32_t data, bool dmamode);
178 uint8_t read_bootrom(uint32_t addr, bool dmamode);
179 void write_bootrom(uint32_t addr, uint32_t data, bool dmamode);
180 uint8_t read_page2(uint32_t addr, bool dmamode);
181 void write_page2(uint32_t addr, uint32_t data, bool dmamode);
182 int check_page2(uint32_t addr, uint32_t *realaddr, bool write_state, bool dmamode);
184 void init_data_table(void);
185 uint8_t read_data(uint32_t addr, bool dmamode);
186 void write_data(uint32_t addr, uint32_t data, bool dmamode);
187 uint8_t read_data_tbl(uint32_t addr, bool dmamode);
188 void write_data_tbl(uint32_t addr, uint32_t data, bool dmamode);
190 void update_mmr_jumptable(uint32_t pos);
191 void update_all_mmr_jumptable(void);
192 uint8_t read_segment_3f(uint32_t addr, bool dmamode);
193 void write_segment_3f(uint32_t addr, uint32_t data, bool dmamode);
194 uint8_t read_with_mmr(uint32_t addr, uint32_t segment, uint32_t dmamode);
195 void write_with_mmr(uint32_t addr, uint32_t segment, uint32_t data, uint32_t dmamode);
198 void call_write_signal(T *np, int id, uint32_t data, uint32_t mask)
200 //T *nnp = static_cast<T *>(np);
201 static_cast<T *>(np)->write_signal(id, data, mask);
204 void call_write_data8(T *np, uint32_t addr, uint32_t data)
206 //T *nnp = static_cast<T *>(np);
207 static_cast<T *>(np)->write_data8(addr, data);
210 uint32_t call_read_data8(T *np, uint32_t addr)
212 //T *nnp = static_cast<T *>(np);
213 return static_cast<T *>(np)->read_data8(addr);
216 void call_write_dma_data8(T *np, uint32_t addr, uint32_t data)
218 //T *nnp = static_cast<T *>(np);
219 static_cast<T *>(np)->write_dma_data8(addr, data);
222 uint32_t call_read_dma_data8(T *np, uint32_t addr)
224 //T *nnp = static_cast<T *>(np);
225 return static_cast<T *>(np)->read_dma_data8(addr);
228 FM7_MAINMEM(VM* parent_vm, EMU* parent_emu);
230 uint32_t read_data8(uint32_t addr);
231 uint32_t read_dma_data8(uint32_t addr);
232 uint32_t read_dma_io8(uint32_t addr);
233 uint32_t read_data8_main(uint32_t addr, bool dmamode);
235 void write_data8(uint32_t addr, uint32_t data);
236 void write_dma_data8(uint32_t addr, uint32_t data);
237 void write_dma_io8(uint32_t addr, uint32_t data);
238 void write_data8_main(uint32_t addr, uint32_t data, bool dmamode);
240 virtual uint32_t read_data16(uint32_t addr);
241 virtual void write_data16(uint32_t addr, uint32_t data);
243 virtual uint32_t read_data32(uint32_t addr);
244 virtual void write_data32(uint32_t addr, uint32_t data);
246 void initialize(void);
248 void dram_refresh(void);
252 bool get_loadstat_basicrom(void);
253 bool get_loadstat_bootrom_bas(void);
254 bool get_loadstat_bootrom_dos(void);
256 void save_state(FILEIO *state_fio);
257 void update_config();
258 bool load_state(FILEIO *state_fio);
260 void set_context_display(DEVICE *p){
261 display = (DISPLAY *)p;
263 void set_context_maincpu(MC6809 *p){
264 maincpu = (MC6809 *)p;
266 void set_context_mainio(DEVICE *p){
267 mainio = (FM7_MAINIO *)p;
269 #if defined(CAPABLE_DICTROM)
270 void set_context_kanjirom_class1(DEVICE *p){
271 kanjiclass1 = (KANJIROM *)p;
274 void write_signal(int sigid, uint32_t data, uint32_t mask);
275 uint32_t read_signal(int sigid);
276 uint32_t read_io8(uint32_t addr);
277 void write_io8(uint32_t addr, uint32_t data);