source/src/vm/fm7/mainmem_writeseq.cpp

   1 /*
   2  * Main memory for FM-7 [FM7_MAINMEM/MAINMEM_WRITESEQ]
   3  *  Author: K.Ohta
   4  *  Date  : 2017.04.01-
   5  *  License: GPLv2
   6  *
   7  */
   8 #include "vm.h"
   9 #include "emu.h"
  10 #include "fm7_mainmem.h"
  11 #include "fm7_mainio.h"
  12 #include "fm7_display.h"
  13 #include "kanjirom.h"
  14
  15 namespace FM7 {
  16
  17 void FM7_MAINMEM::write_data_tbl(uint32_t addr, uint32_t data, bool dmamode)
  18 {
  19         uint32_t paddr = addr >> 7;
  20         if(data_table[paddr].write_data != NULL) {
  21                 data_table[paddr].write_data[addr & 0x7f] = (uint8_t)data;
  22                 return;
  23         } else if(data_table[paddr].write_func != NULL) {
  24                 void (FM7_MAINMEM::*write_func)(uint32_t, uint32_t, bool);
  25                 write_func = this->data_table[paddr].write_func;
  26                 (this->*write_func)(addr, data, dmamode);
  27         }
  28         return;
  29 }
  30
  31 void FM7_MAINMEM::write_shared_ram(uint32_t realaddr, uint32_t data, bool dmamode)
  32 {
  33         realaddr = realaddr & 0x7f;
  34         if(!sub_halted) return; // Not halt
  35         return call_write_data8(display, realaddr  + 0xd380, data); // Okay?
  36 }
  37
  38 void FM7_MAINMEM::write_direct_access(uint32_t realaddr, uint32_t data, bool dmamode)
  39 {
  40 #if defined(_FM77AV_VARIANTS)
  41         if(!sub_halted) return; // Not halt
  42         if(dmamode) {
  43                 call_write_dma_data8(display, realaddr & 0xffff, data); // Okay?
  44         } else {
  45                 call_write_data8(display, realaddr & 0xffff, data); // Okay?
  46         }
  47 #else
  48         return;
  49 #endif
  50 }
  51
  52 void FM7_MAINMEM::write_ura_basicrom(uint32_t addr, uint32_t data, bool dmamode)
  53 {
  54         addr = addr & 0x7fff;
  55         if (basicrom_fd0f) {
  56                 return;
  57         }
  58         fm7_mainmem_ura[addr] = (uint8_t)data;
  59         return;
  60 }
  61
  62 void FM7_MAINMEM::write_mmio(uint32_t addr, uint32_t data, bool dmamode)
  63 {
  64         addr &= 0xff;
  65         iowait();
  66         call_write_data8(mainio, addr, data);
  67         return;
  68 }
  69
  70 void FM7_MAINMEM::write_bootrom(uint32_t addr, uint32_t data, bool dmamode)
  71 {
  72         addr = addr & 0x1ff;
  73         if(addr <  0x1e0) {
  74                 iowait();
  75 #if defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
  76                 if(boot_ram_write) {
  77                         fm7_bootram[addr] = (uint8_t)data;
  78                 }
  79 #endif
  80                 return;
  81         } else if (addr < 0x1fe) { // VECTOR
  82                 fm7_mainmem_bootrom_vector[addr - 0x1e0] = (uint8_t)data;
  83                 return;
  84         }
  85         else {  // RESET VECTOR
  86 #if defined(_FM77AV_VARIANTS) || defined(_FM77_VARIANTS)
  87                 iowait();
  88                 if(boot_ram_write) {
  89                         fm7_bootram[addr] = (uint8_t)data;
  90                 }
  91 #endif
  92                 return;
  93         }
  94         return;
  95 }
  96
  97 void FM7_MAINMEM::write_data(uint32_t addr, uint32_t data, bool dmamode)
  98 {
  99 #ifdef HAS_MMR
 100         int stat;
 101         if(window_enabled) {
 102                 uint32_t raddr;
 103                 stat = window_convert(addr, &raddr);
 104 #if defined(_FM77AV_VARIANTS)
 105                 if(stat >= 0) {
 106                         fm7_mainmem_mmrbank_0[raddr & 0xffff] = (uint8_t)data;
 107                         return;
 108                 }
 109 #elif defined(_FM77_VARIANTS)
 110                 if(stat >= 0) {
 111                         if((extram_pages >= 3) && (fm7_mainmem_extram != NULL)) {
 112                                 fm7_mainmem_extram[raddr] = (uint8_t)data;;
 113                         }
 114                         return;
 115                 }
 116 #endif
 117         }
 118         if(mmr_enabled) {
 119                 uint32_t segment = 0x00;
 120                 uint32_t raddr = (addr & 0xfff);
 121                 uint32_t mmr_bank;
 122                 if(addr < 0xfc00) {
 123                         if(!dmamode) segment = mmr_segment;
 124 #if 1
 125                         write_with_mmr(addr, segment, data, dmamode);
 126                         return;
 127 #else
 128                         if(!mmr_extend) {
 129                                 mmr_bank = mmr_map_data[(addr >> 12) & 0x000f | ((segment & 0x03) << 4)] & 0x003f;
 130                         } else {
 131                                 mmr_bank = mmr_map_data[(addr >> 12) & 0x000f | ((segment & 0x07) << 4)];
 132                         }
 133                         // Reallocated by MMR
 134                         // Bank 3x : Standard memories.
 135                         if(mmr_bank != 0x3f){
 136                                 raddr = (mmr_bank << 12) | raddr;
 137                                 write_data_tbl(raddr, data, dmamode);
 138                                 return;
 139                         }
 140 # ifdef _FM77AV_VARIANTS
 141                         else if(mmr_bank == 0x3f) {
 142                                 if((raddr >= 0xd80) && (raddr <= 0xd97)) { // MMR AREA
 143                                         iowait(); // OK?
 144                                         return;
 145                                 } else {
 146                                         raddr = raddr | 0x3f000;
 147                                         write_data_tbl(raddr, data, dmamode);
 148                                         return;
 149                                 }
 150                         }
 151 # elif defined(_FM77_VARIANTS)
 152                         else if(mmr_bank == 0x3f) {
 153                                 if((raddr >= 0xc00) && (raddr < 0xe00)) {
 154                                         if(is_basicrom) {
 155                                                 return;
 156                                         } else {
 157                                                 raddr = raddr - 0xc00;
 158                                                 fm77_shadowram[raddr] = (uint8_t)data;
 159                                                 return;
 160                                         }
 161                                 } else if(raddr >= 0xe00) {
 162                                         raddr = raddr - 0x0e00;
 163                                         if(is_basicrom) {
 164                                                 return;
 165                                         } else {
 166                                                 fm7_bootram[raddr] = (uint8_t)data;
 167                                                 return;
 168                                         }
 169                                 } else {
 170                                         raddr = raddr | 0x3f000;
 171                                         write_data_tbl(raddr, data, dmamode);
 172                                         return;
 173                                 }
 174                         }
 175 # endif
 176 #endif
 177                 } else {
 178                         raddr = 0x30000 | (addr & 0xffff);
 179                         write_data_tbl(raddr, data, dmamode);
 180                 }
 181         }
 182 # endif
 183 #if !defined(_FM77AV_VARIANTS) && !defined(_FM77_VARIANTS)
 184         uint32_t raddr = (addr & 0xffff);
 185         write_data_tbl(raddr, data, dmamode);
 186 #else
 187         uint32_t raddr = (addr & 0xffff) | 0x30000;
 188         write_data_tbl(raddr, data, dmamode);
 189 #endif
 190 }
 191
 192 void FM7_MAINMEM::write_data8_main(uint32_t addr, uint32_t data, bool dmamode)
 193 {
 194 #ifdef _FM77AV_VARIANTS
 195         if(initiator_enabled) {
 196                 if((addr >= 0x6000) && (addr < 0x8000)) {
 197                         iowait();
 198                         //uint32_t raddr = addr - 0x6000;
 199                         //return fm7_mainmen_initrom[raddr];
 200                         return;
 201                 }
 202                 if((addr >= 0xfffe) && (addr < 0x10000)) {
 203                         iowait();
 204                         //uint32_t raddr = addr - 0xe000;
 205                         //return fm7_mainmen_initrom[raddr];
 206                         return;
 207                 }
 208         }
 209 #endif
 210         write_data(addr, data, dmamode);
 211 }
 212
 213 }