source/src/vm/i286.cpp

   1 /*
   2         Skelton for retropc emulator
   3
   4         Origin : MAME i286 core
   5         Author : Takeda.Toshiya
   6         Date  : 2012.10.18-
   7
   8         [ i286 ]
   9 */
  10
  11 #include "i286.h"
  12 #ifdef USE_DEBUGGER
  13 #include "debugger.h"
  14 #endif
  15
  16 /* ----------------------------------------------------------------------------
  17         MAME i286
  18 ---------------------------------------------------------------------------- */
  19
  20 #if defined(_MSC_VER) && (_MSC_VER >= 1400)
  21 #pragma warning( disable : 4018 )
  22 #pragma warning( disable : 4146 )
  23 #pragma warning( disable : 4244 )
  24 #pragma warning( disable : 4996 )
  25 #endif
  26
  27 #if defined(HAS_I86)
  28         #define CPU_MODEL i8086
  29 #elif defined(HAS_I88)
  30         #define CPU_MODEL i8088
  31 #elif defined(HAS_I186)
  32         #define CPU_MODEL i80186
  33 #elif defined(HAS_V30)
  34         #define CPU_MODEL v30
  35 #elif defined(HAS_I286)
  36         #define CPU_MODEL i80286
  37 #endif
  38
  39 #ifndef __BIG_ENDIAN__
  40 #define LSB_FIRST
  41 #endif
  42
  43 #ifndef INLINE
  44 #define INLINE inline
  45 #endif
  46
  47 #define logerror(...)
  48
  49 /*****************************************************************************/
  50 /* src/emu/devcpu.h */
  51
  52 // CPU interface functions
  53 #define CPU_INIT_NAME(name)                     cpu_init_##name
  54 #define CPU_INIT(name)                          void* CPU_INIT_NAME(name)()
  55 #define CPU_INIT_CALL(name)                     CPU_INIT_NAME(name)()
  56
  57 #define CPU_RESET_NAME(name)                    cpu_reset_##name
  58 #define CPU_RESET(name)                         void CPU_RESET_NAME(name)(cpu_state *cpustate)
  59 #define CPU_RESET_CALL(name)                    CPU_RESET_NAME(name)(cpustate)
  60
  61 #define CPU_EXECUTE_NAME(name)                  cpu_execute_##name
  62 #define CPU_EXECUTE(name)                       int CPU_EXECUTE_NAME(name)(cpu_state *cpustate, int icount)
  63 #define CPU_EXECUTE_CALL(name)                  CPU_EXECUTE_NAME(name)(cpustate, icount)
  64
  65 #define CPU_DISASSEMBLE_NAME(name)              cpu_disassemble_##name
  66 #define CPU_DISASSEMBLE(name)                   int CPU_DISASSEMBLE_NAME(name)(_TCHAR *buffer, offs_t eip, const UINT8 *oprom)
  67 #define CPU_DISASSEMBLE_CALL(name)              CPU_DISASSEMBLE_NAME(name)(buffer, eip, oprom)
  68
  69 /*****************************************************************************/
  70 /* src/emu/didisasm.h */
  71
  72 // Disassembler constants
  73 const UINT32 DASMFLAG_SUPPORTED     = 0x80000000;   // are disassembly flags supported?
  74 const UINT32 DASMFLAG_STEP_OUT      = 0x40000000;   // this instruction should be the end of a step out sequence
  75 const UINT32 DASMFLAG_STEP_OVER     = 0x20000000;   // this instruction should be stepped over by setting a breakpoint afterwards
  76 const UINT32 DASMFLAG_OVERINSTMASK  = 0x18000000;   // number of extra instructions to skip when stepping over
  77 const UINT32 DASMFLAG_OVERINSTSHIFT = 27;           // bits to shift after masking to get the value
  78 const UINT32 DASMFLAG_LENGTHMASK    = 0x0000ffff;   // the low 16-bits contain the actual length
  79
  80 /*****************************************************************************/
  81 /* src/emu/diexec.h */
  82
  83 // I/O line states
  84 enum line_state
  85 {
  86         CLEAR_LINE = 0,                         // clear (a fired or held) line
  87         ASSERT_LINE,                            // assert an interrupt immediately
  88         HOLD_LINE,                              // hold interrupt line until acknowledged
  89         PULSE_LINE                              // pulse interrupt line instantaneously (only for NMI, RESET)
  90 };
  91
  92 enum
  93 {
  94         INPUT_LINE_IRQ = 0,
  95         INPUT_LINE_NMI
  96 };
  97
  98 /*****************************************************************************/
  99 /* src/emu/emucore.h */
 100
 101 // constants for expression endianness
 102 enum endianness_t
 103 {
 104         ENDIANNESS_LITTLE,
 105         ENDIANNESS_BIG
 106 };
 107
 108 // declare native endianness to be one or the other
 109 #ifdef LSB_FIRST
 110 const endianness_t ENDIANNESS_NATIVE = ENDIANNESS_LITTLE;
 111 #else
 112 const endianness_t ENDIANNESS_NATIVE = ENDIANNESS_BIG;
 113 #endif
 114 // endian-based value: first value is if 'endian' is little-endian, second is if 'endian' is big-endian
 115 #define ENDIAN_VALUE_LE_BE(endian,leval,beval)  (((endian) == ENDIANNESS_LITTLE) ? (leval) : (beval))
 116 // endian-based value: first value is if native endianness is little-endian, second is if native is big-endian
 117 #define NATIVE_ENDIAN_VALUE_LE_BE(leval,beval)  ENDIAN_VALUE_LE_BE(ENDIANNESS_NATIVE, leval, beval)
 118 // endian-based value: first value is if 'endian' matches native, second is if 'endian' doesn't match native
 119 #define ENDIAN_VALUE_NE_NNE(endian,leval,beval) (((endian) == ENDIANNESS_NATIVE) ? (neval) : (nneval))
 120
 121 /*****************************************************************************/
 122 /* src/emu/memory.h */
 123
 124 // offsets and addresses are 32-bit (for now...)
 125 typedef UINT32  offs_t;
 126
 127 /*****************************************************************************/
 128 /* src/osd/osdcomm.h */
 129
 130 /* Highly useful macro for compile-time knowledge of an array size */
 131 #define ARRAY_LENGTH(x)     (sizeof(x) / sizeof(x[0]))
 132
 133 #if defined(HAS_I86) || defined(HAS_I88) || defined(HAS_I186) || defined(HAS_V30)
 134 #define cpu_state i8086_state
 135 #include "mame/emu/cpu/i86/i86.c"
 136 #elif defined(HAS_I286)
 137 #define cpu_state i80286_state
 138 #include "mame/emu/cpu/i86/i286.c"
 139 #endif
 140 #ifdef USE_DEBUGGER
 141 #ifdef HAS_V30
 142 #include "mame/emu/cpu/nec/necdasm.c"
 143 #else
 144 #include "mame/emu/cpu/i386/i386dasm.c"
 145 #endif
 146 #endif
 147
 148 void I286::initialize()
 149 {
 150         DEVICE::initialize();
 151         opaque = CPU_INIT_CALL(CPU_MODEL);
 152
 153         cpu_state *cpustate = (cpu_state *)opaque;
 154         cpustate->pic = d_pic;
 155         cpustate->program = d_mem;
 156         cpustate->io = d_io;
 157 #ifdef I86_PSEUDO_BIOS
 158         cpustate->bios = d_bios;
 159 #endif
 160 #ifdef SINGLE_MODE_DMA
 161         cpustate->dma = d_dma;
 162 #endif
 163 #ifdef USE_DEBUGGER
 164         cpustate->emu = emu;
 165         cpustate->debugger = d_debugger;
 166         cpustate->program_stored = d_mem;
 167         cpustate->io_stored = d_io;
 168
 169         d_debugger->set_context_mem(d_mem);
 170         d_debugger->set_context_io(d_io);
 171 #endif
 172 }
 173
 174 void I286::release()
 175 {
 176         free(opaque);
 177 }
 178
 179 void I286::reset()
 180 {
 181         cpu_state *cpustate = (cpu_state *)opaque;
 182         int busreq = cpustate->busreq;
 183
 184         CPU_RESET_CALL(CPU_MODEL);
 185
 186         cpustate->pic = d_pic;
 187         cpustate->program = d_mem;
 188         cpustate->io = d_io;
 189 #ifdef I86_PSEUDO_BIOS
 190         cpustate->bios = d_bios;
 191 #endif
 192 #ifdef SINGLE_MODE_DMA
 193         cpustate->dma = d_dma;
 194 #endif
 195 #ifdef USE_DEBUGGER
 196         cpustate->emu = emu;
 197         cpustate->debugger = d_debugger;
 198         cpustate->program_stored = d_mem;
 199         cpustate->io_stored = d_io;
 200 #endif
 201         cpustate->busreq = busreq;
 202 }
 203
 204 int I286::run(int icount)
 205 {
 206         cpu_state *cpustate = (cpu_state *)opaque;
 207         return CPU_EXECUTE_CALL(CPU_MODEL);
 208 }
 209
 210 void I286::write_signal(int id, uint32_t data, uint32_t mask)
 211 {
 212         cpu_state *cpustate = (cpu_state *)opaque;
 213
 214         if(id == SIG_CPU_NMI) {
 215                 set_irq_line(cpustate, INPUT_LINE_NMI, (data & mask) ? HOLD_LINE : CLEAR_LINE);
 216         } else if(id == SIG_CPU_IRQ) {
 217                 set_irq_line(cpustate, INPUT_LINE_IRQ, (data & mask) ? HOLD_LINE : CLEAR_LINE);
 218         } else if(id == SIG_CPU_BUSREQ) {
 219                 cpustate->busreq = (data & mask) ? 1 : 0;
 220         } else if(id == SIG_I86_TEST) {
 221                 cpustate->test_state = (data & mask) ? 1 : 0;
 222 #ifdef HAS_I286
 223         } else if(id == SIG_I286_A20) {
 224                 i80286_set_a20_line(cpustate, data & mask);
 225 #endif
 226         }
 227 }
 228
 229 void I286::set_intr_line(bool line, bool pending, uint32_t bit)
 230 {
 231         cpu_state *cpustate = (cpu_state *)opaque;
 232         set_irq_line(cpustate, INPUT_LINE_IRQ, line ? HOLD_LINE : CLEAR_LINE);
 233 }
 234
 235 void I286::set_extra_clock(int icount)
 236 {
 237         cpu_state *cpustate = (cpu_state *)opaque;
 238         cpustate->extra_cycles += icount;
 239 }
 240
 241 int I286::get_extra_clock()
 242 {
 243         cpu_state *cpustate = (cpu_state *)opaque;
 244         return cpustate->extra_cycles;
 245 }
 246
 247 uint32_t I286::get_pc()
 248 {
 249         cpu_state *cpustate = (cpu_state *)opaque;
 250         return cpustate->prevpc;
 251 }
 252
 253 uint32_t I286::get_next_pc()
 254 {
 255         cpu_state *cpustate = (cpu_state *)opaque;
 256         return cpustate->pc;
 257 }
 258
 259 #ifdef USE_DEBUGGER
 260 void I286::write_debug_data8(uint32_t addr, uint32_t data)
 261 {
 262         int wait;
 263         d_mem->write_data8w(addr, data, &wait);
 264 }
 265
 266 uint32_t I286::read_debug_data8(uint32_t addr)
 267 {
 268         int wait;
 269         return d_mem->read_data8w(addr, &wait);
 270 }
 271
 272 void I286::write_debug_data16(uint32_t addr, uint32_t data)
 273 {
 274         int wait;
 275         d_mem->write_data16w(addr, data, &wait);
 276 }
 277
 278 uint32_t I286::read_debug_data16(uint32_t addr)
 279 {
 280         int wait;
 281         return d_mem->read_data16w(addr, &wait);
 282 }
 283
 284 void I286::write_debug_io8(uint32_t addr, uint32_t data)
 285 {
 286         int wait;
 287         d_io->write_io8w(addr, data, &wait);
 288 }
 289
 290 uint32_t I286::read_debug_io8(uint32_t addr) {
 291         int wait;
 292         return d_io->read_io8w(addr, &wait);
 293 }
 294
 295 void I286::write_debug_io16(uint32_t addr, uint32_t data)
 296 {
 297         int wait;
 298         d_io->write_io16w(addr, data, &wait);
 299 }
 300
 301 uint32_t I286::read_debug_io16(uint32_t addr) {
 302         int wait;
 303         return d_io->read_io16w(addr, &wait);
 304 }
 305
 306 bool I286::write_debug_reg(const _TCHAR *reg, uint32_t data)
 307 {
 308         cpu_state *cpustate = (cpu_state *)opaque;
 309         if(_tcsicmp(reg, _T("IP")) == 0) {
 310                 cpustate->pc = ((data & 0xffff) + cpustate->base[CS]) & AMASK;
 311                 CHANGE_PC(cpustate->pc);
 312         } else if(_tcsicmp(reg, _T("AX")) == 0) {
 313                 cpustate->regs.w[AX] = data;
 314         } else if(_tcsicmp(reg, _T("BX")) == 0) {
 315                 cpustate->regs.w[BX] = data;
 316         } else if(_tcsicmp(reg, _T("CX")) == 0) {
 317                 cpustate->regs.w[CX] = data;
 318         } else if(_tcsicmp(reg, _T("DX")) == 0) {
 319                 cpustate->regs.w[DX] = data;
 320         } else if(_tcsicmp(reg, _T("SP")) == 0) {
 321                 cpustate->regs.w[SP] = data;
 322         } else if(_tcsicmp(reg, _T("BP")) == 0) {
 323                 cpustate->regs.w[BP] = data;
 324         } else if(_tcsicmp(reg, _T("SI")) == 0) {
 325                 cpustate->regs.w[SI] = data;
 326         } else if(_tcsicmp(reg, _T("DI")) == 0) {
 327                 cpustate->regs.w[DI] = data;
 328         } else if(_tcsicmp(reg, _T("AL")) == 0) {
 329                 cpustate->regs.b[AL] = data;
 330         } else if(_tcsicmp(reg, _T("AH")) == 0) {
 331                 cpustate->regs.b[AH] = data;
 332         } else if(_tcsicmp(reg, _T("BL")) == 0) {
 333                 cpustate->regs.b[BL] = data;
 334         } else if(_tcsicmp(reg, _T("BH")) == 0) {
 335                 cpustate->regs.b[BH] = data;
 336         } else if(_tcsicmp(reg, _T("CL")) == 0) {
 337                 cpustate->regs.b[CL] = data;
 338         } else if(_tcsicmp(reg, _T("CH")) == 0) {
 339                 cpustate->regs.b[CH] = data;
 340         } else if(_tcsicmp(reg, _T("DL")) == 0) {
 341                 cpustate->regs.b[DL] = data;
 342         } else if(_tcsicmp(reg, _T("DH")) == 0) {
 343                 cpustate->regs.b[DH] = data;
 344         } else {
 345                 return false;
 346         }
 347         return true;
 348 }
 349
 350 uint32_t I286::read_debug_reg(const _TCHAR *reg)
 351 {
 352         cpu_state *cpustate = (cpu_state *)opaque;
 353         if(_tcsicmp(reg, _T("IP")) == 0) {
 354                 return cpustate->pc - cpustate->base[CS];
 355         } else if(_tcsicmp(reg, _T("AX")) == 0) {
 356                 return cpustate->regs.w[AX];
 357         } else if(_tcsicmp(reg, _T("BX")) == 0) {
 358                 return cpustate->regs.w[BX];
 359         } else if(_tcsicmp(reg, _T("CX")) == 0) {
 360                 return cpustate->regs.w[CX];
 361         } else if(_tcsicmp(reg, _T("DX")) == 0) {
 362                 return cpustate->regs.w[DX];
 363         } else if(_tcsicmp(reg, _T("SP")) == 0) {
 364                 return cpustate->regs.w[SP];
 365         } else if(_tcsicmp(reg, _T("BP")) == 0) {
 366                 return cpustate->regs.w[BP];
 367         } else if(_tcsicmp(reg, _T("SI")) == 0) {
 368                 return cpustate->regs.w[SI];
 369         } else if(_tcsicmp(reg, _T("DI")) == 0) {
 370                 return cpustate->regs.w[DI];
 371         } else if(_tcsicmp(reg, _T("AL")) == 0) {
 372                 return cpustate->regs.b[AL];
 373         } else if(_tcsicmp(reg, _T("AH")) == 0) {
 374                 return cpustate->regs.b[AH];
 375         } else if(_tcsicmp(reg, _T("BL")) == 0) {
 376                 return cpustate->regs.b[BL];
 377         } else if(_tcsicmp(reg, _T("BH")) == 0) {
 378                 return cpustate->regs.b[BH];
 379         } else if(_tcsicmp(reg, _T("CL")) == 0) {
 380                 return cpustate->regs.b[CL];
 381         } else if(_tcsicmp(reg, _T("CH")) == 0) {
 382                 return cpustate->regs.b[CH];
 383         } else if(_tcsicmp(reg, _T("DL")) == 0) {
 384                 return cpustate->regs.b[DL];
 385         } else if(_tcsicmp(reg, _T("DH")) == 0) {
 386                 return cpustate->regs.b[DH];
 387         }
 388         return 0;
 389 }
 390
 391 void I286::get_debug_regs_info(_TCHAR *buffer, size_t buffer_len)
 392 {
 393         cpu_state *cpustate = (cpu_state *)opaque;
 394         my_stprintf_s(buffer, buffer_len,
 395         _T("AX=%04X  BX=%04X CX=%04X DX=%04X SP=%04X  BP=%04X  SI=%04X  DI=%04X\nDS=%04X  ES=%04X SS=%04X CS=%04X IP=%04X  FLAG=[%c%c%c%c%c%c%c%c%c]\nClocks = %llu (%llu) Since Scanline = %d/%d (%d/%d)"),
 396         cpustate->regs.w[AX], cpustate->regs.w[BX], cpustate->regs.w[CX], cpustate->regs.w[DX], cpustate->regs.w[SP], cpustate->regs.w[BP], cpustate->regs.w[SI], cpustate->regs.w[DI],
 397         cpustate->sregs[DS], cpustate->sregs[ES], cpustate->sregs[SS], cpustate->sregs[CS], cpustate->pc - cpustate->base[CS],
 398         OF ? _T('O') : _T('-'), DF ? _T('D') : _T('-'), cpustate->IF ? _T('I') : _T('-'), cpustate->TF ? _T('T') : _T('-'),
 399         SF ? _T('S') : _T('-'), ZF ? _T('Z') : _T('-'), AF ? _T('A') : _T('-'), PF ? _T('P') : _T('-'), CF ? _T('C') : _T('-'),
 400         cpustate->total_icount, cpustate->total_icount - cpustate->prev_total_icount,
 401         get_passed_clock_since_vline(), get_cur_vline_clocks(), get_cur_vline(), get_lines_per_frame());
 402         cpustate->prev_total_icount = cpustate->total_icount;
 403 }
 404
 405 int I286::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
 406 {
 407         cpu_state *cpustate = (cpu_state *)opaque;
 408         UINT64 eip = pc - cpustate->base[CS];
 409         UINT8 ops[16];
 410         for(int i = 0; i < 16; i++) {
 411                 int wait;
 412                 ops[i] = d_mem->read_data8w(pc + i, &wait);
 413         }
 414         UINT8 *oprom = ops;
 415
 416 #ifdef HAS_V30
 417         return CPU_DISASSEMBLE_CALL(nec_generic) & DASMFLAG_LENGTHMASK;
 418 #else
 419         return CPU_DISASSEMBLE_CALL(x86_16) & DASMFLAG_LENGTHMASK;
 420 #endif
 421 }
 422 #endif
 423
 424 #ifdef HAS_I286
 425 void I286::set_address_mask(uint32_t mask)
 426 {
 427         cpu_state *cpustate = (cpu_state *)opaque;
 428         cpustate->amask = mask;
 429 }
 430
 431 uint32_t I286::get_address_mask()
 432 {
 433         cpu_state *cpustate = (cpu_state *)opaque;
 434         return cpustate->amask;
 435 }
 436
 437 void I286::set_shutdown_flag(int shutdown)
 438 {
 439         cpu_state *cpustate = (cpu_state *)opaque;
 440         cpustate->shutdown = shutdown;
 441 }
 442
 443 int I286::get_shutdown_flag()
 444 {
 445         cpu_state *cpustate = (cpu_state *)opaque;
 446         return cpustate->shutdown;
 447 }
 448 #endif
 449
 450 #define STATE_VERSION   5
 451
 452 void I286::process_state_cpustate(FILEIO* state_fio, bool loading)
 453 {
 454 #if defined(HAS_I86) || defined(HAS_I88) || defined(HAS_I186) || defined(HAS_V30)
 455         struct i8086_state *cpustate = (struct i8086_state *)opaque;
 456
 457         state_fio->StateBuffer(&(cpustate->regs.b[0]), 16, 1);
 458         state_fio->StateUint32(cpustate->pc);
 459         state_fio->StateUint32(cpustate->prevpc);
 460         for(int i = 0; i < 4; i++) {
 461                 state_fio->StateUint32(cpustate->base[i]);
 462         }
 463         for(int i = 0; i < 4; i++) {
 464                 state_fio->StateUint16(cpustate->sregs[i]);
 465         }
 466         state_fio->StateUint16(cpustate->flags);
 467         state_fio->StateInt32(cpustate->AuxVal);
 468         state_fio->StateInt32(cpustate->OverVal);
 469         state_fio->StateInt32(cpustate->SignVal);
 470         state_fio->StateInt32(cpustate->ZeroVal);
 471         state_fio->StateInt32(cpustate->CarryVal);
 472         state_fio->StateInt32(cpustate->DirVal);
 473         state_fio->StateUint8(cpustate->ParityVal);
 474         state_fio->StateUint8(cpustate->TF);
 475         state_fio->StateUint8(cpustate->IF);
 476         state_fio->StateUint8(cpustate->MF);
 477
 478         state_fio->StateUint8(cpustate->int_vector);
 479         state_fio->StateInt8(cpustate->nmi_state);
 480         state_fio->StateInt8(cpustate->irq_state);
 481         state_fio->StateInt8(cpustate->test_state);
 482         state_fio->StateUint8(cpustate->rep_in_progress);
 483         state_fio->StateInt32(cpustate->extra_cycles);
 484
 485         state_fio->StateInt32(cpustate->halted);
 486         state_fio->StateInt32(cpustate->busreq);
 487
 488         state_fio->StateUint16(cpustate->ip);
 489         state_fio->StateUint32(cpustate->sp);
 490
 491   #ifdef USE_DEBUGGER
 492         state_fio->StateUint64(cpustate->total_icount);
 493   #endif
 494         state_fio->StateInt32(cpustate->icount);
 495
 496         state_fio->StateUint8(cpustate->seg_prefix);
 497         state_fio->StateUint8(cpustate->prefix_seg);
 498         state_fio->StateUint32(cpustate->ea);
 499         state_fio->StateUint16(cpustate->eo);
 500         state_fio->StateUint8(cpustate->ea_seg);
 501
 502 #elif defined(HAS_I286)
 503
 504         struct i80286_state *cpustate = (struct i80286_state *)opaque;
 505
 506         state_fio->StateBuffer(&(cpustate->regs.b[0]), 16, 1);
 507         state_fio->StateUint32(cpustate->amask);
 508         state_fio->StateUint32(cpustate->pc);
 509         state_fio->StateUint32(cpustate->prevpc);
 510         state_fio->StateUint16(cpustate->flags);
 511         state_fio->StateUint16(cpustate->msw);
 512         for(int i = 0; i < 4; i++) {
 513                 state_fio->StateUint32(cpustate->base[i]);
 514         }
 515         for(int i = 0; i < 4; i++) {
 516                 state_fio->StateUint16(cpustate->sregs[i]);
 517         }
 518         for(int i = 0; i < 4; i++) {
 519                 state_fio->StateUint16(cpustate->limit[i]);
 520         }
 521         state_fio->StateBuffer(cpustate->rights, 4, 1);
 522         for(int i = 0; i < 4; i++) {
 523                 state_fio->StateBool(cpustate->valid[i]);
 524         }
 525         state_fio->StateUint32(cpustate->gdtr.base);
 526         state_fio->StateUint16(cpustate->gdtr.limit);
 527
 528         state_fio->StateUint32(cpustate->idtr.base);
 529         state_fio->StateUint16(cpustate->idtr.limit);
 530
 531         state_fio->StateUint16(cpustate->ldtr.sel);
 532         state_fio->StateUint32(cpustate->ldtr.base);
 533         state_fio->StateUint16(cpustate->ldtr.limit);
 534         state_fio->StateUint8(cpustate->ldtr.rights);
 535
 536         state_fio->StateUint16(cpustate->tr.sel);
 537         state_fio->StateUint32(cpustate->tr.base);
 538         state_fio->StateUint16(cpustate->tr.limit);
 539         state_fio->StateUint8(cpustate->tr.rights);
 540
 541         state_fio->StateInt32(cpustate->AuxVal);
 542         state_fio->StateInt32(cpustate->OverVal);
 543         state_fio->StateInt32(cpustate->SignVal);
 544         state_fio->StateInt32(cpustate->ZeroVal);
 545         state_fio->StateInt32(cpustate->CarryVal);
 546         state_fio->StateInt32(cpustate->DirVal);
 547         state_fio->StateUint8(cpustate->ParityVal);
 548         state_fio->StateUint8(cpustate->TF);
 549         state_fio->StateUint8(cpustate->IF);
 550         state_fio->StateUint8(cpustate->MF);
 551
 552         state_fio->StateInt8(cpustate->nmi_state);
 553         state_fio->StateInt8(cpustate->irq_state);
 554         state_fio->StateInt8(cpustate->test_state);
 555         state_fio->StateUint8(cpustate->rep_in_progress);
 556         state_fio->StateInt32(cpustate->extra_cycles);
 557
 558         state_fio->StateInt32(cpustate->halted);
 559         state_fio->StateInt32(cpustate->busreq);
 560         state_fio->StateInt32(cpustate->trap_level);
 561         state_fio->StateInt32(cpustate->shutdown);
 562
 563
 564   #ifdef USE_DEBUGGER
 565         state_fio->StateUint64(cpustate->total_icount);
 566   #endif
 567         state_fio->StateInt32(cpustate->icount);
 568
 569         state_fio->StateUint8(cpustate->seg_prefix);
 570         state_fio->StateUint8(cpustate->prefix_seg);
 571         state_fio->StateUint32(cpustate->ea);
 572         state_fio->StateUint16(cpustate->eo);
 573         state_fio->StateUint8(cpustate->ea_seg);
 574 #endif
 575 }
 576
 577 bool I286::process_state(FILEIO* state_fio, bool loading)
 578 {
 579         if(!state_fio->StateCheckUint32(STATE_VERSION)) {
 580                 return false;
 581         }
 582         if(!state_fio->StateCheckInt32(this_device_id)) {
 583                 return false;
 584         }
 585         //state_fio->StateBuffer(opaque, sizeof(cpu_state), 1);
 586         process_state_cpustate(state_fio, loading);
 587
 588         // post process
 589         if(loading) {
 590                 cpu_state *cpustate = (cpu_state *)opaque;
 591                 cpustate->pic = d_pic;
 592                 cpustate->program = d_mem;
 593                 cpustate->io = d_io;
 594 #ifdef I86_PSEUDO_BIOS
 595                 cpustate->bios = d_bios;
 596 #endif
 597 #ifdef SINGLE_MODE_DMA
 598                 cpustate->dma = d_dma;
 599 #endif
 600 #ifdef USE_DEBUGGER
 601                 cpustate->emu = emu;
 602                 cpustate->debugger = d_debugger;
 603                 cpustate->program_stored = d_mem;
 604                 cpustate->io_stored = d_io;
 605                 cpustate->prev_total_icount = cpustate->total_icount;
 606 #endif
 607         }
 608         return true;
 609 }