2 SHARP MZ-5500 Emulator 'EmuZ-5500'
4 Author : Takeda.Toshiya
14 #define SET_BANK(s, e, w, r) { \
15 int sb = (s) >> 14, eb = (e) >> 14; \
16 for(int i = sb; i <= eb; i++) { \
20 wbank[i] = (w) + 0x4000 * (i - sb); \
25 rbank[i] = (r) + 0x4000 * (i - sb); \
30 void MEMORY::initialize()
33 memset(ram, 0, sizeof(ram));
34 memset(vram, 0, sizeof(vram));
35 memset(ipl, 0xff, sizeof(ipl));
36 memset(kanji, 0xff, sizeof(kanji));
37 memset(dic, 0xff, sizeof(dic));
39 memset(dic2, 0xff, sizeof(dic2));
41 #if defined(_MZ6500) || defined(_MZ6550)
42 memset(mz1r32, 0, sizeof(mz1r32));
44 memset(rdmy, 0xff, sizeof(rdmy));
47 FILEIO* fio = new FILEIO();
48 if(fio->Fopen(create_local_path(_T("IPL.ROM")), FILEIO_READ_BINARY)) {
49 fio->Fread(ipl, sizeof(ipl), 1);
52 if(fio->Fopen(create_local_path(_T("KANJI.ROM")), FILEIO_READ_BINARY)) {
53 fio->Fread(kanji, sizeof(kanji), 1);
56 if(fio->Fopen(create_local_path(_T("DICT.ROM")), FILEIO_READ_BINARY)) {
57 fio->Fread(dic, sizeof(dic), 1);
61 if(fio->Fopen(create_local_path(_T("DICT2.ROM")), FILEIO_READ_BINARY)) {
62 fio->Fread(dic2, sizeof(dic2), 1);
69 #if defined(_MZ6500) || defined(_MZ6550)
70 SET_BANK(0x00000, 0x9ffff, ram, ram);
72 SET_BANK(0x00000, 0x7ffff, ram, ram);
73 SET_BANK(0x80000, 0x9ffff, wdmy, rdmy); // aux
75 SET_BANK(0xa0000, 0xbffff, wdmy, kanji);
76 SET_BANK(0xc0000, 0xeffff, vram, vram);
78 SET_BANK(0xf0000, 0xf7fff, wdmy, rdmy); // aux
79 SET_BANK(0xf8000, 0xfffff, wdmy, ipl);
81 SET_BANK(0xf0000, 0xfbfff, wdmy, rdmy); // aux
82 SET_BANK(0xfc000, 0xfffff, wdmy, ipl);
96 void MEMORY::write_data8(uint32_t addr, uint32_t data)
99 // if((0x80000 <= addr && addr < 0xa0000) || (0xf0000 <= addr && addr < 0xfc000)) {
100 // d_cpu->write_signal(SIG_CPU_NMI, 1, 1);
102 wbank[addr >> 14][addr & 0x3fff] = data;
105 uint32_t MEMORY::read_data8(uint32_t addr)
108 // if((0x80000 <= addr && addr < 0xa0000) || (0xf0000 <= addr && addr < 0xfc000)) {
109 // d_cpu->write_signal(SIG_CPU_NMI, 1, 1);
111 return rbank[addr >> 14][addr & 0x3fff];
114 void MEMORY::write_dma_data8(uint32_t addr, uint32_t data)
116 addr = (addr & 0xffff) | haddr;
117 // if((0x80000 <= addr && addr < 0xa0000) || (0xf0000 <= addr && addr < 0xfc000)) {
118 // d_cpu->write_signal(SIG_CPU_NMI, 1, 1);
120 wbank[addr >> 14][addr & 0x3fff] = data;
123 uint32_t MEMORY::read_dma_data8(uint32_t addr)
125 addr = (addr & 0xffff) | haddr;
126 // if((0x80000 <= addr && addr < 0xa0000) || (0xf0000 <= addr && addr < 0xfc000)) {
127 // d_cpu->write_signal(SIG_CPU_NMI, 1, 1);
129 return rbank[addr >> 14][addr & 0x3fff];
132 void MEMORY::write_io8(uint32_t addr, uint32_t data)
134 switch(addr & 0xff) {
136 haddr = (data & 0xf0) << 12;
138 #if defined(_MZ6500) || defined(_MZ6550)
141 if(bank2 != (data & 0x0f)) {
150 uint32_t MEMORY::read_io8(uint32_t addr)
152 return 0xf0 | bank2; // ???
155 void MEMORY::write_signal(int id, uint32_t data, uint32_t mask)
163 void MEMORY::update_bank()
165 switch(bank1 & 0xe0) {
167 SET_BANK(0x0a0000, 0x0bffff, wdmy, kanji);
170 SET_BANK(0x0a0000, 0x0bffff, wdmy, kanji + 0x20000);
173 SET_BANK(0x0a0000, 0x0bffff, wdmy, dic);
176 SET_BANK(0x0a0000, 0x0bffff, wdmy, dic + 0x20000);
178 #if defined(_MZ6500) || defined(_MZ6550)
182 int ofs = 0x20000 * ((bank2 >> 1) & 7);
183 SET_BANK(0x0a0000, 0x0bffff, mz1r32 + ofs, mz1r32 + ofs);
188 SET_BANK(0x0a0000, 0x0bffff, wdmy, rdmy);
193 #define STATE_VERSION 1
195 bool MEMORY::process_state(FILEIO* state_fio, bool loading)
197 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
200 if(!state_fio->StateCheckInt32(this_device_id)) {
203 state_fio->StateBuffer(ram, sizeof(ram), 1);
204 state_fio->StateBuffer(vram, sizeof(vram), 1);
205 #if defined(_MZ6500) || defined(_MZ6550)
206 state_fio->StateBuffer(mz1r32, sizeof(mz1r32), 1);
208 state_fio->StateUint8(bank1);
209 state_fio->StateUint8(bank2);
210 state_fio->StateUint32(haddr);