2 TOSHIBA PASOPIA 7 Emulator 'EmuPIA7'
4 Author : Takeda.Toshiya
14 #define SET_BANK(s, e, w, r) { \
15 int sb = (s) >> 12, eb = (e) >> 12; \
16 for(int i = sb; i <= eb; i++) { \
20 wbank[i] = (w) + 0x1000 * (i - sb); \
25 rbank[i] = (r) + 0x1000 * (i - sb); \
30 void PASOPIA7_MEMORY::initialize()
32 memset(bios, 0xff, sizeof(bios));
33 memset(basic, 0xff, sizeof(basic));
34 memset(rdmy, 0xff, sizeof(rdmy));
37 FILEIO* fio = new FILEIO();
38 if(fio->Fopen(create_local_path(_T("BIOS.ROM")), FILEIO_READ_BINARY)) {
39 fio->Fread(bios, sizeof(bios), 1);
42 if(fio->Fopen(create_local_path(_T("BASIC.ROM")), FILEIO_READ_BINARY)) {
43 fio->Fread(basic, sizeof(basic), 1);
52 vram_sel = pal_sel = attr_wrap = false;
55 void PASOPIA7_MEMORY::reset()
57 memset(vram, 0, sizeof(vram));
60 void PASOPIA7_MEMORY::write_data8(uint32_t addr, uint32_t data)
63 if(vram_sel && (addr & 0xc000) == 0x8000) {
64 if(pal_sel && !(plane & 0x70)) {
65 pal[addr & 0x0f] = data & 0x0f;
68 uint32_t laddr = addr & 0x3fff;
70 vram[0x0000 | laddr] = (plane & 0x1) ? data : 0xff;
73 vram[0x4000 | laddr] = (plane & 0x2) ? data : 0xff;
76 vram[0x8000 | laddr] = (plane & 0x4) ? data : 0xff;
77 attr_latch = attr_wrap ? attr_latch : attr_data;
78 vram[0xc000 | laddr] = attr_latch;
80 d_pio0->write_signal(SIG_I8255_PORT_B, (attr_latch << 4) | (attr_latch & 7), 0x87);
84 wbank[addr >> 12][addr & 0xfff] = data;
87 uint32_t PASOPIA7_MEMORY::read_data8(uint32_t addr)
90 if(vram_sel && (addr & 0xc000) == 0x8000) {
91 if(pal_sel && !(plane & 0x70)) {
92 return pal[addr & 0x0f];
94 uint32_t laddr = addr & 0x3fff, val = 0xff;
95 if((plane & 0x11) == 0x11) {
96 val &= vram[0x0000 | laddr];
98 if((plane & 0x22) == 0x22) {
99 val &= vram[0x4000 | laddr];
101 if((plane & 0x44) == 0x44) {
102 attr_latch = vram[0xc000 | laddr];
103 val &= vram[0x8000 | laddr];
105 d_pio0->write_signal(SIG_I8255_PORT_B, (attr_latch << 4) | (attr_latch & 7), 0x87);
109 return rbank[addr >> 12][addr & 0xfff];
112 void PASOPIA7_MEMORY::write_io8(uint32_t addr, uint32_t data)
114 if(mem_map != (data & 7)) {
118 vram_sel = ((data & 4) != 0);
121 d_iobus->write_signal(SIG_IOBUS_MIO, data, 8);
124 d_pio2->write_signal(SIG_I8255_PORT_C, data, 3);
127 void PASOPIA7_MEMORY::write_signal(int id, uint32_t data, uint32_t mask)
129 if(id == SIG_MEMORY_I8255_1_A) {
131 } else if(id == SIG_MEMORY_I8255_1_B) {
132 attr_data = data & 0x0f;
133 } else if(id == SIG_MEMORY_I8255_1_C) {
134 attr_wrap = ((data & 0x10) != 0);
135 pal_sel = ((data & 0x0c) != 0);
139 void PASOPIA7_MEMORY::update_memory_map()
141 if(mem_map == 0xff) {
142 SET_BANK(0x0000, 0x3fff, wdmy, bios);
143 SET_BANK(0x4000, 0x7fff, wdmy, bios);
144 SET_BANK(0x8000, 0xbfff, wdmy, bios);
145 SET_BANK(0xc000, 0xffff, wdmy, bios);
148 SET_BANK(0x0000, 0x3fff, ram + 0x0000, ram + 0x0000);
150 SET_BANK(0x0000, 0x3fff, ram + 0x0000, basic + 0x0000);
153 SET_BANK(0x4000, 0x7fff, ram + 0x4000, bios + 0x0000);
154 } else if(mem_map & 2) {
155 SET_BANK(0x4000, 0x7fff, ram + 0x4000, ram + 0x4000);
157 SET_BANK(0x4000, 0x7fff, ram + 0x4000, basic + 0x4000);
160 SET_BANK(0x8000, 0xbfff, wdmy, rdmy);
162 SET_BANK(0x8000, 0xbfff, ram + 0x8000, ram + 0x8000);
164 SET_BANK(0xc000, 0xffff, ram + 0xc000, ram + 0xc000);
168 #define STATE_VERSION 1
170 bool PASOPIA7_MEMORY::process_state(FILEIO* state_fio, bool loading)
172 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
175 if(!state_fio->StateCheckInt32(this_device_id)) {
178 state_fio->StateBuffer(ram, sizeof(ram), 1);
179 state_fio->StateBuffer(vram, sizeof(vram), 1);
180 state_fio->StateBuffer(pal, sizeof(pal), 1);
181 state_fio->StateUint8(mem_map);
182 state_fio->StateUint8(plane);
183 state_fio->StateUint8(attr_data);
184 state_fio->StateUint8(attr_latch);
185 state_fio->StateBool(vram_sel);
186 state_fio->StateBool(pal_sel);
187 state_fio->StateBool(attr_wrap);