source/src/vm/pc9801/dmareg.cpp

   1 /*
   2         NEC PC-9801VX Emulator 'ePC-9801VX'
   3         NEC PC-9801RA Emulator 'ePC-9801RA'
   4         NEC PC-98XA Emulator 'ePC-98XA'
   5         NEC PC-98XL Emulator 'ePC-98XL'
   6         NEC PC-98RL Emulator 'ePC-98RL'
   7
   8         Author : Takeda.Toshiya
   9         Date   : 2017.06.25-
  10
  11         [ dma regs ]
  12 */
  13
  14 #include "dmareg.h"
  15 #include "../i8237.h"
  16
  17 namespace PC9801 {
  18
  19 static const int bank_lo_id[] = {
  20         SIG_I8237_BANK1, SIG_I8237_BANK2, SIG_I8237_BANK3, SIG_I8237_BANK0,
  21 };
  22 static const int bank_hi_id[] = {
  23         SIG_I8237_BANK0, SIG_I8237_BANK1, SIG_I8237_BANK2, SIG_I8237_BANK3,
  24 };
  25 static const int mask_id[] = {
  26         SIG_I8237_MASK0, SIG_I8237_MASK1, SIG_I8237_MASK2, SIG_I8237_MASK3,
  27 };
  28
  29 void DMAREG::write_io8(uint32_t addr, uint32_t data)
  30 {
  31         switch(addr) {
  32         case 0x0021:
  33         case 0x0023:
  34         case 0x0025:
  35         case 0x0027:
  36 #if defined(SUPPORT_32BIT_ADDRESS)
  37                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0xff, 0x00ff);
  38 #elif defined(_PC98XA)
  39                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0x7f, 0x00ff);
  40 #elif defined(SUPPORT_24BIT_ADDRESS)
  41                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0xff, 0x00ff);
  42 #else
  43                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0x0f, 0x00ff);
  44 #endif
  45                 break;
  46 #if defined(SUPPORT_24BIT_ADDRESS) || defined(SUPPORT_32BIT_ADDRESS)
  47         case 0x0029:
  48                 switch(data & 0x0c) {
  49                 case 0x00:
  50                         d_dma->write_signal(mask_id[data & 3], 0x0000, 0xffff); // 64KB
  51                         break;
  52                 case 0x04:
  53                         d_dma->write_signal(mask_id[data & 3], 0x000f, 0xffff); // 1MB
  54                         break;
  55                 case 0x0c:
  56                         d_dma->write_signal(mask_id[data & 3], 0x00ff, 0xffff); // 16MB
  57                         break;
  58                 }
  59                 break;
  60 #endif
  61 #if defined(SUPPORT_32BIT_ADDRESS)
  62         case 0x0e05:
  63         case 0x0e07:
  64         case 0x0e09:
  65         case 0x0e0b:
  66                 d_dma->write_signal(bank_hi_id[((addr - 0xe05) >> 1) & 3], (data & 0xff) << 8, 0xff00);
  67                 break;
  68 #endif
  69         }
  70 }
  71
  72 uint32_t DMAREG::read_io8(uint32_t addr)
  73 {
  74         switch(addr) {
  75         case 0x0021:
  76         case 0x0023:
  77         case 0x0025:
  78         case 0x0027:
  79                 return d_dma->read_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3]);
  80         }
  81         return 0xff;
  82 }
  83
  84 /*
  85 #define STATE_VERSION   1
  86
  87 bool DMAREG::process_state(FILEIO* state_fio, bool loading)
  88 {
  89         if(!state_fio->StateCheckUint32(STATE_VERSION)) {
  90                 return false;
  91         }
  92         if(!state_fio->StateCheckInt32(this_device_id)) {
  93                 return false;
  94         }
  95         return true;
  96 }
  97
  98 */
  99
 100 }
 101