source/src/vm/pc9801/dmareg.cpp

   1 /*
   2         NEC PC-9801VX Emulator 'ePC-9801VX'
   3         NEC PC-9801RA Emulator 'ePC-9801RA'
   4         NEC PC-98XA Emulator 'ePC-98XA'
   5         NEC PC-98XL Emulator 'ePC-98XL'
   6         NEC PC-98RL Emulator 'ePC-98RL'
   7
   8         Author : Takeda.Toshiya
   9         Date   : 2017.06.25-
  10
  11         [ dma regs ]
  12 */
  13
  14 #include "dmareg.h"
  15 #include "../i8237.h"
  16
  17 static const int bank_lo_id[] = {
  18         SIG_I8237_BANK1, SIG_I8237_BANK2, SIG_I8237_BANK3, SIG_I8237_BANK0,
  19 };
  20 static const int bank_hi_id[] = {
  21         SIG_I8237_BANK0, SIG_I8237_BANK1, SIG_I8237_BANK2, SIG_I8237_BANK3,
  22 };
  23 static const int mask_id[] = {
  24         SIG_I8237_MASK0, SIG_I8237_MASK1, SIG_I8237_MASK2, SIG_I8237_MASK3,
  25 };
  26
  27 void DMAREG::write_io8(uint32_t addr, uint32_t data)
  28 {
  29         switch(addr) {
  30         case 0x0021:
  31         case 0x0023:
  32         case 0x0025:
  33         case 0x0027:
  34 #if defined(SUPPORT_32BIT_ADDRESS)
  35                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0xff, 0x00ff);
  36 #elif defined(_PC98XA)
  37                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0x7f, 0x00ff);
  38 #elif defined(SUPPORT_24BIT_ADDRESS)
  39                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0xff, 0x00ff);
  40 #else
  41                 d_dma->write_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3], data & 0x0f, 0x00ff);
  42 #endif
  43                 break;
  44 #if defined(SUPPORT_24BIT_ADDRESS) || defined(SUPPORT_32BIT_ADDRESS)
  45         case 0x0029:
  46                 switch(data & 0x0c) {
  47                 case 0x00:
  48                         d_dma->write_signal(mask_id[data & 3], 0x0000, 0xffff); // 64KB
  49                         break;
  50                 case 0x04:
  51                         d_dma->write_signal(mask_id[data & 3], 0x000f, 0xffff); // 1MB
  52                         break;
  53                 case 0x0c:
  54                         d_dma->write_signal(mask_id[data & 3], 0x00ff, 0xffff); // 16MB
  55                         break;
  56                 }
  57                 break;
  58 #endif
  59 #if defined(SUPPORT_32BIT_ADDRESS)
  60         case 0x0e05:
  61         case 0x0e07:
  62         case 0x0e09:
  63         case 0x0e0b:
  64                 d_dma->write_signal(bank_hi_id[((addr - 0xe05) >> 1) & 3], (data & 0xff) << 8, 0xff00);
  65                 break;
  66 #endif
  67         }
  68 }
  69
  70 uint32_t DMAREG::read_io8(uint32_t addr)
  71 {
  72         switch(addr) {
  73         case 0x0021:
  74         case 0x0023:
  75         case 0x0025:
  76         case 0x0027:
  77                 return d_dma->read_signal(bank_lo_id[((addr - 0x0021) >> 1) & 3]);
  78         }
  79         return 0xff;
  80 }
  81
  82 /*
  83 #define STATE_VERSION   1
  84
  85 bool DMAREG::process_state(FILEIO* state_fio, bool loading)
  86 {
  87         if(!state_fio->StateCheckUint32(STATE_VERSION)) {
  88                 return false;
  89         }
  90         if(!state_fio->StateCheckInt32(this_device_id)) {
  91                 return false;
  92         }
  93         return true;
  94 }
  95
  96 */