2 NEC-HE PC Engine Emulator 'ePCEngine'
3 SHARP X1twin Emulator 'eX1twin'
5 Origin : Ootake (joypad/cdrom)
7 : MESS (vdc/vce/vpc/cdrom)
8 Author : Takeda.Toshiya
18 #include "../../emu.h"
19 #include "../device.h"
22 #define SIG_PCE_SCSI_IRQ 0
23 #define SIG_PCE_SCSI_DRQ 1
24 #define SIG_PCE_SCSI_BSY 2
25 #define SIG_PCE_CDDA_DONE 3
26 #define SIG_PCE_ADPCM_VCLK 4
29 #define VDC_WPF 684 /* width of a line in frame including blanking areas */
30 #define VDC_LPF 262 /* number of lines in a single frame */
32 #define ADPCM_CLOCK 9216000
35 #define USE_CPU_HUC6280
46 class PCE : public DEVICE
52 SCSI_HOST* d_scsi_host;
53 SCSI_CDROM* d_scsi_cdrom;
56 bool support_6btn_pad;
57 bool support_multi_tap;
58 #ifdef SUPPORT_SUPER_GFX
66 uint8_t cart[0x400000]; // max 4mb
67 #ifdef SUPPORT_SUPER_GFX
68 uint8_t ram[0x8000]; // ram 32kb
70 uint8_t ram[0x2000]; // ram 8kb
72 #ifdef SUPPORT_BACKUP_RAM
73 uint8_t backup[0x2000];
74 uint32_t backup_crc32;
83 int dvssr_write; /* Set when the DVSSR register has been written to */
84 int physical_width; /* Width of the display */
85 int physical_height; /* Height of the display */
86 uint16_t sprite_ram[64*4]; /* Sprite RAM */
87 int curline; /* the current scanline we're on */
88 int current_segment; /* current segment of display */
89 int current_segment_line; /* current line inside a segment of display */
90 int vblank_triggered; /* to indicate whether vblank has been triggered */
91 int raster_count; /* counter to compare RCR against */
92 int satb_countdown; /* scanlines to wait to trigger the SATB irq */
93 uint8_t vram[0x10000];
103 uint8_t vce_control; /* VCE control register */
104 pair_t vce_address; /* Current address in the palette */
105 pair_t vce_data[512]; /* Palette data */
106 int current_bitmap_line; /* The current line in the display we are on */
108 scrntype_t bmp[VDC_LPF][VDC_WPF];
109 scrntype_t palette[1024];
118 UINT8 prio_map[512]; /* Pre-calculated priority map */
119 pair_t priority; /* Priority settings registers */
120 pair_t window1; /* Window 1 setting */
121 pair_t window2; /* Window 2 setting */
122 UINT8 vdc_select; /* Which VDC do the ST0, ST1, and ST2 instructions write to */
125 void pce_interrupt();
126 #ifdef SUPPORT_SUPER_GFX
127 void sgx_interrupt();
130 void vdc_advance_line(int which);
131 void draw_black_line(int line);
132 void draw_overscan_line(int line);
133 #ifdef SUPPORT_SUPER_GFX
134 void draw_sgx_overscan_line(int line);
136 void vram_write(int which, uint32_t offset, uint8_t data);
137 uint8_t vram_read(int which, uint32_t offset);
138 void vdc_w(int which, uint16_t offset, uint8_t data);
139 uint8_t vdc_r(int which, uint16_t offset);
140 void vce_w(uint16_t offset, uint8_t data);
141 uint8_t vce_r(uint16_t offset);
142 void pce_refresh_line(int which, int line, int external_input, uint8_t *drawn, scrntype_t *line_buffer);
143 void conv_obj(int which, int i, int l, int hf, int vf, char *buf);
144 void pce_refresh_sprites(int which, int line, uint8_t *drawn, scrntype_t *line_buffer);
145 void vdc_do_dma(int which);
146 void vpc_update_prio_map();
147 void vpc_w(uint16_t offset, uint8_t data);
148 uint8_t vpc_r(uint16_t offset);
149 #ifdef SUPPORT_SUPER_GFX
150 void sgx_vdc_w(uint16_t offset, uint8_t data);
151 uint8_t sgx_vdc_r(uint16_t offset);
167 uint8_t psg_ch, psg_vol, psg_lfo_freq, psg_lfo_ctrl;
169 int volume_l, volume_r;
171 void psg_write(uint16_t addr, uint8_t data);
172 uint8_t psg_read(uint16_t addr);
175 const uint32_t *joy_stat;
177 bool joy_high_nibble, joy_second_byte;
180 void joy_write(uint16_t addr, uint8_t data);
181 uint8_t joy_read(uint16_t addr);
182 uint8_t joy_2btn_pad_r(uint8_t index);
183 uint8_t joy_6btn_pad_r(uint8_t index);
187 uint8_t cdrom_ram[0x40000];
188 uint8_t cdrom_regs[16];
190 bool irq_status, drq_status;
192 void cdrom_initialize();
194 void cdrom_write(uint16_t addr, uint8_t data);
195 uint8_t cdrom_read(uint16_t addr);
196 void write_cdrom_data(uint8_t data);
197 uint8_t read_cdrom_data();
200 void set_cdrom_irq_line(int num, int state);
202 uint8_t adpcm_ram[0x10000];
203 int adpcm_read_ptr, adpcm_write_ptr, adpcm_written;
204 int adpcm_length, adpcm_clock_divider;
205 uint8_t adpcm_read_buf, adpcm_write_buf;
206 bool adpcm_dma_enabled;
207 int msm_start_addr, msm_end_addr, msm_half_addr;
208 uint8_t msm_nibble, msm_idle;
211 void write_adpcm_ram(uint8_t data);
212 uint8_t read_adpcm_ram();
217 double cdda_volume, adpcm_volume;
218 int event_cdda_fader, event_adpcm_fader;
220 void cdda_fade_in(int time);
221 void cdda_fade_out(int time);
222 void adpcm_fade_in(int time);
223 void adpcm_fade_out(int time);
227 PCE(VM_TEMPLATE* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
229 volume_l = volume_r = 1024;
230 set_device_name(_T("PC-Engine Core"));
238 void event_vline(int v, int clock);
239 void write_data8(uint32_t addr, uint32_t data);
240 uint32_t read_data8(uint32_t addr);
241 void write_io8(uint32_t addr, uint32_t data);
242 uint32_t read_io8(uint32_t addr);
244 void write_signal(int id, uint32_t data, uint32_t mask);
245 void event_callback(int event_id, int err);
247 void mix(int32_t* buffer, int cnt);
248 void set_volume(int ch, int decibel_l, int decibel_r);
249 bool process_state(FILEIO* state_fio, bool loading);
252 void set_context_cpu(HUC6280* device)
257 void set_context_adpcm(MSM5205* device)
261 void set_context_scsi_host(SCSI_HOST* device)
263 d_scsi_host = device;
265 void set_context_scsi_cdrom(SCSI_CDROM* device)
267 d_scsi_cdrom = device;
270 void initialize_sound(int rate)
274 void open_cart(const _TCHAR* file_path);
276 bool is_cart_inserted()