2 SANYO PHC-20 Emulator 'ePHC-20'
4 Author : Takeda.Toshiya
11 #include "../datarec.h"
13 static const uint8_t key_map[9][8] = {
14 {0x31, 0x57, 0x53, 0x58, 0x00, 0x28, 0xba, 0xbd}, // 1 W S X DOWN : -
15 {0x1b, 0x51, 0x41, 0x5a, 0x00, 0x0d, 0xbb, 0xbf}, // ESC??? Q A Z RET ; /
16 {0x33, 0x52, 0x46, 0x56, 0x00, 0x27, 0xdb, 0x00}, // 3 R F V RIGHT [
17 {0x32, 0x45, 0x44, 0x43, 0x00, 0x26, 0xdd, 0x20}, // 2 E D C UP ] SPACE
18 {0x35, 0x59, 0x48, 0x4e, 0x00, 0x30, 0x50, 0x00}, // 5 Y H N 0 P
19 {0x34, 0x54, 0x47, 0x42, 0x00, 0x25, 0xc0, 0x00}, // 4 T G B LEFT @
20 {0x36, 0x55, 0x4a, 0x4d, 0x00, 0x39, 0x4f, 0x00}, // 6 U J M 9 O
21 {0x37, 0x49, 0x4b, 0xbc, 0x00, 0x38, 0x4c, 0xbe}, // 7 I K , 8 L .
22 {0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, // ??? SHIFT
25 #define SET_BANK(s, e, w, r) { \
26 int sb = (s) >> 10, eb = (e) >> 10; \
27 for(int i = sb; i <= eb; i++) { \
31 wbank[i] = (w) + 0x400 * (i - sb); \
36 rbank[i] = (r) + 0x400 * (i - sb); \
41 void PHC20_MEMORY::initialize()
43 memset(rom, 0xff, sizeof(rom));
44 memset(rdmy, 0xff, sizeof(rdmy));
47 FILEIO* fio = new FILEIO();
48 if(fio->Fopen(create_local_path(_T("BASIC.ROM")), FILEIO_READ_BINARY)) {
49 fio->Fread(rom, sizeof(rom), 1);
55 SET_BANK(0x0000, 0x1fff, wdmy, rom );
56 SET_BANK(0x2000, 0x2fff, ram, ram );
57 SET_BANK(0x3000, 0x3fff, wdmy, rdmy);
58 SET_BANK(0x4000, 0x43ff, vram, vram);
59 SET_BANK(0x4400, 0xffff, wdmy, rdmy);
61 key_stat = emu->get_key_buffer();
63 // register event to update the key status
64 register_frame_event(this);
67 void PHC20_MEMORY::reset()
69 memset(ram, 0, sizeof(ram));
70 memset(vram, 0, sizeof(vram));
72 memset(status, 0, sizeof(status));
76 void PHC20_MEMORY::write_data8(uint32_t addr, uint32_t data)
79 if((0x3000 <= addr && addr < 0x4000) || 0x4400 <= addr) {
85 d_drec->write_signal(SIG_DATAREC_MIC, 1, 1);
86 } else if(data == 0x0a) {
88 d_drec->write_signal(SIG_DATAREC_MIC, 0, 1);
92 this->out_debug_log(_T("%6x\tWM8\t%4x,%2x\n"), get_cpu_pc(0), addr, data);
98 this->out_debug_log(_T("%6x\tWM8\t%4x,%2x\n"), get_cpu_pc(0), addr, data);
104 wbank[addr >> 10][addr & 0x3ff] = data;
107 uint32_t PHC20_MEMORY::read_data8(uint32_t addr)
110 if((0x3000 <= addr && addr < 0x4000) || 0x4400 <= addr) {
122 // note: bit0 of 3808h ... break cload ???
123 return ~status[addr & 0x0f];
126 // bit1: vsync or hsync ???
130 this->out_debug_log(_T("%6x\tRM8\t%4x\n"), get_cpu_pc(0), addr);
134 return rbank[addr >> 10][addr & 0x3ff];
137 void PHC20_MEMORY::event_frame()
139 memset(status, 0, sizeof(status));
141 for(int i = 0; i < 9; i++) {
143 for(int j = 0; j < 8; j++) {
144 val |= key_stat[key_map[i][j]] ? (1 << j) : 0;
150 void PHC20_MEMORY::write_signal(int id, uint32_t data, uint32_t mask)
159 #define STATE_VERSION 1
161 bool PHC20_MEMORY::process_state(FILEIO* state_fio, bool loading)
163 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
166 if(!state_fio->StateCheckInt32(this_device_id)) {
169 state_fio->StateBuffer(ram, sizeof(ram), 1);
170 state_fio->StateBuffer(vram, sizeof(vram), 1);
171 state_fio->StateBuffer(status, sizeof(status), 1);
172 state_fio->StateUint8(sysport);