2 EPSON QC-10 Emulator 'eQC-10'
4 Author : Takeda.Toshiya
12 #include "../pcm1bit.h"
13 #include "../upd765a.h"
17 #define SET_BANK(s, e, w, r) { \
18 int sb = (s) >> 11, eb = (e) >> 11; \
19 for(int i = sb; i <= eb; i++) { \
20 wbank[i] = (w) + 0x800 * (i - sb); \
21 rbank[i] = (r) + 0x800 * (i - sb); \
25 void MEMORY::initialize()
28 memset(ram, 0, sizeof(ram));
29 memset(cmos, 0, sizeof(cmos));
30 memset(ipl, 0xff, sizeof(ipl));
31 memset(rdmy, 0xff, sizeof(rdmy));
34 FILEIO* fio = new FILEIO();
35 if(fio->Fopen(create_local_path(_T("IPL.ROM")), FILEIO_READ_BINARY)) {
36 fio->Fread(ipl, sizeof(ipl), 1);
39 if(fio->Fopen(create_local_path(_T("CMOS.BIN")), FILEIO_READ_BINARY)) {
40 fio->Fread(cmos, sizeof(cmos), 1);
45 cmos_crc32 = get_crc32(cmos, sizeof(cmos));
48 void MEMORY::release()
50 if(cmos_crc32 != get_crc32(cmos, sizeof(cmos))) {
51 FILEIO* fio = new FILEIO();
52 if(fio->Fopen(create_local_path(_T("CMOS.BIN")), FILEIO_WRITE_BINARY)) {
53 fio->Fwrite(cmos, sizeof(cmos), 1);
68 pcm_on = pcm_cont = pcm_pit = false;
70 // init fdc/fdd status
71 fdc_irq = motor = false;
74 void MEMORY::write_data8(uint32_t addr, uint32_t data)
77 wbank[addr >> 11][addr & 0x7ff] = data;
80 uint32_t MEMORY::read_data8(uint32_t addr)
83 return rbank[addr >> 11][addr & 0x7ff];
86 void MEMORY::write_io8(uint32_t addr, uint32_t data)
89 case 0x18: case 0x19: case 0x1a: case 0x1b:
92 d_pit->write_signal(SIG_I8253_GATE_0, data, 1);
93 d_pit->write_signal(SIG_I8253_GATE_2, data, 2);
95 pcm_cont = ((data & 4) != 0);
98 case 0x1c: case 0x1d: case 0x1e: case 0x1f:
101 case 0x20: case 0x21: case 0x22: case 0x23:
108 uint32_t MEMORY::read_io8(uint32_t addr)
110 switch(addr & 0xff) {
111 case 0x18: case 0x19: case 0x1a: case 0x1b:
112 return ~config.dipswitch & 0xff;
113 case 0x30: case 0x31: case 0x32: case 0x33:
114 return (bank & 0xf0) | (d_fdc->is_disk_inserted() ? 8 : 0) | (motor ? 0 : 2) | (fdc_irq ? 1 : 0);
120 0000-DFFF : RAM * 4banks
127 void MEMORY::write_signal(int id, uint32_t data, uint32_t mask)
129 if(id == SIG_MEMORY_PCM) {
131 pcm_pit = ((data & mask) != 0);
133 } else if(id == SIG_MEMORY_FDC_IRQ) {
134 fdc_irq = ((data & mask) != 0);
135 } else if(id == SIG_MEMORY_MOTOR) {
136 motor = ((data & mask) != 0);
140 void MEMORY::update_map()
143 SET_BANK(0x0000, 0x1fff, wdmy, ipl);
144 SET_BANK(0x2000, 0xdfff, wdmy, rdmy);
145 } else if(csel & 1) {
147 SET_BANK(0x0000, 0x7fff, ram + 0x00000, ram + 0x00000);
148 } else if(bank & 0x20) {
149 SET_BANK(0x0000, 0x7fff, ram + 0x10000, ram + 0x10000);
150 } else if(bank & 0x40) {
151 SET_BANK(0x0000, 0x7fff, ram + 0x20000, ram + 0x20000);
152 } else if(bank & 0x80) {
153 SET_BANK(0x0000, 0x7fff, ram + 0x30000, ram + 0x30000);
155 SET_BANK(0x0000, 0x7fff, wdmy, rdmy);
157 SET_BANK(0x8000, 0x87ff, cmos, cmos);
160 SET_BANK(0x0000, 0xdfff, ram + 0x00000, ram + 0x00000);
161 } else if(bank & 0x20) {
162 SET_BANK(0x0000, 0xdfff, ram + 0x10000, ram + 0x10000);
163 } else if(bank & 0x40) {
164 SET_BANK(0x0000, 0xdfff, ram + 0x20000, ram + 0x20000);
165 } else if(bank & 0x80) {
166 SET_BANK(0x0000, 0xdfff, ram + 0x30000, ram + 0x30000);
168 SET_BANK(0x0000, 0xdfff, wdmy, rdmy);
171 SET_BANK(0xe000, 0xffff, ram + 0xe000, ram + 0xe000);
174 void MEMORY::update_pcm()
176 if(!pcm_on && (pcm_cont || pcm_pit)) {
177 d_pcm->write_signal(SIG_PCM1BIT_ON, 1, 1);
179 } else if(pcm_on && !(pcm_cont || pcm_pit)) {
180 d_pcm->write_signal(SIG_PCM1BIT_ON, 0, 1);
185 #define STATE_VERSION 1
187 bool MEMORY::process_state(FILEIO* state_fio, bool loading)
189 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
192 if(!state_fio->StateCheckInt32(this_device_id)) {
195 state_fio->StateBuffer(ram, sizeof(ram), 1);
196 state_fio->StateBuffer(cmos, sizeof(cmos), 1);
197 state_fio->StateUint32(cmos_crc32);
198 state_fio->StateUint8(bank);
199 state_fio->StateUint8(psel);
200 state_fio->StateUint8(csel);
201 state_fio->StateBool(pcm_on);
202 state_fio->StateBool(pcm_cont);
203 state_fio->StateBool(pcm_pit);
204 state_fio->StateBool(fdc_irq);
205 state_fio->StateBool(motor);