2 EPSON QC-10 Emulator 'eQC-10'
4 Author : Takeda.Toshiya
12 #include "../pcm1bit.h"
13 #include "../upd765a.h"
15 #define SET_BANK(s, e, w, r) { \
16 int sb = (s) >> 11, eb = (e) >> 11; \
17 for(int i = sb; i <= eb; i++) { \
18 wbank[i] = (w) + 0x800 * (i - sb); \
19 rbank[i] = (r) + 0x800 * (i - sb); \
23 void MEMORY::initialize()
26 memset(ram, 0, sizeof(ram));
27 memset(cmos, 0, sizeof(cmos));
28 memset(ipl, 0xff, sizeof(ipl));
29 memset(rdmy, 0xff, sizeof(rdmy));
32 FILEIO* fio = new FILEIO();
33 if(fio->Fopen(create_local_path(_T("IPL.ROM")), FILEIO_READ_BINARY)) {
34 fio->Fread(ipl, sizeof(ipl), 1);
37 if(fio->Fopen(create_local_path(_T("CMOS.BIN")), FILEIO_READ_BINARY)) {
38 fio->Fread(cmos, sizeof(cmos), 1);
43 cmos_crc32 = get_crc32(cmos, sizeof(cmos));
46 void MEMORY::release()
48 if(cmos_crc32 != get_crc32(cmos, sizeof(cmos))) {
49 FILEIO* fio = new FILEIO();
50 if(fio->Fopen(create_local_path(_T("CMOS.BIN")), FILEIO_WRITE_BINARY)) {
51 fio->Fwrite(cmos, sizeof(cmos), 1);
66 pcm_on = pcm_cont = pcm_pit = false;
68 // init fdc/fdd status
69 fdc_irq = motor = false;
72 void MEMORY::write_data8(uint32_t addr, uint32_t data)
75 wbank[addr >> 11][addr & 0x7ff] = data;
78 uint32_t MEMORY::read_data8(uint32_t addr)
81 return rbank[addr >> 11][addr & 0x7ff];
84 void MEMORY::write_io8(uint32_t addr, uint32_t data)
87 case 0x18: case 0x19: case 0x1a: case 0x1b:
90 d_pit->write_signal(SIG_I8253_GATE_0, data, 1);
91 d_pit->write_signal(SIG_I8253_GATE_2, data, 2);
93 pcm_cont = ((data & 4) != 0);
96 case 0x1c: case 0x1d: case 0x1e: case 0x1f:
99 case 0x20: case 0x21: case 0x22: case 0x23:
106 uint32_t MEMORY::read_io8(uint32_t addr)
108 switch(addr & 0xff) {
109 case 0x18: case 0x19: case 0x1a: case 0x1b:
110 return ~config.dipswitch & 0xff;
111 case 0x30: case 0x31: case 0x32: case 0x33:
112 return (bank & 0xf0) | (d_fdc->is_disk_inserted() ? 8 : 0) | (motor ? 0 : 2) | (fdc_irq ? 1 : 0);
118 0000-DFFF : RAM * 4banks
125 void MEMORY::write_signal(int id, uint32_t data, uint32_t mask)
127 if(id == SIG_MEMORY_PCM) {
129 pcm_pit = ((data & mask) != 0);
131 } else if(id == SIG_MEMORY_FDC_IRQ) {
132 fdc_irq = ((data & mask) != 0);
133 } else if(id == SIG_MEMORY_MOTOR) {
134 motor = ((data & mask) != 0);
138 void MEMORY::update_map()
141 SET_BANK(0x0000, 0x1fff, wdmy, ipl);
142 SET_BANK(0x2000, 0xdfff, wdmy, rdmy);
143 } else if(csel & 1) {
145 SET_BANK(0x0000, 0x7fff, ram + 0x00000, ram + 0x00000);
146 } else if(bank & 0x20) {
147 SET_BANK(0x0000, 0x7fff, ram + 0x10000, ram + 0x10000);
148 } else if(bank & 0x40) {
149 SET_BANK(0x0000, 0x7fff, ram + 0x20000, ram + 0x20000);
150 } else if(bank & 0x80) {
151 SET_BANK(0x0000, 0x7fff, ram + 0x30000, ram + 0x30000);
153 SET_BANK(0x0000, 0x7fff, wdmy, rdmy);
155 SET_BANK(0x8000, 0x87ff, cmos, cmos);
158 SET_BANK(0x0000, 0xdfff, ram + 0x00000, ram + 0x00000);
159 } else if(bank & 0x20) {
160 SET_BANK(0x0000, 0xdfff, ram + 0x10000, ram + 0x10000);
161 } else if(bank & 0x40) {
162 SET_BANK(0x0000, 0xdfff, ram + 0x20000, ram + 0x20000);
163 } else if(bank & 0x80) {
164 SET_BANK(0x0000, 0xdfff, ram + 0x30000, ram + 0x30000);
166 SET_BANK(0x0000, 0xdfff, wdmy, rdmy);
169 SET_BANK(0xe000, 0xffff, ram + 0xe000, ram + 0xe000);
172 void MEMORY::update_pcm()
174 if(!pcm_on && (pcm_cont || pcm_pit)) {
175 d_pcm->write_signal(SIG_PCM1BIT_ON, 1, 1);
177 } else if(pcm_on && !(pcm_cont || pcm_pit)) {
178 d_pcm->write_signal(SIG_PCM1BIT_ON, 0, 1);
183 #define STATE_VERSION 1
185 #include "../../statesub.h"
187 void MEMORY::decl_state()
189 enter_decl_state(STATE_VERSION);
191 DECL_STATE_ENTRY_1D_ARRAY(ram, sizeof(ram));
192 DECL_STATE_ENTRY_1D_ARRAY(cmos, sizeof(cmos));
193 DECL_STATE_ENTRY_UINT32(cmos_crc32);
194 DECL_STATE_ENTRY_UINT8(bank);
195 DECL_STATE_ENTRY_UINT8(psel);
196 DECL_STATE_ENTRY_UINT8(csel);
197 DECL_STATE_ENTRY_BOOL(pcm_on);
198 DECL_STATE_ENTRY_BOOL(pcm_cont);
199 DECL_STATE_ENTRY_BOOL(pcm_pit);
200 DECL_STATE_ENTRY_BOOL(fdc_irq);
201 DECL_STATE_ENTRY_BOOL(motor);
206 void MEMORY::save_state(FILEIO* state_fio)
208 if(state_entry != NULL) {
209 state_entry->save_state(state_fio);
211 // state_fio->FputUint32(STATE_VERSION);
212 // state_fio->FputInt32(this_device_id);
214 // state_fio->Fwrite(ram, sizeof(ram), 1);
215 // state_fio->Fwrite(cmos, sizeof(cmos), 1);
216 // state_fio->FputUint32(cmos_crc32);
217 // state_fio->FputUint8(bank);
218 // state_fio->FputUint8(psel);
219 // state_fio->FputUint8(csel);
220 // state_fio->FputBool(pcm_on);
221 // state_fio->FputBool(pcm_cont);
222 // state_fio->FputBool(pcm_pit);
223 // state_fio->FputBool(fdc_irq);
224 // state_fio->FputBool(motor);
227 bool MEMORY::load_state(FILEIO* state_fio)
230 if(state_entry != NULL) {
231 mb = state_entry->load_state(state_fio);
236 // if(state_fio->FgetUint32() != STATE_VERSION) {
239 // if(state_fio->FgetInt32() != this_device_id) {
242 // state_fio->Fread(ram, sizeof(ram), 1);
243 // state_fio->Fread(cmos, sizeof(cmos), 1);
244 // cmos_crc32 = state_fio->FgetUint32();
245 // bank = state_fio->FgetUint8();
246 // psel = state_fio->FgetUint8();
247 // csel = state_fio->FgetUint8();
248 // pcm_on = state_fio->FgetBool();
249 // pcm_cont = state_fio->FgetBool();
250 // pcm_pit = state_fio->FgetBool();
251 // fdc_irq = state_fio->FgetBool();
252 // motor = state_fio->FgetBool();
259 bool MEMORY::process_state(FILEIO* state_fio, bool loading)
261 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
264 if(!state_fio->StateCheckInt32(this_device_id)) {
267 state_fio->StateBuffer(ram, sizeof(ram), 1);
268 state_fio->StateBuffer(cmos, sizeof(cmos), 1);
269 state_fio->StateUint32(cmos_crc32);
270 state_fio->StateUint8(bank);
271 state_fio->StateUint8(psel);
272 state_fio->StateUint8(csel);
273 state_fio->StateBool(pcm_on);
274 state_fio->StateBool(pcm_cont);
275 state_fio->StateBool(pcm_pit);
276 state_fio->StateBool(fdc_irq);
277 state_fio->StateBool(motor);