source/src/vm/x1/sasi.cpp

   1 /*
   2         SHARP X1 Emulator 'eX1'
   3         SHARP X1twin Emulator 'eX1twin'
   4         SHARP X1turbo Emulator 'eX1turbo'
   5         SHARP X1turboZ Emulator 'eX1turboZ'
   6
   7         Author : Takeda.Toshiya
   8         Date   : 2018.05.15-
   9
  10         [ SASI I/F ]
  11 */
  12
  13 #include "sasi.h"
  14 #ifdef _X1TURBO_FEATURE
  15 #include "../z80dma.h"
  16 #endif
  17
  18 #define STATUS_INT      0x00    // unknown
  19 #define STATUS_REQ      0x01
  20 #define STATUS_BSY      0x02
  21 #define STATUS_IXO      0x04
  22 #define STATUS_CXD      0x08
  23 #define STATUS_MSG      0x10
  24
  25 namespace X1 {
  26
  27 void SASI::reset()
  28 {
  29         irq_status = drq_status = false;
  30 }
  31
  32 void SASI::write_io8(uint32_t addr, uint32_t data)
  33 {
  34         switch(addr) {
  35         case 0xfd0:
  36                 #ifdef _SCSI_DEBUG_LOG
  37                         this->out_debug_log(_T("[SASI] out %04X %02X\n"), addr, data);
  38                 #endif
  39                 d_host->write_dma_io8(addr, data);
  40                 break;
  41         case 0xfd1:
  42                 #ifdef _SCSI_DEBUG_LOG
  43                         this->out_debug_log(_T("[SASI] out %04X %02X\n"), addr, data);
  44                 #endif
  45                 d_host->write_signal(SIG_SCSI_SEL, 0, 1);
  46                 break;
  47         case 0xfd2:
  48                 #ifdef _SCSI_DEBUG_LOG
  49                         this->out_debug_log(_T("[SASI] out %04X %02X\n"), addr, data);
  50                 #endif
  51                 d_host->write_signal(SIG_SCSI_RST, 0, 1);
  52                 d_host->write_signal(SIG_SCSI_RST, 1, 1);
  53                 d_host->write_signal(SIG_SCSI_RST, 0, 1);
  54                 break;
  55         case 0xfd3:
  56                 #ifdef _SCSI_DEBUG_LOG
  57                         this->out_debug_log(_T("[SASI] out %04X %02X\n"), addr, data);
  58                 #endif
  59                 d_host->write_dma_io8(addr, data);
  60                 d_host->write_signal(SIG_SCSI_SEL, 1, 1);
  61                 break;
  62         }
  63 }
  64
  65 uint32_t SASI::read_io8(uint32_t addr)
  66 {
  67         uint32_t val = 0;
  68
  69         switch(addr) {
  70         case 0xfd0:
  71                 val = d_host->read_dma_io8(addr);
  72                 #ifdef _SCSI_DEBUG_LOG
  73                         this->out_debug_log(_T("[SASI] in  %04X %02X\n"), addr, val);
  74                 #endif
  75                 return val;
  76         case 0xfd1:
  77                 val = (d_host->read_signal(SIG_SCSI_REQ) ? STATUS_REQ : 0) |
  78 //                    (d_host->read_signal(SIG_SCSI_ACK) ? STATUS_ACK : 0) |
  79                       (d_host->read_signal(SIG_SCSI_BSY) ? STATUS_BSY : 0) |
  80                       (d_host->read_signal(SIG_SCSI_MSG) ? STATUS_MSG : 0) |
  81                       (d_host->read_signal(SIG_SCSI_CD ) ? STATUS_CXD : 0) |
  82                       (d_host->read_signal(SIG_SCSI_IO ) ? STATUS_IXO : 0) |
  83                       (irq_status                        ? STATUS_INT : 0);
  84                 irq_status = false;
  85                 #ifdef _SCSI_DEBUG_LOG
  86                         this->out_debug_log(_T("[SASI] in  %04X %02X (REQ=%d,BSY=%d,MSG=%d,CxD=%d,IxO=%d)\n"), addr, val,
  87                                 (val & STATUS_REQ) ? 1 : 0,
  88                                 (val & STATUS_BSY) ? 1 : 0,
  89                                 (val & STATUS_MSG) ? 1 : 0,
  90                                 (val & STATUS_CXD) ? 1 : 0,
  91                                 (val & STATUS_IXO) ? 1 : 0);
  92                 #endif
  93                 return val;
  94         }
  95         return 0xff;
  96 }
  97
  98 void SASI::write_dma_io8(uint32_t addr, uint32_t data)
  99 {
 100         write_io8(0xfd0, data);
 101 }
 102
 103 uint32_t SASI::read_dma_io8(uint32_t addr)
 104 {
 105         return read_io8(0xfd0);
 106 }
 107
 108 void SASI::write_signal(int id, uint32_t data, uint32_t mask)
 109 {
 110         switch(id) {
 111         case SIG_SASI_IRQ:
 112 #ifdef _X1TURBO_FEATURE
 113                 d_dma->write_signal(SIG_Z80DMA_READY, data, mask);
 114 #endif
 115                 irq_status = ((data & mask) != 0);
 116                 break;
 117         case SIG_SASI_DRQ:
 118 #ifdef _X1TURBO_FEATURE
 119                 d_dma->write_signal(SIG_Z80DMA_READY, data, mask);
 120 #endif
 121                 drq_status = ((data & mask) != 0);
 122                 break;
 123         }
 124 }
 125
 126 #define STATE_VERSION   1
 127
 128 bool SASI::process_state(FILEIO* state_fio, bool loading)
 129 {
 130         if(!state_fio->StateCheckUint32(STATE_VERSION)) {
 131                 return false;
 132         }
 133         if(!state_fio->StateCheckInt32(this_device_id)) {
 134                 return false;
 135         }
 136         state_fio->StateBool(irq_status);
 137         state_fio->StateBool(drq_status);
 138         return true;
 139 }
 140
 141 }