d_vram->write_memory_mapped_io32(x_addr + addr, tmp_r1.d);
}
+uint32_t PLANEVRAM::read_dma_data8w(uint32_t addr, int* wait)
+{
+ uint32_t val = read_memory_mapped_io8(addr); // OK?
+ __LIKELY_IF(wait != NULL) {
+ *wait = 0; // Discard WAIT VALUE(s) for DMA transfer.
+ }
+ return val;
+}
+
+void PLANEVRAM::write_dma_data8w(uint32_t addr, uint32_t data, int* wait)
+{
+ write_memory_mapped_io8(addr, data); // OK?
+ __LIKELY_IF(wait != NULL) {
+ *wait = 0; // Discard WAIT VALUE(s) for DMA transfer.
+ }
+}
+
#define STATE_VERSION 2
bool PLANEVRAM::process_state(FILEIO* state_fio, bool loading)
DEVICE* d_crtc;
DEVICE* d_sprite;
TOWNS_VRAM* d_vram;
-
+
uint8_t mix_reg; // MMIO 000CH:FF80H
uint8_t r50_readplane; // MMIO 000CH:FF81H : BIT 7 and 6.
uint8_t r50_ramsel; // MMIO 000CH:FF81H : BIT 3 to 0.
d_vram = NULL;
}
- void initialize();
- void reset();
-
- virtual uint32_t __FASTCALL read_memory_mapped_io8(uint32_t addr);
- virtual void __FASTCALL write_memory_mapped_io8(uint32_t addr, uint32_t data);
+ void initialize() override;
+ void reset() override;
+
+ virtual uint32_t __FASTCALL read_memory_mapped_io8(uint32_t addr) override;
+ virtual void __FASTCALL write_memory_mapped_io8(uint32_t addr, uint32_t data) override;
+ virtual uint32_t __FASTCALL read_dma_data8w(uint32_t addr, int* wait) override;
+ virtual void __FASTCALL write_dma_data8w(uint32_t addr, uint32_t data, int* wait) override;
+
+ virtual uint32_t __FASTCALL read_io8(uint32_t addr) override;
+ virtual void __FASTCALL write_io8(uint32_t addr, uint32_t data) override;
- virtual uint32_t __FASTCALL read_io8(uint32_t addr);
- virtual void __FASTCALL write_io8(uint32_t addr, uint32_t data);
-
- virtual bool process_state(FILEIO* state_fio, bool loading);
+ virtual bool process_state(FILEIO* state_fio, bool loading) override;
// unique functions
void set_context_crtc(DEVICE* dev)