[VM][FM7][SOUND] Separate reset sequence for OPN/WHG/THG/PSG to a common function.
[VM][FM7] Replace printf debug messages to out_debug_log().
{
if(id == SIG_AY_3_891X_MUTE) {
mute = ((data & mask) != 0);
-
} else if(id == SIG_AY_3_891X_PORT_A) {
if(_SUPPORT_AY_3_891X_PORT_A) {
port[0].rreg = (port[0].rreg & ~mask) | (data & mask);
#endif
case SIG_DISPLAY_EXTRA_MODE: // FD04 bit 4, 3
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
- //printf("Wrote $FD04: %02x\n", data);
+ //out_debug_log("Wrote $FD04: %02x\n", data);
{
int oldmode = display_mode;
int mode;
case SIG_DISPLAY_MODE320: // FD12 bit 6
# if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
{
- //printf("Wrote $FD12: %02x\n", data);
+ //out_debug_log("Wrote $FD12: %02x\n", data);
int oldmode = display_mode;
mode320 = flag;
if(mode400line) {
}
#if !defined(_FM77AV_VARIANTS) || defined(_FM8)
# if defined(USE_AY_3_8910_AS_PSG)
+ psg->set_reg(0x27, 0); // set prescaler
psg->set_reg(0x2e, 0); // set prescaler
psg->write_signal(SIG_AY_3_891X_MUTE, 0x00, 0x01); // Okay?
# else
opn[2]->initialize_sound(rate, (int)(4.9152 * 1000.0 * 1000.0 / 4.0), samples, 0, 0);
# if !defined(_FM77AV_VARIANTS)
psg->initialize_sound(rate, (int)(4.9152 * 1000.0 * 1000.0 / 4.0), samples, 0, 0);
+# if defined(USE_AY_3_8910_AS_PSG)
psg->set_low_pass_filter_freq(4500);
psg->set_high_pass_filter_freq(50);
+# endif
# endif
# if defined(_FM77AV_VARIANTS)
keyboard_beep->initialize_sound(rate, 2400.0, 512);
void FM7_MAINIO::set_irq_keyboard(bool flag)
{
//uint8_t backup = irqstat_reg0;
- //printf("MAIN: KEYBOARD: IRQ=%d MASK=%d\n", flag ,irqmask_keyboard);
+ //out_debug_log("MAIN: KEYBOARD: IRQ=%d MASK=%d\n", flag ,irqmask_keyboard);
irqreq_keyboard = flag;
if(flag && !irqmask_keyboard) {
irqstat_reg0 &= 0xfe;
#endif
if(firq_sub_attention) {
set_sub_attention(false);
- //printf("Attention \n");
+ //out_debug_log("Attention \n");
}
#if defined(_FM77AV_VARIANTS)
if(hotreset) {
defined(_FM77AV20) || defined(_FM77AV20EX) || defined(_FM77AV20SX)
if(!stat_kanjirom) return 0xff;
#endif
- //printf("KANJI MAIN CLASS1 ADDR: %05x\n", kaddress.w.l);
+ //out_debug_log("KANJI MAIN CLASS1 ADDR: %05x\n", kaddress.w.l);
if(kanjiclass1) {
return kanjiclass1->read_data8(KANJIROM_DATA_HI);
} else {
return mainmem->read_data8(addr - 0x80 + FM7_MAINIO_MMR_BANK + mmr_segment * 16);
}
#endif
- // if((addr >= 0x0006) && !(addr == 0x1f) && !(addr == 0x0b)) printf("MAINIO: READ: %08x \n", addr);
+ // if((addr >= 0x0006) && !(addr == 0x1f) && !(addr == 0x0b)) out_debug_log("MAINIO: READ: %08x \n", addr);
switch(addr) {
case 0x00: // FD00
retval = (uint32_t) get_port_fd00();
#endif
case 0x0e: // PSG DATA
retval = (uint32_t) get_psg();
- //printf("PSG DATA READ val=%02x\n", retval);
+ //out_debug_log("PSG DATA READ reg=%d val=%02x\n", opn_address[3], retval);
break;
case 0x0f: // FD0F
read_fd0f();
retval = subsystem_read_status();
break;
#endif
- //printf("OPN CMD READ \n");
+ //out_debug_log("OPN CMD READ \n");
break;
case 0x16: // OPN DATA
retval = (uint32_t) get_opn(0);
retval = (uint32_t) get_fdc_stat();
}
break;
- //printf("FDC: READ STATUS %02x PC=%04x\n", retval, maincpu->get_pc());
+ //out_debug_log("FDC: READ STATUS %02x PC=%04x\n", retval, maincpu->get_pc());
break;
case 0x19: // FDC: Track
if(stat_fdmode_2hd) {
} else {
retval = (uint32_t) get_fdc_track();
}
- //printf("FDC: READ TRACK REG %02x\n", retval);
+ //out_debug_log("FDC: READ TRACK REG %02x\n", retval);
break;
case 0x1a: // FDC: Sector
if(stat_fdmode_2hd) {
} else {
retval = (uint32_t) get_fdc_sector();
}
- //printf("FDC: READ SECTOR REG %02x\n", retval);
+ //out_debug_log("FDC: READ SECTOR REG %02x\n", retval);
break;
case 0x1b: // FDC: Data
if(stat_fdmode_2hd) {
} else {
retval = (uint32_t) get_fdc_fd1c();
}
- //printf("FDC: READ HEAD REG %02x\n", retval);
+ //out_debug_log("FDC: READ HEAD REG %02x\n", retval);
break;
case 0x1d:
if(stat_fdmode_2hd) {
} else {
retval = (uint32_t) get_fdc_motor();
}
- //printf("FDC: READ MOTOR REG %02x\n", retval);
+ //out_debug_log("FDC: READ MOTOR REG %02x\n", retval);
break;
case 0x1e:
if(stat_fdmode_2hd) {
} else {
retval = (uint32_t) get_fdc_fd1e();
}
- //printf("FDC: READ MOTOR REG %02x\n", retval);
+ //out_debug_log("FDC: READ MOTOR REG %02x\n", retval);
break;
case 0x1f:
if(stat_fdmode_2hd) {
case 0x18: // FDC: STATUS
retval = (uint32_t) get_fdc_stat();
break;
- //printf("FDC: READ STATUS %02x PC=%04x\n", retval, maincpu->get_pc());
+ //out_debug_log("FDC: READ STATUS %02x PC=%04x\n", retval, maincpu->get_pc());
break;
case 0x19: // FDC: Track
retval = (uint32_t) get_fdc_track();
- //printf("FDC: READ TRACK REG %02x\n", retval);
+ //out_debug_log("FDC: READ TRACK REG %02x\n", retval);
break;
case 0x1a: // FDC: Sector
retval = (uint32_t) get_fdc_sector();
- //printf("FDC: READ SECTOR REG %02x\n", retval);
+ //out_debug_log("FDC: READ SECTOR REG %02x\n", retval);
break;
case 0x1b: // FDC: Data
retval = (uint32_t) get_fdc_data();
break;
case 0x1c:
retval = (uint32_t) get_fdc_fd1c();
- //printf("FDC: READ HEAD REG %02x\n", retval);
+ //out_debug_log("FDC: READ HEAD REG %02x\n", retval);
break;
case 0x1d:
retval = (uint32_t) get_fdc_motor();
- //printf("FDC: READ MOTOR REG %02x\n", retval);
+ //out_debug_log("FDC: READ MOTOR REG %02x\n", retval);
break;
case 0x1e:
retval = (uint32_t) get_fdc_fd1e();
- //printf("FDC: READ MOTOR REG %02x\n", retval);
+ //out_debug_log("FDC: READ MOTOR REG %02x\n", retval);
break;
case 0x1f:
retval = (uint32_t) fdc_getdrqirq();
return retval;
}
#endif
- //if((addr >= 0x0006) && (addr != 0x1f)) printf("MAINIO: READ: %08x DATA=%08x\n", addr);
+ //if((addr >= 0x0006) && (addr != 0x1f)) out_debug_log("MAINIO: READ: %08x DATA=%08x\n", addr);
return 0xff;
}
#endif
break;
case 0x0d:
- //printf("PSG CMD WRITE val=%02x\n", data);
+ //out_debug_log("PSG CMD WRITE val=%02x\n", data);
set_psg_cmd(data);
break;
case 0x0e:
- //printf("PSG DATA WRITE val=%02x\n", data);
+ //out_debug_log("PSG DATA WRITE val=%02x\n", data);
set_psg(data);
break;
case 0x0f: // FD0F
break;
#endif
case 0x15: // OPN CMD
- //printf("OPN CMD WRITE val=%02x\n", data);
+ //out_debug_log("OPN CMD WRITE val=%02x\n", data);
set_opn_cmd(0, data);
break;
case 0x16: // OPN DATA
- //printf("OPN DATA WRITE val=%02x\n", data);
+ //out_debug_log("OPN DATA WRITE val=%02x\n", data);
set_opn(0, data);
break;
case 0x17:
} else {
set_fdc_cmd((uint8_t)data);
}
- //printf("FDC: WRITE CMD %02x\n", data);
+ //out_debug_log("FDC: WRITE CMD %02x\n", data);
break;
case 0x19: // FDC: Track
if(stat_fdmode_2hd) {
} else {
set_fdc_track((uint8_t)data);
}
- //printf("FDC: WRITE TRACK REG %02x\n", data);
+ //out_debug_log("FDC: WRITE TRACK REG %02x\n", data);
break;
case 0x1a: // FDC: Sector
if(stat_fdmode_2hd) {
} else {
set_fdc_sector((uint8_t)data);
}
- //printf("FDC: WRITE SECTOR REG %02x\n", data);
+ //out_debug_log("FDC: WRITE SECTOR REG %02x\n", data);
break;
case 0x1b: // FDC: Data
if(stat_fdmode_2hd) {
} else {
set_fdc_fd1c((uint8_t)data);
}
- //printf("FDC: WRITE HEAD REG %02x\n", data);
+ //out_debug_log("FDC: WRITE HEAD REG %02x\n", data);
break;
case 0x1d:
if(stat_fdmode_2hd) {
} else {
set_fdc_fd1d((uint8_t)data);
}
- //printf("FDC: WRITE MOTOR REG %02x\n", data);
+ //out_debug_log("FDC: WRITE MOTOR REG %02x\n", data);
break;
case 0x1e:
if(stat_fdmode_2hd) {
#else
case 0x18: // FDC: COMMAND
set_fdc_cmd((uint8_t)data);
- //printf("FDC: WRITE CMD %02x\n", data);
+ //out_debug_log("FDC: WRITE CMD %02x\n", data);
break;
case 0x19: // FDC: Track
set_fdc_track((uint8_t)data);
- //printf("FDC: WRITE TRACK REG %02x\n", data);
+ //out_debug_log("FDC: WRITE TRACK REG %02x\n", data);
break;
case 0x1a: // FDC: Sector
set_fdc_sector((uint8_t)data);
- //printf("FDC: WRITE SECTOR REG %02x\n", data);
+ //out_debug_log("FDC: WRITE SECTOR REG %02x\n", data);
break;
case 0x1b: // FDC: Data
set_fdc_data((uint8_t)data);
break;
case 0x1c:
set_fdc_fd1c((uint8_t)data);
- //printf("FDC: WRITE HEAD REG %02x\n", data);
+ //out_debug_log("FDC: WRITE HEAD REG %02x\n", data);
break;
case 0x1d:
set_fdc_fd1d((uint8_t)data);
- //printf("FDC: WRITE MOTOR REG %02x\n", data);
+ //out_debug_log("FDC: WRITE MOTOR REG %02x\n", data);
break;
case 0x1e:
set_fdc_fd1e((uint8_t)data);
defined(_FM77AV20) || defined(_FM77AV20SX) || defined(_FM77AV20EX)
mmr_segment = data & 7;
#else
- // printf("MMR SEGMENT: %02x\n", data & 3);
+ // out_debug_log("MMR SEGMENT: %02x\n", data & 3);
mmr_segment = data & 3;
#endif
mainmem->write_data8(FM7_MAINIO_MMR_SEGMENT, (uint32_t)mmr_segment);
}
break;
default:
- //printf("MAIN: Write I/O Addr=%08x DATA=%02x\n", addr, data);
+ //out_debug_log("MAIN: Write I/O Addr=%08x DATA=%02x\n", addr, data);
break;
}
if((addr < 0x40) && (addr >= 0x38)) {
set_clockmode((uint8_t)data);
return;
}
- //if((addr >= 0x0006) && !(addr == 0x1f)) printf("MAINIO: WRITE: %08x DATA=%08x\n", addr, data);
+ //if((addr >= 0x0006) && !(addr == 0x1f)) out_debug_log("MAINIO: WRITE: %08x DATA=%08x\n", addr, data);
}
void FM7_MAINIO::event_callback(int event_id, int err)
{
-// printf("MAIN EVENT id=%d\n", event_id);
+// out_debug_log("MAIN EVENT id=%d\n", event_id);
switch(event_id) {
case EVENT_BEEP_OFF:
event_beep_off();
void set_beep(uint32_t data); // fd03
virtual void reset_sound(void);
+ void reset_opn_psg(int ch_num);
void reset_printer(void);
void reset_fdc(void);
break;
case 0x0e: // PSG DATA
retval = (uint32_t) get_psg();
- //printf("PSG DATA READ val=%02x\n", retval);
+ //out_debug_log("PSG DATA READ val=%02x\n", retval);
return retval;
break;
case 0x0f: // FD0F
fio->Fopen(file_path, FILEIO_READ_WRITE_BINARY);
file_length = fio->FileLength();
if(file_length == 0) return false;
- //printf("Size=%d\n", file_length);
+ //out_debug_log("Size=%d\n", file_length);
if(file_length == 0x8000) { // 32KB
bubble_type = BUBBLE_TYPE_32KB;
media_size = 0x8000;
return false;
break;
}
- //printf("Write One Page: PAGE=%04x COUNT=%04x:\n ",page_address.w.l, page_count.w.l);
+ //out_debug_log("Write One Page: PAGE=%04x COUNT=%04x:\n ",page_address.w.l, page_count.w.l);
if(remain < (int)(offset + page_size)) return false;
fio->Fseek(f_pos + offset, FILEIO_SEEK_SET);
fio->Fwrite(&bubble_data[offset], page_size, 1);
} else if(sc == 0x53) { // LSHIFT
lshift_pressed = flag;
shift_pressed = lshift_pressed | rshift_pressed;
- //printf("LSHIFT : %d\n", flag ? 1 : 0);
+ //out_debug_log("LSHIFT : %d\n", flag ? 1 : 0);
} else if(sc == 0x54) { // RSHIFT
rshift_pressed = flag;
shift_pressed = lshift_pressed | rshift_pressed;
- //printf("RSHIFT : %d\n", flag ? 1 : 0);
+ //out_debug_log("RSHIFT : %d\n", flag ? 1 : 0);
} else if(sc == 0x56) { // GRPH
graph_pressed = flag;
} else if(sc == 0x55) { // CAPS
mode = cmd_fifo->read();
if(mode <= KEYMODE_SCAN) {
keymode = mode;
- //printf("Keymode : %d\n", keymode);
+ //out_debug_log("Keymode : %d\n", keymode);
//reset_unchange_mode();
beep_phase = 0;
autokey_backup = 0x00;
raddr = ((window_offset * 256) + addr) & 0x0ffff;
*realaddr = raddr;
#ifdef _FM77AV_VARIANTS
- //printf("TWR hit %04x -> %04x\n", addr, raddr);
+ //out_debug_log("TWR hit %04x -> %04x\n", addr, raddr);
return FM7_MAINMEM_AV_PAGE0; // 0x00000 - 0x0ffff
#else // FM77(L4 or others)
*realaddr |= 0x20000;
void (__FASTCALL FM7_MAINMEM::*write_func)(uint32_t, uint32_t, bool);
write_func = this->mmr_update_table_nor[n_pos].write_func;
raddr = mmr_baseaddr_table_nor[n_pos] | (addr & 0xfff);
- //printf("%08x %08x %08x\n", addr, raddr, n_pos);
+ //out_debug_log("%08x %08x %08x\n", addr, raddr, n_pos);
(this->*write_func)(raddr, data, dmamode);
}
return;
}
if((addr >= 0xfffe) && (addr < 0x10000)) {
uint32_t raddr = addr - 0xe000;
- //printf("%04x %02x\n", raddr, fm7_mainmem_initrom[raddr]);
+ //out_debug_log("%04x %02x\n", raddr, fm7_mainmem_initrom[raddr]);
iowait();
return fm7_mainmem_initrom[raddr];
}
do_compare(addr);
break;
}
- //printf("ALU DMYREAD ADDR=%04x, CMD=%02x CMP STATUS=%02x DISABLE=%01x\n", addr, command_reg, cmp_status_reg, bank_disable_reg);
+ //out_debug_log("ALU DMYREAD ADDR=%04x, CMD=%02x CMP STATUS=%02x DISABLE=%01x\n", addr, command_reg, cmp_status_reg, bank_disable_reg);
//if(eventid_busy >= 0) cancel_event(this, eventid_busy) ;
//register_event(this, EVENT_MB61VH010_BUSY_OFF, 1.0 / 16.0, false, &eventid_busy) ;
}
do_compare(addr);
break;
}
- //printf("ALU CMDS ADDR=%04x, CMD=%02x CMP STATUS=%02x\n", addr, command_reg, cmp_status_reg);
+ //out_debug_log("ALU CMDS ADDR=%04x, CMD=%02x CMP STATUS=%02x\n", addr, command_reg, cmp_status_reg);
return;
}
namespace FM7 {
+void FM7_MAINIO::reset_opn_psg(int ch_num)
+{
+ if((ch_num < 0) || (ch_num > 3)) return;
+ opn_data[ch_num]= 0;
+ opn_cmdreg[ch_num] = 0;
+ opn_address[ch_num] = 0;
+ opn_stat[ch_num] = 0;
+ opn_prescaler_type[ch_num] = 1;
+ memset(opn_regs[ch_num], 0x00, 0x100 * sizeof(uint8_t));
+ if(ch_num == 3) {
+#if !defined(_FM77AV_VARIANTS)
+ if(psg != NULL) {
+ psg->reset();
+ write_opn_reg(3, 0x2e, 0);
+ write_opn_reg(3, 0x27, 0);
+ write_opn_reg(3, 0, 0);
+ }
+#endif
+ return;
+ }
+ if(opn[ch_num] != NULL) {
+ opn[ch_num]->reset();
+ write_opn_reg(ch_num, 0x2e, 0);
+ write_opn_reg(ch_num, 0x27, 0);
+ }
+ return;
+}
+
void FM7_MAINIO::reset_sound(void)
{
int i, j;
-//#if !defined(_FM8)
- for(i = 0; i < 3; i++) {
- opn_data[i]= 0;
- opn_cmdreg[i] = 0;
- opn_address[i] = 0;
- opn_stat[i] = 0;
- opn_prescaler_type[i] = 1;
- memset(opn_regs[i], 0x00, 0x100 * sizeof(uint8_t));
- if(opn[i] != NULL) {
- opn[i]->reset();
- write_opn_reg(i, 0x2e, 0);
- write_opn_reg(i, 0x27, 0);
- }
+ for(i = 0; i < 4; i++) {
+ reset_opn_psg(i);
}
-//#endif
-#if !defined(_FM77AV_VARIANTS)
- if(psg != NULL) {
- psg->reset();
- write_opn_reg(3, 0x2e, 0);
- write_opn_reg(3, 0x27, 0);
- }
-#endif
+
#if defined(_FM77AV_VARIANTS)
opn_psg_77av = true;
#else
uint8_t FM7_MAINIO::get_opn(int index)
{
uint8_t val = 0xff;
- if((index > 2) || (index < 0)) return val;
+ if((index > 3) || (index < 0)) return val;
if((index == 0) && (!connect_opn)) return val;
if((index == 1) && (!connect_whg)) return val;
if((index == 2) && (!connect_thg)) return val;
if(psg == NULL) return val;
} else
# endif
- if(opn[index] == NULL) {
- return val;
- }
+ if(opn[index] == NULL) {
+ return val;
+ }
+ // 20190922 from XM7 3477a.
+ static const uint8_t opn_bitmask[16] = {
+ 0xff, 0x0f, 0xff, 0x0f,
+ 0xff, 0x0f, 0x1f, 0xff,
+ 0x1f, 0x1f, 0x1f, 0xff,
+ 0xff, 0x0f, 0xff, 0xff,
+ };
+
if(index == 3) opn_cmdreg[index] = opn_cmdreg[index] & 0x03;
+
switch(opn_cmdreg[index]) {
case 0: // Unavailable
val = 0xff;
} else {
# if !defined(_FM77AV_VARIANTS)
if(index == 3) {
- val = psg->read_io8(1);
+// if(opn_address[index] < 0x10) {
+ val = psg->read_io8(1) & opn_bitmask[opn_address[index] & 15];
+// }
} else
# endif
{