[VM][FMTOWNS][CDROM] DMAC driven DMA_IRQ.
dma->set_context_ch1(scsi_host);
//dma->set_context_ch2(printer);
dma->set_context_ch3(cdrom);
+ dma->set_context_tc(cdrom, SIG_TOWNS_CDROM_DMAINT, 1 << 3);
dma->set_context_ube1(scsi_host, SIG_SCSI_16BIT_BUS, 0x02);
dma->set_context_child_dma(extra_dma);
reset();
}
break;
+ case SIG_TOWNS_CDROM_DMAINT:
+ if((data & mask) != 0) {
+ set_dma_intr(true);
+ }
+ break;
default:
// SCSI_DEV::write_signal(id, data, mask);
// ToDo: Implement master devices.
if(read_length > 0) {
out_debug_log(_T("READ NEXT SECTOR"));
set_status(true, 0, TOWNS_CD_STATUS_DATA_READY, 0x00, 0x00, 0x00);
- set_dma_intr(true);
+ set_mcu_intr(true);
register_event(this, EVENT_CDROM_SEEK_COMPLETED,
(1.0e6 / ((double)transfer_speed * 150.0e3)) * 16.0, // OK?
false, NULL);
#define SIG_TOWNS_CDROM_ABSOLUTE_MSF 0x21
#define SIG_TOWNS_CDROM_READ_DATA 0x22
#define SIG_TOWNS_CDROM_RESET 0x23
+#define SIG_TOWNS_CDROM_DMAINT 0x24
class SCSI_HOST;
class FIFO;
dma->set_context_memory(memory);
dma->set_context_ch0(sasi);
dma->set_context_ch1(fdc);
- dma->set_context_tc(pic, SIG_I8259_CHIP0 | SIG_I8259_IR3, 1);
+ dma->set_context_tc(pic, SIG_I8259_CHIP0 | SIG_I8259_IR3, 3); // OK?
dma->set_context_tc(sasi, SIG_SASI_TC, 1);
opn->set_context_irq(pic, SIG_I8259_CHIP1 | SIG_I8259_IR7, 1);
opn->set_context_port_a(crtc, SIG_CRTC_PALLETE, 0x04, 0);
sreq &= ~bit;
tc |= bit;
- write_signals(&outputs_tc, 0xffffffff);
+ write_signals(&outputs_tc, tc);
return true;
}
if(_SINGLE_MODE_DMA) {