1 //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp
2 // Spec Reference: dsp32shift a0 ashift, lshift, rot
5 .include "testutils.inc"
24 A0 = A0 << 0; /* a0 = 0x00000000 */
25 R1 = A0.w; /* r5 = 0x00000000 */
26 CHECKREG r1, 0x012C003E;
31 A0 = A0 << 1; /* a0 = 0x00000000 */
32 R2 = A0.w; /* r5 = 0x00000000 */
33 CHECKREG r2, 0x026B3C48;
38 A0 = A0 << 15; /* a0 = 0x00000000 */
39 R3 = A0.w; /* r5 = 0x00000000 */
40 CHECKREG r3, 0xCF120000;
45 A0 = A0 << 31; /* a0 = 0x00000000 */
46 R4 = A0.w; /* r5 = 0x00000000 */
47 CHECKREG r4, 0x00000000;
52 A0 = A0 >>> 1; /* a0 = 0x00000000 */
53 R5 = A0.w; /* r5 = 0x00000000 */
54 CHECKREG r5, 0x28B13579;
60 A0 = A0 >>> 16; /* a0 = 0x00000000 */
61 R6 = A0.w; /* r5 = 0x00000000 */
62 CHECKREG r6, 0x00009176;
67 A0 = A0 >>> 31; /* a0 = 0x00000000 */
68 R0 = A0.w; /* r5 = 0x00000000 */
69 CHECKREG r0, 0x00000001;
74 .dw 0xC683 // .dw 0xC683 // A0 = A0 >>> 32;
76 R7 = A0.w; /* r5 = 0x00000000 */
77 CHECKREG r7, 0x00000000;
92 A0 = A0 << 0; /* a0 = 0x00000000 */
93 R1 = A0.w; /* r5 = 0x00000000 */
94 CHECKREG r1, 0x028C003E;
99 A0 = A0 << 3; /* a0 = 0x00000000 */
100 R2 = A0.w; /* r5 = 0x00000000 */
101 CHECKREG r2, 0x10ACF120;
106 A0 = A0 << 15; /* a0 = 0x00000000 */
107 R3 = A0.w; /* r5 = 0x00000000 */
108 CHECKREG r3, 0xCF120000;
113 A0 = A0 << 31; /* a0 = 0x00000000 */
114 R4 = A0.w; /* r5 = 0x00000000 */
115 CHECKREG r4, 0x00000000;
120 A0 = A0 >> 1; /* a0 = 0x00000000 */
121 R5 = A0.w; /* r5 = 0x00000000 */
122 CHECKREG r5, 0x29713579;
128 A0 = A0 >> 16; /* a0 = 0x00000000 */
129 R6 = A0.w; /* r5 = 0x00000000 */
130 CHECKREG r6, 0x00009226;
135 A0 = A0 >> 31; /* a0 = 0x00000000 */
136 R7 = A0.w; /* r5 = 0x00000000 */
137 CHECKREG r7, 0x00000001;
143 .dw 0x4100 // A0 = A0 >> 32;
144 R0 = A0.w; /* r5 = 0x00000000 */
145 CHECKREG r0, 0x00000000;
147 imm32 r0, 0x13340000;
148 imm32 r1, 0x038C003E;
149 imm32 r2, 0x83159E24;
150 imm32 r3, 0x83159E24;
151 imm32 r4, 0xD359E268;
152 imm32 r5, 0x53E26AF2;
153 imm32 r6, 0x9326AF36;
154 imm32 r7, 0xE36BFF86;
160 A0 = ROT A0 BY 0; /* a0 = 0x00000000 */
161 R1 = A0.w; /* r5 = 0x00000000 */
162 CHECKREG r1, 0x038C003E;
167 A0 = ROT A0 BY 1; /* a0 = 0x00000000 */
168 R2 = A0.w; /* r5 = 0x00000000 */
169 CHECKREG r2, 0x062B3C48;
174 A0 = ROT A0 BY 15; /* a0 = 0x00000000 */
175 R3 = A0.w; /* r5 = 0x00000000 */
176 CHECKREG r3, 0xCF120060;
181 A0 = ROT A0 BY 31; /* a0 = 0x00000000 */
182 R4 = A0.w; /* r5 = 0x00000000 */
183 CHECKREG r4, 0x62B4D678;
188 A0 = ROT A0 BY -1; /* a0 = 0x00000000 */
189 R5 = A0.w; /* r5 = 0x00000000 */
190 CHECKREG r5, 0x29F13579;
195 A0 = ROT A0 BY -16; /* a0 = 0x00000000 */
196 R6 = A0.w; /* r5 = 0x00000000 */
197 CHECKREG r6, 0x6C9A9326;
202 A0 = ROT A0 BY -31; /* a0 = 0x00000000 */
203 R7 = A0.w; /* r5 = 0x00000000 */
204 CHECKREG r7, 0xAFFE1ABD;
209 A0 = ROT A0 BY -32; /* a0 = 0x00000000 */
210 R0 = A0.w; /* r5 = 0x00000000 */
211 CHECKREG r0, 0x6800018D;