1 ; -*- coding: utf-8 -*-
4 ; Fast Forth For Texas Instrument CHIPSTICK MSP430FR2433
6 ; Copyright (C) <2016> <J.M. THOORENS>
8 ; This program is free software: you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
21 ; ======================================================================
22 ; INIT CHIPSTICK MSP430FR2433
23 ; ======================================================================
26 ; http://www.ebay.fr/itm/CP2102-USB-UART-Board-mini-Data-Transfer-Convertor-Module-Development-Board-/251433941479
28 ; for sd card socket be carefull : pin CD must be present !
29 ; http://www.ebay.com/itm/2-PCS-SD-Card-Module-Slot-Socket-Reader-For-Arduino-MCU-/181211954262?pt=LH_DefaultDomain_0&hash=item2a3112fc56
32 ; ChipStick PROG Header
33 ; ------------------------
41 ; ChipStick Header PL1
42 ; ------------------------
45 ; P3 - 4 - P1.5 UCA0 RXD
46 ; P4 - 3 - P1.4 UCA0 TXD
47 ; P5 - 5 - P1.6 UCA0 CLK
50 ; P8 - 7 - P1.0 UCB0 STE
51 ; P9 - 8 - P1.1 UCB0 CLK
52 ; P10- 9 - P1.2 UCB0 SIMO/SDA
54 ; ChipStick Header PL2
55 ; -------------------------
61 ; P6 - 17 - P2.6 UCA1 TX/SIMO
62 ; P7 - 16 - P2.5 UCA1 RX/SOMI
63 ; P8 - 15 - P2.4 UCA1 CLK
65 ; P10- 10 - P1.3 UCB0 SOMI/SCL
68 ; LED1 - 14 - P3.1 UCA1 STE
74 ; ===================================================================================
75 ; in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
76 ; then wire VCC and GND of bridge onto J13 connector
77 ; ===================================================================================
79 ; ---------------------------------------------------
80 ; CHIPSTICK_FR2433 <--> OUTPUT WORLD
81 ; ---------------------------------------------------
87 ; +--4k7-< DeepRST <-- GND
89 ; P1.4 - UCA0 TXD PL1.4 - <-+-> RX UARTtoUSB bridge
90 ; P1.5 - UCA0 RXD PL1.3 - <---- TX UARTtoUSB bridge
91 ; P3.2 - RTS PL1.2 - ----> CTS UARTtoUSB bridge (if TERMINALCTSRTS option)
93 ; P3.0 - PL1.7 - ----> /CS SPI_RAM
94 ; P1.1 - UCB0 CLK PL1.9 - ----> CLK SPI_RAM
95 ; P1.2 - UCB0 SIMO PL1.10 - ----> SI SPI_RAM
96 ; P1.3 - UCB0 SOMI PL2.10 - <---- S0 SPI_RAM
99 ; P1.1 - UCB0 CLK PL1.9 - ----> SD_CLK
100 ; P1.2 - UCB0 SIMO PL1.10 - ----> SD_SDI
101 ; P1.3 - UCB0 SOMI PL2.10 - <---- SD_SDO
102 ; P2.3 - PL1.6 - <---- SD_CD (Card Detect)
103 ; P2.2 - PL2.9 - ----> SD_CS (Card Select)
105 ; P1.2 - UCB0 SDA PL1.10 - <---> SDA I2C Slave
106 ; P1.3 - UCB0 SCL PL2.10 - ----> SCL I2C Slave
108 ; P2.2 - PL2.9 - ----> SCL I2C SoftMaster
109 ; P2.0 - PL2.3 - <---> SDA I2C SoftMaster
111 ; P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5)
113 ; ----------------------------------------------------------------------
114 ; INIT order : WDT, GPIOs, FRAM, Clock, UARTs...
115 ; ----------------------------------------------------------------------
117 ; ----------------------------------------------------------------------
118 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
119 ; ----------------------------------------------------------------------
121 ; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
123 ; ----------------------------------------------------------------------
124 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
125 ; ----------------------------------------------------------------------
128 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
130 ; ----------------------------------------------------------------------
131 ; POWER ON RESET AND INITIALIZATION : I/O
132 ; ----------------------------------------------------------------------
134 ; ----------------------------------------------------------------------
135 ; POWER ON RESET AND INITIALIZATION : PORT1/2
136 ; ----------------------------------------------------------------------
138 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
140 ; PORTx default wanted state : pins as input with pullup resistor
142 MOV #-1,&PAOUT ; OUT1 for all pins
143 BIS #-1,&PAREN ; all pins with pull resistors
147 TXD .equ 10h ; P1.4 = TXD + FORTH Deep_RST pin
157 SD_SEL .equ PASEL0 ; to configure UCB0
158 SD_REN .equ PAREN ; to configure pullup resistors
159 SD_BUS .equ 000Eh ; pins P1.1 as UCB0CLK, P1.2 as UCB0SIMO & P1.3 as UCB0SOMI
162 SD_CD .equ 8 ; P2.3 as SD_CD
163 SD_CS .equ 4 ; P2.2 as SD_CS
171 TXD .equ 40h ; P2.6 = TXD + FORTH Deep_RST pin
173 TERM_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
179 ; ----------------------------------------------------------------------
180 ; POWER ON RESET AND INITIALIZATION : PORT3
181 ; ----------------------------------------------------------------------
183 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
188 ; RTS output is wired to the CTS input of UART2USB bridge
189 ; CTS is not used by FORTH terminal
190 ; configure RTS as output high to disable RX TERM during start FORTH
192 ; PORTx default wanted state : pins as input with pullup resistor
194 MOV.B #001h,&P3DIR ; all pins as input else LED1 as output
195 BIS.B #-1,&P3REN ; all inputs with pull resistors
196 MOV.B #0FDh,&P3OUT ; all pins with pullup resistors and LED1 = output low
198 .IFDEF TERMINAL4WIRES
199 ; RTS output is wired to the CTS input of UART2USB bridge
200 ; configure RTS as output high to disable RX TERM during start FORTH
201 HANDSHAKOUT .equ P3OUT
204 BIS.B #RTS,&P3DIR ; RTS as output high
205 .IFDEF TERMINAL5WIRES
206 ; CTS input must be wired to the RTS output of UART2USB bridge
207 ; configure CTS as input low (true) to avoid lock when CTS is not wired
209 BIC.B #CTS,&P3OUT ; CTS input pulled down
210 .ENDIF ; TERMINAL5WIRES
211 .ENDIF ; TERMINAL4WIRES
213 ; ----------------------------------------------------------------------
215 ; ----------------------------------------------------------------------
218 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
219 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
220 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
223 ; ----------------------------------------------------------------------
224 ; POWER ON RESET SYS config
225 ; ----------------------------------------------------------------------
228 ; BIC #1,&SYSCFG0 ; enable write program in FRAM
229 MOV #0A500h,&SYSCFG0 ; enable write MAIN and INFO
231 ; ----------------------------------------------------------------------
232 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
233 ; ----------------------------------------------------------------------
235 ; CS code for EXP430FR2433
237 ; to measure REFO frequency, output ACLK on P2.2:
240 ; result : REFO = 32.69kHz
242 ; ===================================================================
243 ; need to adjust FLLN (and DCO) for each device of MSP430fr2xxx family ?
244 ; (no problem with MSP430FR5xxx families without FLL).
245 ; ===================================================================
249 MOV #0D6h,&CSCTL0 ; preset DCO = 0xD6 (measured value @ 0x180 ; to measure, type 0x180 @ U.)
251 MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
252 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
253 ; MOV #200Dh,&CSCTL2 ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Dh
254 ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz
255 ; MOV #200Eh,&CSCTL2 ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Eh
256 ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz
257 MOV #200Fh,&CSCTL2 ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Fh
258 ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
259 ; =====================================
262 .ELSEIF FREQUENCY = 0.5
264 MOV #0D6h,&CSCTL0 ; preset DCO = 0xD6 (measured value @ 0x180 ; to measure, type 0x180 @ U.)
266 MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
267 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
268 ; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh
269 ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz
270 ; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh
271 ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz
272 MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
273 ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
274 ; =====================================
277 .ELSEIF FREQUENCY = 1
279 MOV #00B4h,&CSCTL0 ; preset DCO = 0xB4 (measured value @ 0x180 ; to measure, type HEX 0x180 ?)
281 MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
282 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
283 ; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh
284 ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz
285 MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh
286 ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz
287 ; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
288 ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
289 ; =====================================
292 .ELSEIF FREQUENCY = 2
294 MOV #00B4h,&CSCTL0 ; preset DCO = 0xB4 (measured value @ 0x180 ; to measure, type HEX 0x180 ?)
296 MOV #0003h,&CSCTL1 ; Set 2MHZ DCORSEL,disable DCOFTRIM,Modulation
297 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
298 ; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh
299 ; fCOCLKDIV = 32768 x (59+1) = 1.996 MHz ; measured : MHz
300 ; MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch
301 ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz
302 MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
303 ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz
304 ; =====================================
307 .ELSEIF FREQUENCY = 4
309 MOV #00D2h,&CSCTL0 ; preset DCO = 0xD2 (measured value @ 0x180)
311 MOV #0005h,&CSCTL1 ; Set 4MHZ DCORSEL,disable DCOFTRIM,Modulation
312 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
313 ; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h
314 ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz
316 MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h
317 ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz
319 ; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
320 ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
321 ; =====================================
324 .ELSEIF FREQUENCY = 8
327 MOV #00F3h,&CSCTL0 ; preset DCO = 0xF2 (measured value @ 0x180)
329 MOV #0007h,&CSCTL1 ; Set 8MHZ DCORSEL,disable DCOFTRIM,Modulation
330 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
331 ; MOV #00F2h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F2h
332 ; fCOCLKDIV = 32768 x (242+1) = 7.963 MHz ; measured : 7.943MHz
333 ; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h
334 ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz
335 ; MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h
336 ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz
338 ; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h
339 ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz
341 ; MOV #00F8h,&CSCTL2 ; don't work with cp2102 (by low value)
342 ; MOV #00FAh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh
343 ; ===================================================================
344 ; CHIPSTICK_FR2433 : TLV area corrupted when welding ?
345 ; ===================================================================
346 MOV #00FCh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FCh
347 ; fCOCLKDIV = 32768 x (252+1) = 8.290 MHz <============ why ?
349 ; =====================================
352 .ELSEIF FREQUENCY = 16
354 MOV #0129h,&CSCTL0 ; preset DCO = 0x129 (measured value @ 0x180)
356 MOV #000Bh,&CSCTL1 ; Set 16MHZ DCORSEL,disable DCOFTRIM,Modulation
357 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
358 ; MOV #01E6h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h
359 ; fCOCLKDIV = 32768 x 486+1) = 15.958 MHz ; measured : 15.92MHz
360 ; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
361 ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz
362 ; MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
363 ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz
364 MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
365 ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
366 ; =====================================
370 .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
374 ; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
375 MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
377 BIS #0010h,&CSCTL3 ; FLL select REFCLOCK
378 ; MOV #0100h,&CSCTL4 ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value)
381 BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
382 ; MOV &SAVE_SYSRSTIV,TOS ;
383 ; CMP #2,TOS ; POWER ON ?
384 ; JZ ClockWaitX ; yes
385 ; RRUM #2,X ; wait only 125 ms
386 ClockWaitX MOV #5209,Y ; wait 0.5s before starting after POR
387 ; ...because FLL lock time = 280 ms
388 ClockWaitY SUB #1,Y ;1
389 JNZ ClockWaitY ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
390 SUB #1,X ; x 32 @ 1 MHZ = 500ms
391 JNZ ClockWaitX ; time to stabilize power source ( 500ms )
393 ;WAITFLL BIT #300h,&CSCTL7 ; wait FLL lock