2 ; -----------------------------------------------------------------------
4 ; -----------------------------------------------------------------------
7 \ MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
9 \ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC
10 \ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
12 \ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack
14 \ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
15 \ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
17 \ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack
19 \ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
20 \ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
22 \ FORTH conditionnal : 0= 0< = < > U<
28 ; --------------------------------------------------------------------------------
29 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV : Adda|Cmpa|Mova|Suba (without extended word)
30 ; --------------------------------------------------------------------------------
31 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
32 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
33 ; --------------------------------------------------------------------------------
40 ; you should see: 45 53 54 52>0B 0A<04 44 55 4D 50 4F
48 ; you should see: 45 53 54 52>1A 0B<04 44 55 4D 50 4F
56 ; you should see: 45 53 54 52>2B 01 45 23<04 44 55 4D
64 ; you should see: 45 53 54 52>3C 0A 34 12<04 44 55 4D
72 ; you should see: 45 53 54 52>61 0B 45 23<04 44 55 4D
80 ; you should see: 45 53 54 52>7A 0C 34 12<04 44 55 4D
88 ; you should see: 45 53 54 52>8C 00 01 00<04 44 55 4D
96 ; you should see: 45 53 54 52>9C 01 45 23<04 44 55 4D
104 ; you should see: 45 53 54 52>AC 02 56 34<04 44 55 4D
112 ; you should see: 45 53 54 52>BC 03 67 45<04 44 55 4D
122 ; you should see: 45 53 54 52>CB 0A<04 44 55 4D 50 4F
130 ; you should see: 45 53 54 52>DB 0A<04 44 55 4D 50 4F
138 ; you should see: 45 53 54 52>EB 0A<04 44 55 4D 50 4F
146 ; you should see: 45 53 54 52>FB 0A<04 44 55 4D 50 4F
149 ; --------------------------------------------------------------------------------
150 ; DTCforthMSP430FR5xxx ASSEMBLER: CALLA (without extended word)
151 ; --------------------------------------------------------------------------------
152 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
153 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
154 ; --------------------------------------------------------------------------------
161 ; you should see: 45 53 54 52>4A 13<04 44 55 4D 50 4F
169 ; you should see: 45 53 54 52>5A 13 56 34<04 44 55 4D
177 ; you should see: 45 53 54 52>6A 13<04 44 55 4D 50 4F
185 ; you should see: 45 53 54 52>7A 13<04 44 55 4D 50 4F
193 ; you should see: 45 53 54 52>82 13 56 34<04 44 55 4D
201 ; you should see: 45 53 54 52>B5 13 89 67<04 44 55 4D
204 ; --------------------------------------------------------------------------------
205 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES V extended double operand
206 ; --------------------------------------------------------------------------------
207 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
208 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
209 ; --------------------------------------------------------------------------------
217 ; you should see: 45 53 54 52>0B 4C 40 18 0B 4C<04 44
226 ; you should see: 45 53 54 52>0B 5B 00 18 4B 5B<04 44
236 ; you should see: 45 53 54 52>0B 5B 89 18 4B 5B<04 44
246 ; you should see: 45 53 54 52>0B 5B 07 18 4B 5B<04 44
255 ; you should see: 45 53 54 52>3B 60 76 98 80 1A 7B 60
265 ; you should see: 45 53 54 52>1B 62 76 98 80 1A 5B 62
275 ; you should see: 45 53 54 52>5B EC 32 54 46 18 5B EC
285 ; you should see: 45 53 54 52>8C 7B 32 54 06 18 CC 7B
295 ; you should see: 45 53 54 52>CC EB 32 54 46 18 CC EB
299 ; --------------------------------------------------------------------------------
300 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES VI extended single operand (take count of RPT)
301 ; --------------------------------------------------------------------------------
302 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
303 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
304 ; --------------------------------------------------------------------------------
312 ; you should see: 45 53 54 52>09 11 40 18 09 11<04 44
321 ; you should see: 45 53 54 52>29 10 00 18 69 10<04 44
330 ; you should see: 45 53 54 52>2C 10 00 18 6C 10<04 44
339 ; you should see: 45 53 54 52>39 10 00 19 79 10<04 44
349 ; you should see: 45 53 54 52>0B 10 08 19 4B 10<04 44
359 ; you should see: 45 53 54 52>0B 10 89 19 4B 10<04 44
368 ; you should see: 45 53 54 52>30 12 45 23 40 18 30 12
378 ; you should see: 45 53 54 52>12 12 78 56 00 1A 52 12
388 ; you should see: 45 53 54 52>52 12 33 00 40 18 52 12
398 ; you should see: 45 53 54 52>5B 12 44 33 40 18 5B 12
405 BASE @ %10 BASE ! SWAP 8 EMIT . BASE !
409 BASE @ %10 BASE ! SWAP 8 EMIT U. BASE ! ;
420 \ MOVX #$F0F0,Y \ don't forget decimal point with MOVX instruction !
429 RRUX_T ; you should see %111100001111000 --> %
448 RRUX_T ; you should see %111100001111000 --> %
462 RRUX_T ; you should see %111100001111 --> %
476 RRUX_T ; you should see %11110000 --> %
496 RRCX_T ; you should see %100000000000000 --> %
515 RRCX_T ; you should see %100000000000000 --> %
530 RRCX_T ; you should see %10000000 --> %
548 RRAX_T ; you should see %-100000000000000 --> %
567 RRAX_T ; you should see %-100000000000000 --> %
581 RRAX_T ; you should see %-10000000000000 --> %
595 RRAX_T ; you should see %-1000000000000 --> %
609 RRAX_T ; you should see %-100000000 --> %
624 MOV #.,PC \ BRANCH to .
627 RLAX_T ; you should see -2 -->
643 MOV #.,PC \ BRANCH to .
646 RLAX_T ; you should see -2 -->
657 MOV #.,PC \ BRANCH to .
660 RLAX_T ; you should see -4 -->
671 MOV #.,PC \ BRANCH to .
674 RLAX_T ; you should see -8 -->
685 MOV #.,PC \ BRANCH to .
688 RLAX_T ; you should see -256 -->
704 MOV #.,PC \ BRANCH to .
707 ADDX_T ; you should see -1 -->
724 MOV #.,PC \ BRANCH to .
727 ADDX_T ; you should see -1 -->
739 MOV #.,PC \ BRANCH to .
742 ADDX_T ; you should see -2 -->
754 MOV #.,PC \ BRANCH to .
757 ADDX_T ; you should see -8 -->
774 MOV #.,PC \ BRANCH to .
777 SUBX_T ; you should see 1 -->
794 MOV #.,PC \ BRANCH to .
797 SUBX_T ; you should see 1 -->
809 MOV #.,PC \ BRANCH to .
812 SUBX_T ; you should see 2 -->
824 MOV #.,PC \ BRANCH to .
827 SUBX_T ; you should see 8 -->
831 CODE SUBX_T \ W register = R10
832 MOV #15,W \ RPT [W] times, modulo 16 <--> RPT #15
840 MOV #.,PC \ BRANCH to .
843 SUBX_T ; you should see 16 -->
848 MOV #32,W \ RPT [W] times, modulo 16 <--> RPT #0
856 MOV #.,PC \ BRANCH to .
859 SUBX_T ; you should see 1 -->
864 MOV #33,W \ RPT [W] times, modulo 16 <--> RPT #1
872 MOV #.,PC \ BRANCH to .
875 SUBX_T ; you should see 2 -->