1 \ -*- coding: utf-8 -*-
3 ; -----------------------------------------------------------------------
5 ; -----------------------------------------------------------------------
7 \ TARGET SELECTION ( = the name of \INC\target.pat file without the extension)
8 \ MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
10 \ from scite editor : copy your target selection in (shift+F8) parameter 1:
14 \ drag and drop this file onto SendSourceFileToTarget.bat
15 \ then select your TARGET when asked.
18 \ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC
19 \ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
21 \ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack
23 \ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
24 \ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
26 \ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack
28 \ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
29 \ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
31 \ FORTH conditionnal : 0= 0< = < > U<
37 SUB #400,TOS \ FastForth V4.0
39 'CR' EMIT \ return to column 1 without 'LF'
40 ABORT" FastForth V4.0 please!"
41 RST_RET \ remove ABORT_TEST_ASM definition before resuming
44 ABORT_TEST_ASMX \ abort test
48 \ https://forth-standard.org/standard/core/Plus
49 \ + n1/u1 n2/u2 -- n3/u3 add n1+n2
58 \ https://forth-standard.org/standard/core/Minus
59 \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
63 SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
65 ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2
71 [IF] \ define MAX and MIN
72 CODE MAX \ n1 n2 -- n3 signed maximum
79 CODE MIN \ n1 n2 -- n3 signed minimum
87 \ https://forth-standard.org/standard/core/CFetch
88 \ C@ c-addr -- char fetch char from memory
97 \ https://forth-standard.org/standard/core/CONSTANT
98 \ CONSTANT <name> n -- define a Forth CONSTANT
104 MOV TOS,-2(W) \ PFA = n
111 \ https://forth-standard.org/standard/core/SPACE
112 \ SPACE -- output a space
119 \ https://forth-standard.org/standard/core/SPACES
120 \ SPACES n -- output n spaces
136 MOV @PSP+,TOS \ -- drop n
141 \ https://forth-standard.org/standard/core/OVER
142 \ OVER x1 x2 -- x1 x2 x1
146 MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
147 MOV @PSP,TOS \ 2 -- x1 (x2) x1
148 SUB #2,PSP \ 1 -- x1 x2 x1
153 \ https://forth-standard.org/standard/core/SWAP
154 \ SWAP x1 x2 -- x2 x1 swap top two items
165 \ https://forth-standard.org/standard/core/toR
166 \ >R x -- R: -- x push to return stack
176 \ https://forth-standard.org/standard/core/Rfrom
177 \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
189 [IF] \ defined in {UTILITY}
190 : U.R \ u n -- display u unsigned in n width (n >= 2)
192 R> OVER - 0 MAX SPACES TYPE
197 [IF] \ define DO LOOP +LOOP
199 \ https://forth-standard.org/standard/core/DO
200 \ DO -- DOadr L: -- 0
201 HDNCODE XDO \ DO run time
202 MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor"
204 MOV TOS,Y \ 1 loop ctr = index+fudge
205 ADD X,Y \ 1 Y = INDEX
206 PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX
214 ADD #2,&DP \ make room to compile xdo
215 MOV &DP,TOS \ -- HERE+2
216 MOV #XDO,-2(TOS) \ compile xdo
217 ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2
219 MOV #0,0(W) \ -- HERE+2 L-- 0, init
223 \ https://forth-standard.org/standard/core/LOOP
224 \ LOOP DOadr -- L-- an an-1 .. a1 0
225 HDNCODE XLOOP \ LOOP run time
226 ADD #1,0(RSP) \ 4 increment INDEX
227 BW1 BIT #$100,SR \ 2 is overflow bit set?
228 0= IF \ branch if no overflow
232 ADD #4,RSP \ 1 empties RSP
233 ADD #2,IP \ 1 overflow = loop done, skip branch ofs
234 MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop
239 BW2 ADD #4,&DP \ make room to compile two words
241 MOV X,-4(W) \ xloop --> HERE
242 MOV TOS,-2(W) \ DOadr --> HERE+2
243 BEGIN \ resolve all "leave" adr
244 MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell
245 SUB #2,&LEAVEPTR \ --
246 MOV @TOS,TOS \ -- first LeaveStack value
247 CMP #0,TOS \ -- = value left by DO ?
249 MOV W,0(TOS) \ move adr after loop as UNLOOP adr
255 \ https://forth-standard.org/standard/core/PlusLOOP
256 \ +LOOP adrs -- L-- an an-1 .. a1 0
257 HDNCODE XPLOO \ +LOOP run time
258 ADD TOS,0(RSP) \ 4 increment INDEX by TOS value
259 MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags
269 \ https://forth-standard.org/standard/core/I
270 \ I -- n R: sys1 sys2 -- sys1 sys2
271 \ get the innermost loop index
275 SUB #2,PSP \ 1 make room in TOS
277 MOV @RSP,TOS \ 2 index = loopctr - fudge
283 \ https://forth-standard.org/standard/core/CR
284 \ CR -- send CR+LF to the output device
287 \ DEFER CR \ DEFERed definition, by default executes that of :NONAME
288 \ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition
289 CODE CR \ part I : DEFERed definition of CR
290 MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR
298 \ https://forth-standard.org/standard/core/BASE
299 \ BASE -- a-addr holds conversion radix
302 BASEADR CONSTANT BASE
305 \ https://forth-standard.org/standard/tools/DUMP
307 [IF] \ defined in {UTILITY}
308 CODE DUMP \ adr n -- dump memory
310 PUSH &BASE \ save current base
311 MOV #$10,&BASE \ HEX base
312 ADD @PSP,TOS \ -- ORG END
315 DO CR \ generate line
316 I 4 U.R SPACE \ generate address
323 I $10 + I \ display 16 chars
324 DO I C@ $7E MIN $20 MAX EMIT LOOP
326 R> BASE ! \ restore current base
342 ; -----------------------------------------------------------------------------
343 ; DTCforthMSP430FR5xxx ASSEMBLER: CALLA (without extended word)
344 ; -----------------------------------------------------------------------------
345 ; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers)
346 ; indexed instructions must be written as $xxxx(REG) (single numbers)
347 ; -----------------------------------------------------------------------------
354 ; you should see: 4A 13
362 ; you should see: 5A 13 56 34
370 ; you should see: 5F 13 00 00
378 ; you should see: 6A 13
386 ; you should see: 6F 13
394 ; you should see: 7A 13
402 ; you should see: 82 13 56 34
410 ; you should see: B5 13 89 67
413 ; -----------------------------------------------------------------------------
414 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV : Adda|Cmpa|Mova|Suba
415 ; -----------------------------------------------------------------------------
416 ; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers)
417 ; indexed instructions must be written as $xxxx(REG) (single numbers)
418 ; -----------------------------------------------------------------------------
425 ; you should see: 0B 0A
433 ; you should see: 1A 0B
441 ; you should see: 2B 01 45 23
449 ; you should see: 3E 0F 02 00
457 ; you should see: 3C 0A 34 12
465 ; you should see: 61 0B 45 23
473 ; you should see: 7F 0E 00 00
481 ; you should see: 7A 0C 34 12
489 ; you should see: 8C 00 01 00
497 ; you should see: 9C 01 45 23
505 ; you should see: AC 02 56 34
513 ; you should see: BC 03 67 45
521 ; you should see: CB 0A
529 ; you should see: DB 0A
537 ; you should see: EB 0A
545 ; you should see: FB 0A
548 ; -----------------------------------------------------------------------------
549 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES V extended double operand
550 ; -----------------------------------------------------------------------------
551 ; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers)
552 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
553 ; -----------------------------------------------------------------------------
561 ; you should see: 0B 4C 40 18 0B 4C
570 ; you should see: 0B 5B 00 18 4B 5B
580 ; you should see: 0B 5B 89 18 4B 5B
590 ; you should see: 0B 5B 07 18 4B 5B
599 ; you should see: 3B 60 76 98 80 1A 7B 60 76 98
608 ; you should see: 1B 62 76 98 80 1A 5B 62 76 98
617 ; you should see: 5B EC 32 54 46 18 5B EC 32 54
626 ; you should see: 8C 7B 32 54 06 18 CC 7B 32 54
635 ; you should see: CC EB 32 54 46 18 CC EB 32 54
638 ; -----------------------------------------------------------------------------
639 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES VI extended single operand
640 ; -----------------------------------------------------------------------------
641 ; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers)
642 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
643 ; -----------------------------------------------------------------------------
651 ; you should see: 09 11 40 18 09 11
660 ; you should see: 29 10 00 18 69 10
669 ; you should see: 2C 10 00 18 6C 10
678 ; you should see: 39 10 00 19 79 10
688 ; you should see: 0B 10 08 19 4B 10
698 ; you should see: 0B 10 89 19 4B 10
707 ; you should see: 30 12 45 23 40 18 30 12 45 23
716 ; you should see: 12 12 78 56 00 1A 52 12 78 56
725 ; you should see: 52 12 33 00 40 18 52 12 33 00
734 ; you should see: 5B 12 44 33 40 18 5B 12 44 33
737 \ https://forth-standard.org/standard/core/BASE
738 \ BASE -- a-addr holds conversion radix
741 ' # 2 + CONSTANT BASE
747 BASE @ %10 BASE ! SWAP 8 EMIT . BASE !
752 BASE @ %10 BASE ! SWAP 8 EMIT U. BASE !
764 \ MOVX #$F0F0,Y \ don't forget decimal point with MOVX instruction !
774 ; you should see: %111100001111000
792 ; you should see: %111100001111000
805 ; you should see: %111100001111
818 ; you should see: %11110000
835 ; you should see: %100000000000000
853 ; you should see: %100000000000000
867 ; you should see: %10000000
883 ; you should see: %-100000000000000
901 ; you should see: %-100000000000000
914 ; you should see: %-10000000000000
927 ; you should see: %-1000000000000
940 ; you should see: %-100000000
953 MOV #.,PC \ BRANCH to .
956 RLAX_T ; you should see -2 -->
970 MOV #.,PC \ BRANCH to .
973 RLAX_T ; you should see -2 -->
982 MOV #.,PC \ BRANCH to .
985 RLAX_T ; you should see -4 -->
994 MOV #.,PC \ BRANCH to .
997 RLAX_T ; you should see -8 -->
1006 MOV #.,PC \ BRANCH to .
1009 RLAX_T ; you should see -256 -->
1023 MOV #.,PC \ BRANCH to .
1026 ADDX_T ; you should see -1 -->
1041 MOV #.,PC \ BRANCH to .
1044 ADDX_T ; you should see -1 -->
1054 MOV #.,PC \ BRANCH to .
1057 ADDX_T ; you should see -2 -->
1067 MOV #.,PC \ BRANCH to .
1070 ADDX_T ; you should see -8 -->
1084 MOV #.,PC \ BRANCH to .
1087 SUBX_T ; you should see 1 -->
1102 MOV #.,PC \ BRANCH to .
1105 SUBX_T ; you should see 1 -->
1115 MOV #.,PC \ BRANCH to .
1118 SUBX_T ; you should see 2 -->
1128 MOV #.,PC \ BRANCH to .
1131 SUBX_T ; you should see 8 -->
1133 CODE SUBX_T \ W register = R10
1134 MOV #15,W \ RPT [W] times, modulo 16 <--> RPT #16
1142 MOV #.,PC \ BRANCH to .
1145 SUBX_T ; you should see 16 -->
1148 MOV #32,W \ RPT [W] times, modulo 16 <--> RPT #1
1156 MOV #.,PC \ BRANCH to .
1159 SUBX_T ; you should see 1 -->
1162 MOV #33,W \ RPT [W] times, modulo 16 <--> RPT #2
1170 MOV #.,PC \ BRANCH to .
1173 SUBX_T ; you should see 2 -->