2 ; -----------------------------------------------------------------------
4 ; -----------------------------------------------------------------------
7 \ MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
9 \ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC
10 \ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
12 \ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack
14 \ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
15 \ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
17 \ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack
19 \ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
20 \ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
22 \ FORTH conditionnal : 0= 0< = < > U<
25 [UNDEFINED] {ASMEXT_TEST} [IF]
31 ; --------------------------------------------------------------------------------
32 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV : Adda|Cmpa|Mova|Suba (without extended word)
33 ; --------------------------------------------------------------------------------
34 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
35 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
36 ; --------------------------------------------------------------------------------
43 ; you should see: 45 53 54 52>0B 0A<04 44 55 4D 50 4F
51 ; you should see: 45 53 54 52>1A 0B<04 44 55 4D 50 4F
59 ; you should see: 45 53 54 52>2B 01 45 23<04 44 55 4D
67 ; you should see: 45 53 54 52>3C 0A 34 12<04 44 55 4D
75 ; you should see: 45 53 54 52>61 0B 45 23<04 44 55 4D
83 ; you should see: 45 53 54 52>7A 0C 34 12<04 44 55 4D
91 ; you should see: 45 53 54 52>8C 00 01 00<04 44 55 4D
99 ; you should see: 45 53 54 52>9C 01 45 23<04 44 55 4D
107 ; you should see: 45 53 54 52>AC 02 56 34<04 44 55 4D
115 ; you should see: 45 53 54 52>BC 03 67 45<04 44 55 4D
125 ; you should see: 45 53 54 52>CB 0A<04 44 55 4D 50 4F
133 ; you should see: 45 53 54 52>DB 0A<04 44 55 4D 50 4F
141 ; you should see: 45 53 54 52>EB 0A<04 44 55 4D 50 4F
149 ; you should see: 45 53 54 52>FB 0A<04 44 55 4D 50 4F
152 ; --------------------------------------------------------------------------------
153 ; DTCforthMSP430FR5xxx ASSEMBLER: CALLA (without extended word)
154 ; --------------------------------------------------------------------------------
155 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
156 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
157 ; --------------------------------------------------------------------------------
164 ; you should see: 45 53 54 52>4A 13<04 44 55 4D 50 4F
172 ; you should see: 45 53 54 52>5A 13 56 34<04 44 55 4D
180 ; you should see: 45 53 54 52>6A 13<04 44 55 4D 50 4F
188 ; you should see: 45 53 54 52>7A 13<04 44 55 4D 50 4F
196 ; you should see: 45 53 54 52>82 13 56 34<04 44 55 4D
204 ; you should see: 45 53 54 52>B5 13 89 67<04 44 55 4D
207 ; --------------------------------------------------------------------------------
208 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES V extended double operand
209 ; --------------------------------------------------------------------------------
210 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
211 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
212 ; --------------------------------------------------------------------------------
220 ; you should see: 45 53 54 52>0B 4C 40 18 0B 4C<04 44
229 ; you should see: 45 53 54 52>0B 5B 00 18 4B 5B<04 44
239 ; you should see: 45 53 54 52>0B 5B 89 18 4B 5B<04 44
249 ; you should see: 45 53 54 52>0B 5B 07 18 4B 5B<04 44
258 ; you should see: 45 53 54 52>3B 60 76 98 80 1A 7B 60
268 ; you should see: 45 53 54 52>1B 62 76 98 80 1A 5B 62
278 ; you should see: 45 53 54 52>5B EC 32 54 46 18 5B EC
288 ; you should see: 45 53 54 52>8C 7B 32 54 06 18 CC 7B
298 ; you should see: 45 53 54 52>CC EB 32 54 46 18 CC EB
302 ; --------------------------------------------------------------------------------
303 ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES VI extended single operand (take count of RPT)
304 ; --------------------------------------------------------------------------------
305 ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers)
306 ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers)
307 ; --------------------------------------------------------------------------------
315 ; you should see: 45 53 54 52>09 11 40 18 09 11<04 44
324 ; you should see: 45 53 54 52>29 10 00 18 69 10<04 44
333 ; you should see: 45 53 54 52>2C 10 00 18 6C 10<04 44
342 ; you should see: 45 53 54 52>39 10 00 19 79 10<04 44
352 ; you should see: 45 53 54 52>0B 10 08 19 4B 10<04 44
362 ; you should see: 45 53 54 52>0B 10 89 19 4B 10<04 44
371 ; you should see: 45 53 54 52>30 12 45 23 40 18 30 12
381 ; you should see: 45 53 54 52>12 12 78 56 00 1A 52 12
391 ; you should see: 45 53 54 52>52 12 33 00 40 18 52 12
401 ; you should see: 45 53 54 52>5B 12 44 33 40 18 5B 12
408 BASE @ %10 BASE ! SWAP 8 EMIT . BASE !
412 BASE @ %10 BASE ! SWAP 8 EMIT U. BASE ! ;
423 \ MOVX #$F0F0,Y \ don't forget decimal point with MOVX instruction !
432 RRUX_T ; you should see %111100001111000 --> %
451 RRUX_T ; you should see %111100001111000 --> %
465 RRUX_T ; you should see %111100001111 --> %
479 RRUX_T ; you should see %11110000 --> %
499 RRCX_T ; you should see %100000000000000 --> %
518 RRCX_T ; you should see %100000000000000 --> %
533 RRCX_T ; you should see %10000000 --> %
551 RRAX_T ; you should see %-100000000000000 --> %
570 RRAX_T ; you should see %-100000000000000 --> %
584 RRAX_T ; you should see %-10000000000000 --> %
598 RRAX_T ; you should see %-1000000000000 --> %
612 RRAX_T ; you should see %-100000000 --> %
627 MOV #.,PC \ BRANCH to .
630 RLAX_T ; you should see -2 -->
646 MOV #.,PC \ BRANCH to .
649 RLAX_T ; you should see -2 -->
660 MOV #.,PC \ BRANCH to .
663 RLAX_T ; you should see -4 -->
674 MOV #.,PC \ BRANCH to .
677 RLAX_T ; you should see -8 -->
688 MOV #.,PC \ BRANCH to .
691 RLAX_T ; you should see -256 -->
707 MOV #.,PC \ BRANCH to .
710 ADDX_T ; you should see -1 -->
727 MOV #.,PC \ BRANCH to .
730 ADDX_T ; you should see -1 -->
742 MOV #.,PC \ BRANCH to .
745 ADDX_T ; you should see -2 -->
757 MOV #.,PC \ BRANCH to .
760 ADDX_T ; you should see -8 -->
777 MOV #.,PC \ BRANCH to .
780 SUBX_T ; you should see 1 -->
797 MOV #.,PC \ BRANCH to .
800 SUBX_T ; you should see 1 -->
812 MOV #.,PC \ BRANCH to .
815 SUBX_T ; you should see 2 -->
827 MOV #.,PC \ BRANCH to .
830 SUBX_T ; you should see 8 -->
834 CODE SUBX_T \ W register = R10
835 MOV #15,W \ RPT [W] times, modulo 16 <--> RPT #15
843 MOV #.,PC \ BRANCH to .
846 SUBX_T ; you should see 16 -->
851 MOV #32,W \ RPT [W] times, modulo 16 <--> RPT #0
859 MOV #.,PC \ BRANCH to .
862 SUBX_T ; you should see 1 -->
867 MOV #33,W \ RPT [W] times, modulo 16 <--> RPT #1
875 MOV #.,PC \ BRANCH to .
878 SUBX_T ; you should see 2 -->