MSP430-FORTH/lib/IR_RC5_to_I2CF_Soft_Master.f

   1 \ IR_RC5_to_I2CF_Soft_Master.f
   2
   3 \ Copyright (C) <2016>  <J.M. THOORENS>
   4 \
   5 \ This program is free software: you can redistribute it and/or modify
   6 \ it under the terms of the GNU General Public License as published by
   7 \ the Free Software Foundation, either version 3 of the License, or
   8 \ (at your option) any later version.
   9 \
  10 \ This program is distributed in the hope that it will be useful,
  11 \ but WITHOUT ANY WARRANTY\ without even the implied warranty of
  12 \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 \ GNU General Public License for more details.
  14 \
  15 \ You should have received a copy of the GNU General Public License
  16 \ along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17
  18
  19 \ --------------------------------------\
  20 \ example of App running under interrupt
  21 \ --------------------------------------\
  22 \ FORTH driver for IR remote compatible with the PHILIPS RC5 protocol, with select new/repeated command
  23
  24 \ target : any MSP430FRxxxx @ 8Mhz
  25
  26 \ prerequisites : your launchpad is wired as described in launchpad.pat file : UART0, Soft_Master(SDA,SCL), IR_RC5 parts.
  27 \                 FastForth runs @ 8MHz
  28 \                 add 3k3 pull up resistors on SDA and SCL lines.
  29
  30 \ usage :   create a logical network drive ( a: b: ...as you want) from your local copy of Gitlab FAST FORTH
  31 \           with scite.exe open this file MSP430-FORTH\IR_RC5_to_I2CF_Soft_Master.f,
  32 \           select "tools" menu, "preprocess" item 1 (CTRL+0),
  33 \           a dialog box asks you for 4 parameters $(1) to $(4),
  34 \           in the 2th param. field, type your launchpad to select the launchpad.pat to be used : for example MSP_EXP430FR5969,
  35 \ result :  the word START starts the app that runs under LPMx.
  36
  37 \           to recover the console input (i.e. to quit LPMx), type a space. Then you can enter a command, for example STOP.
  38
  39 \ select one initial state :
  40 WIPE        \ to suppress any previous app
  41 \ RST_STATE   \ to conserve the previous app protected against <reset>
  42 \ PWR_STATE   \ to conserve the previous app protected against POWER OFF
  43 NOECHO      \ comment if an error occurs, to detect it with new download
  44
  45 \ HERE        \ uncomment for a dump, part 1
  46     \
  47
  48
  49
  50 \ -------------------------------------------------------------------------------------------------------------------\
  51 \ I2CF Soft MASTER driver, FAST MODE, 8MHz
  52 \ -------------------------------------------------------------------------------------------------------------------\
  53
  54 VARIABLE I2CS_ADR   \ low(I2CS_ADR) = slave I2C address with RW flag, high(I2CS_ADR) = RX buffer,data0
  55 2 ALLOT             \ data1,data2
  56 VARIABLE I2CM_BUF   \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
  57 2 ALLOT             \ data1,data2
  58     \
  59
  60 \ ------------------------------\
  61 ASM I2C_MTX                     \ MASTER TX \ shared code for address and TX data
  62 \ ------------------------------\
  63 BEGIN                           \
  64     ADD.B   X,X                 \ 1 l     shift one left
  65     U>= IF                      \ 2 l carry set ?
  66         BIC.B #MSDA,&I2CSM_DIR  \ 4 l yes : SDA as input  ==> SDA high because pull up resistor
  67     ELSE                        \ 2 l
  68         BIS.B #MSDA,&I2CSM_DIR  \ 4 l no  : SDA as output ==> SDA low
  69     THEN                        \   l   _
  70     BIC.B #MSCL,&I2CSM_DIR      \ 4 l _^    release SCL (high)
  71     BEGIN                       \           14/16~l
  72         BIT.B #MSCL,&I2CSM_IN   \ 3 h       test if SCL is released
  73     0<> UNTIL                   \ 2 h _
  74     BIS.B #MSCL,&I2CSM_DIR      \ 4 h  v_   SCL as output : force SCL low
  75     SUB #1,W                    \ 1 l     count of bits
  76 0= UNTIL                        \ 2 l
  77 BIC.B   #MSDA,&I2CSM_DIR        \ 5 l _   SDA as input : release SDA high to prepare read Ack/Nack
  78 RET
  79 ENDASM                          \
  80     \
  81
  82 \ ******************************\
  83 \ IR_RC5 driver                 \ IP,S,T,W,X,Y registers are free for use
  84 \ ******************************\
  85 ASM INT_RC5                     \ wake up on P1.2 change interrupt \ IP,TOS,W,X,Y are free for use
  86 \ ------------------------------\
  87 BIC #$F8,0(RSP)                 \ SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPMx_LOOP with pending interrupt
  88 \ BIC #$B8,0(RSP)                \ {SCG1,OSCOFF,CPUOFF,GIE}=OFF after RETI to force goto label "LPMx_LOOP" with any pending interrupt
  89 \ ------------------------------\
  90 \ define LPM mode for ACCEPT    \ uncomment a line
  91 \ ------------------------------\
  92 \ MOV #LPM4,&LPM_MODE             \ with MSP430FR59xx
  93 \ MOV #LPM2,&LPM_MODE             \ with MSP430FR57xx, terminal input don't work for LPMx > 2
  94 \                                 \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
  95 \ ------------------------------\
  96 \                               \ in :  SR(9)=old Toggle bit memory (ADD on)
  97 \                               \       SMclock = 8|16|24 MHz
  98 \                               \ use : IP,TOS,W,X,Y, TA0 timer, TA0R register
  99 \                               \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
 100 \                               \       SR(9)=new Toggle bit memory (ADD on)
 101 \ ------------------------------\
 102 \ RC5_FirstStartBitHalfCycle:   \
 103 \ ------------------------------\
 104 MOV     #0,&TA0EX0              \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
 105 \    MOV     #1,&TA0EX0          \ predivide by 2 in TA0EX0 register (16 MHZ)
 106 \    MOV     #2,&TA0EX0          \ predivide by 3 in TA0EX0 register (24 MHZ)
 107 MOV     #1778,X                 \ RC5_Period in us
 108 MOV     #14,W                   \ count of loop
 109 BEGIN                           \
 110 \ ------------------------------\
 111 \ RC5_TopSynchro:               \ <--- loop back ---+ with readjusted RC5_Period
 112 \ ------------------------------\                   | here, we are just after 1/2 RC5_cycle
 113     MOV #%1011100100,&TA0CTL    \ (re)start timer_A | SMCLK/8 : 2us time interval,free running,clear TA0_IFG and TA0R
 114 \ RC5_Compute_3/4_Period:        \                   |
 115     RRUM    #1,X                \ X=1/2 cycle       |
 116     MOV     X,Y                 \ Y=1/2             ^
 117     RRUM    #1,Y                \ Y=1/4
 118     ADD     X,Y                 \ Y=3/4
 119 \ RC5_Wait_1_1/4                 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
 120     BEGIN   CMP Y,&TA0R         \ CMP &TA0R with 3/4 cycle value
 121     0= UNTIL                    \
 122 \ ------------------------------\
 123 \ RC5_Sample:                   \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
 124 \ ------------------------------\
 125     BIT.B   #RC5,&IR_IN         \ C_flag = IR bit
 126     ADDC    IP,IP               \ C_flag <-- IP(15):IP(0) <-- C_flag
 127     MOV     &IR_IN,&IR_IES      \ preset Px_IES.y state for next IFG
 128     BIC.B   #RC5,&IR_IFG        \ clear Px_IFG.y after 4/4 cycle pin change
 129     SUB     #1,W                \ decrement count loop
 130 \                               \  count = 13 ==> IP = x  x  x  x  x  x  x  x |x  x  x  x  x  x  x /C6
 131 \                               \  count = 0  ==> IP = x  x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0  1
 132 0<> WHILE                       \ ----> out of loop ----+
 133 \ RC5_compute_7/4_Time_out:     \                       |
 134     ADD     X,Y                 \                       |   out of bound = 7/4 period
 135 \ RC5_WaitHalfCycleP1.2_IFG:    \                       |
 136     BEGIN                       \                       |
 137         CMP Y,&TA0R             \                       |   TA0R = 5/4 cycle test
 138         0>= IF                  \                       |   if cycle time out of bound
 139           BIC #$30,&TA0CTL      \                       |   stop timer_A0
 140           RETI                  \                       |   then quit to do nothing
 141         THEN                    \                       |
 142 \ ------------------------------\                       |
 143         BIT.B #RC5,&IR_IFG      \                   ^   |   test P1.2_IFG
 144     0<> UNTIL                   \                   |   |
 145     MOV &TA0R,X                 \                   |   |   get new RC5_period value
 146 REPEAT                          \ ----> loop back --+   |
 147 \ ------------------------------\                       |
 148 \ RC5_SampleEndOf:              \ <---------------------+
 149 \ ------------------------------\
 150 MOV #$30,&TA0CTL                \ stop timer_A0
 151 RLAM #1,IP                      \ IP =  x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0  1  0
 152 \ ******************************\
 153 \ Only New_RC5_Command ADD_ON   \ use SR(9) bit as toggle bit
 154 \ ******************************\
 155 MOV @RSP,X                      \ retiSR(9)  = old RC5 toggle bit
 156 RLAM #4,X                       \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
 157 XOR IP,X                        \ (new XOR old) Toggle bit (13)
 158 BIT #BIT13,X                    \ X(13) = New_RC5_command
 159 0= IF
 160     RETI                        \ case of repeated RC5_command : RETI without SR(9) change
 161 THEN                            \
 162 XOR #UF1,0(RSP)                 \ change Toggle bit memory, User Flag 1 = SR(9)
 163 \ ******************************\
 164 \ RC5_ComputeNewRC5word         \
 165 \ ******************************\
 166 MOV.B IP,S                      \ S = C5 C4 C3 C2 C1 C0  0  0
 167 RRUM #2,S                       \ S =  0  0 C5 C4 C3 C2 C1 C0
 168 \ ******************************\
 169 \ RC5_ComputeC6bit              \
 170 \ ******************************\
 171 BIT #BIT14,IP                   \ test /C6 bit in IP
 172 0= IF
 173    BIS #BIT6,S                  \ set C6 bit in S
 174 THEN                            \ S =  0  C6 C5 C4 C3 C2 C1 C0
 175 \ ******************************\
 176 \ RC5_CommandByteIsDone         \ RC5_code --
 177 \ ******************************\
 178 \ ------------------------------\
 179 \ Prepare I2C_MASTER            \
 180 \ ------------------------------\
 181 SWPB S                          \ 1 high byte = data
 182 ADD #1,S                        \ 1 low byte = count
 183 MOV S,&I2CM_BUF                 \ 3
 184 MOV #%0010100,&I2CS_ADR         \ MSP-EXP430FRxxx I2C slave address
 185 \ ------------------------------\
 186 \ echo code to terminal option  \
 187 \ ------------------------------\
 188 \ SUB #2,PSP
 189 \ MOV TOS,0(PSP)
 190 \ MOV.B S,TOS
 191 \ LO2HI
 192 \ cr ." $" HEX 2 U.R
 193 \ HI2LO
 194
 195 \ ==================================\
 196 \ CODE I2C_M                        \ fast I2C soft Master, only 8 MHz
 197 \ ==================================\
 198 \                                   \ in    I2CS_ADR/I2CM_BUF as RX/TX buffer requested by I2CS_ADR(0(0))
 199 \                                   \       I2CS_ADR(0) = I2C_Slave_addr&R/w
 200 \                                   \       I2CM_BUF(0) = TX/RX count of datas
 201 \                                   \       I2CM_BUF(0) = 0 ==> send only I2C address
 202 \                                   \ used  S           BUF ptr
 203 \                                   \       T           datas countdown
 204 \                                   \       W           bits countdown
 205 \                                   \       X           data
 206 \                                   \ out   I2CSLA_ADR & (R/W) unCHNGd
 207 \                                   \       S = BUF PTR pointing on first data not exCHNGd
 208 \                                   \       T = count+1 of TX/RX datas exCHNGd
 209 \                                   \       I2CS_ADR(0) = unCHNGd
 210 \                                   \       I2CM_BUF(0) = count of data not exCHNGd (normally = 0)
 211 \                                   \       I2CM_BUF(0) = -1 <==> Nack on address
 212 \ ----------------------------------\
 213 \ I2C_MR_DC_ListenBeforeStart:      \ test if SCL & SDA lines are idle (high)
 214 \ ----------------------------------\
 215 BIC.B #M_BUS,&I2CSM_DIR             \ SDA & SCL pins as input
 216 BIC.B #M_BUS,&I2CSM_OUT             \ preset output LOW for SDA & SCL pins
 217 MOV #2,T                            \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 8 MHz
 218 \ MOV #4,T                          \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 16 MHz
 219 \ MOV #6,T                          \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 24 MHz
 220 BEGIN                               \
 221     BEGIN                           \
 222         BEGIN                       \
 223            BIT.B #MSCL,&I2CSM_IN    \ 4 P1DIR.3 SCL high ?
 224         0<> UNTIL                   \ 2
 225         BIT.B #MSDA,&I2CSM_IN       \ 4 P1IN.2 SDA high ?
 226     0<> UNTIL                       \ 2
 227         SUB #1,T                    \ 1
 228 0= UNTIL                            \ 2 here the I2C bus is idle
 229 \ ----------------------------------\
 230 \ I2C_Master_Start_Cond:            \ here, SDA and SCL are in idle state
 231 \ ----------------------------------\
 232 BIS.B   #MSDA,&I2CSM_DIR            \ 4 l   force SDA as output (low)
 233 MOV     #I2CM_BUF,W                 \ 2 h   W=buffer out
 234 MOV.B   @W+,T                       \ 2 h   T=datas countdown
 235 MOV     #I2CS_ADR,S                 \ 2 h   S=buffer in
 236 MOV.B   @S+,X                       \ 2 h   X=Slave address to TX
 237 BIT.B   #1,X                        \ 1 h   test I2C R/w flag
 238 0= IF                               \ 2 h   if write
 239     MOV W,S                         \ 2 h   S= buffer out ptr
 240 THEN                                \       S= buffer ptr
 241 BIS.B   #MSCL,&I2CSM_DIR            \ 4 h   force SCL as output (low)
 242 \ ----------------------------------\
 243 \ I2C_Master_Start_EndOf:           \
 244 \ ----------------------------------\
 245 \ I2C_Master_Send_address           \       may be SCL is held low by slave
 246 \ ----------------------------------\
 247 ADD     #1,T                        \ 1 l   to add address in count
 248 MOV     #8,W                        \ 1 l   prepare 8 bit Master writing
 249 CALL    #I2C_MTX                    \ 21 l   to send address
 250 \ ----------------------------------\
 251 \ I2C_Master_Loop_Data              \
 252 \ ----------------------------------\
 253 BEGIN                               \ 4 l   here ack/nack is received/transmitted
 254 \   --------------------------------\   l
 255 \   Master TX/RX ACK/NACK           \
 256 \   --------------------------------\   l   _
 257     BIC.B   #MSCL,&I2CSM_DIR        \ 3 l _^    release SCL (high)
 258     BEGIN                           \
 259         BIT.B #MSCL,&I2CSM_IN       \ 3 h       test if SCL is released
 260     0<> UNTIL                       \ 2 h
 261     BIT.B   #MSDA,&I2CSM_IN         \ 3 h _     get SDA
 262     BIS.B   #MSCL,&I2CSM_DIR        \ 3 h  v_   SCL as output : force SCL low
 263 \   --------------------------------\   l
 264 \   I2C_Master_Loop_Data            \
 265 \   --------------------------------\
 266     0<> IF  BIS #Z,SR               \ 5 l   if Nack (TX), force Z=1 ==> StopCond
 267     ELSE    SUB.B #1,T              \ 3 l   else dec count
 268     THEN                            \ l
 269 \   --------------------------------\
 270 \   I2C_Master_CheckCountDown       \       count=0 (TX) or Nack received
 271 \   --------------------------------\
 272     0= IF                           \ 2 l   send stop
 273 \       ----------------------------\
 274 \       Send Stop                   \
 275 \       ----------------------------\     _
 276         BIS.B #MSDA,&I2CSM_DIR      \ 4 l  v_   SDA as output ==> SDA low
 277         SUB.B T,&I2CM_BUF           \ 4 l   _   refresh buffer length and reach tSU:STO
 278         BIC.B #MSCL,&I2CSM_DIR      \ 4 l _^    release SCL (high)
 279         BEGIN                       \
 280             BIT.B #MSCL,&I2CSM_IN   \ 3 h       SCL released ?
 281         0<> UNTIL                   \ 2 h
 282         BIC.B #MSDA,&I2CSM_DIR      \ 4 h _^    SDA as input  ==> SDA high with pull up resistor
 283 \        MOV @RSP+,PC               \ RET  ====>
 284         RETI                        \
 285     THEN                            \
 286     MOV.B #8,W                      \ 1 l     prepare 8 bits transaction
 287     BIT.B #1,&I2CS_ADR              \ 3 l     I2C_Master Read/write bit test
 288     0= IF                           \ 2 l     write flag test
 289 \       ============================\
 290 \       I2C_Master_TX               \
 291 \       ============================\
 292         MOV.B @S+,X                 \ 2 l     next byte to transmit
 293         CALL #I2C_MTX               \   l       to send data
 294     ELSE                            \ l
 295 \       ============================\
 296 \       I2C_Master_RX:              \       here, SDA is indetermined, SCL is strech low by master
 297 \       ============================\
 298         BIC.B #MSDA,&I2CSM_DIR      \ 5 l _    After ACK we must release SDA
 299         BEGIN                       \
 300 \           ------------------------\       _
 301 \           send bit                \ SCL _| |_
 302 \           ------------------------\       _
 303             BIC.B #MSCL,&I2CSM_DIR  \ 4 l _^    release SCL (high)
 304             BEGIN                   \           14/16~l
 305               BIT.B #MSCL,&I2CSM_IN \ 3 h       test if SCL is released
 306             0<> UNTIL               \ 2 h
 307             BIT.B #MSDA,&I2CSM_IN   \ 4 h _     get SDA
 308             BIS.B #MSCL,&I2CSM_DIR  \ 4 h  v_   SCL as output : force SCL low   13~
 309             ADDC.B X,X              \ 1 l   C <-- X <--- C
 310             SUB #1,W                \ 1 l   count of bits
 311         0= UNTIL                    \ 2 l
 312         MOV.B X,0(S)                \ 3 l     store byte in buffer
 313         ADD #1,S                    \ 1 l
 314 \       ----------------------------\
 315 \       Compute Ack Or Nack         \ here, SDA is released by slave, SCL is strech low by master
 316 \       ----------------------------\
 317         CMP.B #1,T                  \
 318         0<> IF                      \ 2 l
 319             BIS.B #MSDA,&I2CSM_DIR  \ 5 l       yes : send Ack
 320         THEN                        \
 321     THEN                            \
 322 AGAIN                               \ 2 l
 323 ENDASM                              \
 324     \
 325
 326
 327 \ ------------------------------\
 328 CODE START                      \
 329 \ ------------------------------\
 330 \ init PORT M_BUS (complement)  \ when reset occurs all I/O are set in input with resistors pullup
 331 BIC.B #M_BUS,&I2CSM_OUT         \ preset SDA + SCL output low
 332 BIC.B #M_BUS,&I2CSM_REN         \ SDA + SCL pullup/down disable
 333 \ ------------------------------\
 334 \ init PORT IR (complement) default I/O are input with pullup resistors
 335 BIS.B #RC5,&IR_IE               \ enable interrupt for TSOP32236
 336 BIC.B #RC5,&IR_IFG              \ clear int flag for TSOP32236
 337 \ ------------------------------\
 338 \ init interrupt vectors        \
 339 \ ------------------------------\
 340 MOV #INT_RC5,&IR_Vec            \ init IR vector interrupt
 341 \ ------------------------------\
 342 \ define LPM mode for ACCEPT    \
 343 \ ------------------------------\
 344 \ MOV #LPM4,&LPM_MODE             \ with MSP430FR59xx
 345 \ MOV #LPM2,&LPM_MODE             \ with MSP430FR57xx, terminal input don't work for LPMx > 2
 346 \                                 \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
 347 \ ------------------------------\
 348 LO2HI
 349 ." RC5toI2CF_Master is running. Type STOP to quit"
 350 \ NOECHO                          \ uncomment to run this app without terminal connexion
 351 LIT RECURSE IS WARM             \ insert this starting routine between COLD and WARM...
 352 (WARM) ;                        \ ...and continue with WARM (very, very usefull after COLD or RESET !:-)
 353     \
 354
 355 : STOP                  \ stops multitasking, must to be used before downloading app
 356     ['] (WARM) IS WARM  \ remove START app from FORTH init process
 357     ECHO COLD           \ reset CPU, interrupt vectors, and start FORTH
 358 ;
 359     \
 360
 361 ECHO
 362
 363 \ DUP HERE SWAP - DUMP            \ uncomment for a dump, part 2
 364     \
 365
 366 \ select one end state :
 367 RST_HERE    \ this app is protected against POWER OFF, <reset>, COLD, ...and STOP that executes COLD.
 368 \ PWR_HERE    \ this app is protected only againt POWER OFF
 369 \ nothing   \ this app is volatile !
 370
 371
 372 \ all lines beyond START command are ignored
 373
 374 \ --------------------------------------------------\
 375 \ PHILIPS IR REMOTE RC5/RC6 protocol                \
 376 \ --------------------------------------------------\
 377 \ first half bit = no light, same as idle state
 378 \ second half bit : 32 IR-light pulses of 6,944us,light ON/off ratio = 1/3
 379
 380 \        |<------32 IR light pulses = second half of first start bit ------->|
 381 \        |_     _     _     _     _     _     _     _     _     _     _     _|
 382 \ ...____| |___| |___| |___| |___| |___| |...| |___| |___| |___| |___| |___| |____________________________________...
 383 \        |                                                                   |
 384 \
 385
 386
 387 \ at the output of IR receiver TSOPxxx during the first start bit :
 388
 389 \ ...idle state ->|<----- first half bit ------>|<- second half bit (IR light) ->|
 390 \ ..._____________|_____________________________|                                |_________...
 391 \                 |                             |                                |
 392 \                 |                             |                                |
 393 \                 |                             |________________________________|
 394
 395 \ 32 cycles of 27,777us (36kHz) = 888,888 us
 396 \ one bit = 888,888 x 2 = 1778 us.
 397
 398
 399
 400 \   14 bits of active message   = 24.889 ms
 401 \ + 50  bits of silent (idle)   = 88.888 ms
 402 \ = RC5 message                 = 113.792 ms
 403
 404 \
 405 \ RC5_message on IR LIGHT \ idle state = light off
 406
 407 \ 89ms>|<--------------------------------------------------24.889 ms-------------------------------------------------->|<88,
 408 \      |                                                                                                               |
 409 \      |       |       |       |       |       |       |       |       |       |       |       |       |       |       |
 410 \      |  ST1  | ST2/C6|  Tog  |  A4   |  A3   |  A2   |  A1   |  A0   |  C5   |  C4   |  C3   |  C2   |  C1   |  C0   |
 411 \      |       |       |       |       |       |       |       |       |       |       |       |       |       |       |
 412 \          1       1       1       1       0       0       1       1       1       1       1       1       1       1
 413 \           ___     ___     ___     _______     ___         ___     ___     ___     ___     ___     ___     ___     ___
 414 \          ^   |   ^   |   ^   |   ^       |   |   |       ^   |   ^   |   ^   |   ^   |   ^   |   ^   |   ^   |   ^   |
 415 \  idle____|   |___|   |___|   |___|       v___|   v_______|   |___|   |___|   |___|   |___|   |___|   |___|   |___|   |____
 416 \
 417 \
 418 \ notice that each cycle contains its bit value preceded by its complement
 419
 420
 421
 422
 423 \ the same RC5_message inverted at the output of IR receiver : idle state = 1
 424 \
 425 \       |       |       |       |       |       |       |       |       |       |       |       |       |       |       |
 426 \       |  ST1  | ST2/C6|  Tog  |  A4   |  A3   |  A2   |   A1  |  A0   |  C5   |  C4   |  C3   |  C2   |  C1   |  C0   |
 427 \       |       |       |       |       |       |       |       |       |       |       |       |       |       |       |
 428 \           1       1       1       1       0       0       1       1       1       1       1       1       1       1
 429 \  idle_____     ___     ___     ___         ___     _______     ___     ___     ___     ___     ___     ___     ___     __idle
 430 \           |   |   |   |   |   |   |       ^   |   ^       |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
 431 \           v___|   v___|   v___|   v_______|   |___|       v___|   v___|   v___|   v___|   v___|   v___|   v___|   v___|
 432 \           I       R       R       R       R       R       R       R       R       R       R       R       R       R
 433 \
 434 \ notice that each cycle contains its bit value followed by its complement
 435
 436
 437
 438
 439 \ principe of the driver : 13 samples at 1/4 period and Resynchronise (R) on 1/2 period (two examples)
 440
 441 \       0,888 ms
 442 \       |<->|<--------------------------------routine time = 12 3/4 cycles = 22.644 ms--------------------------->|
 443 \       |       |       |       |       |       |       |       |       |       |       |       |       |       | |     |
 444 \       |  ST1  | ST2/C6| Toggle|  A4   |  A3   |  A2   |   A1  |  A0   |  C5   |  C4   |  C3   |  C2   |  C1   | |C0   |
 445 \       |       |       |       |       |       |       |       |       |       |       |       |       |       | |     |
 446 \           1       1       1       1       0       0       1       1       1       1       1       1       1     | 1
 447 \  idle_____     _s_     _s_     _s_         ___     _____s_     _s_     _s_     _s_     _s_     _s_     _s_     _s_     __idle
 448 \           |   |   |   |   |   |   |       ^   |   ^       |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
 449 \           v___|   v___|   v___|   v_____s_|   |_s_|       v___|   v___|   v___|   v___|   v___|   v___|   v___|   v___|
 450 \           S       R       R       R       R       R       R       R       R       R       R       R       R       ^   ^
 451 \ samples :       1       2       3       4       5       6       4       8       9      10      11      12      13 |   |
 452 \                                                                                                                   |   |
 453 \                                                                                                                   I   I
 454 \       0,888 ms
 455 \       |<->|<--------------------------------routine time = 12 3/4 cycles = 22.644 ms--------------------------->|
 456 \       |       |       |       |       |       |       |       |       |       |       |       |       |       | |     |
 457 \       |  ST1  | ST2/C6| Toggle|  A4   |  A3   |  A2   |   A1  |  A0   |  C5   |  C4   |  C3   |  C2   |  C1   | |C0   |
 458 \       |       |       |       |       |       |       |       |       |       |       |       |       |       | |     |
 459 \           1       1       1       1       0       0       1       1       1       1       1       1       1     | 1
 460 \  idle_____     _s_     _s_     ___         _o_     _o___s_     _s_     _s_     _s_     _s_     _s_     _s_         ______idle
 461 \           |   |   |   |   |   |   |       ^   |   ^       |   |   |   |   |   |   |   |   |   |   |   |   |       ^
 462 \           v___|   v_o_|   v_o_|   v_o___s_|   |_s_|       v_o_|   v_o_|   v_o_|   v_o_|   v_o_|   v_o_|   v_o___s_|
 463 \           S       R       R       R       R       R       R       R       R       R       R       R       R       ^
 464 \ samples :       1       2       3       4       5       6       7       8       9       10       11     12      13|
 465 \                                                                                                                   |
 466 \                                                                                                                   I
 467 \ good ! but we have too many of RC5_Int...
 468
 469
 470
 471
 472 \ So, to avoid these RC5_Int after end : 13+1=14 samples, then the result is shifted one to right (two examples)
 473
 474 \       0,888 ms
 475 \       |<->|<--------------------------------routine time = 13 3/4 cycles = 24.447 ms----------------------------------->|
 476 \       |       |       |       |       |       |       |       |       |       |       |       |       |       |       | |
 477 \       |  ST1  | ST2/C6| Toggle|  A4   |  A3   |  A2   |   A1  |  A0   |  C5   |  C4   |  C3   |  C2   |  C1   |  C0   | |
 478 \       |   1   |   1   |   1   |   1   |   0   |   0   |   1   |   1   |   1   |   1   |   1   |   1   |   1   |   1   | |
 479 \       |       |       |       |       |       |       |       |       |       |       |       |       |       |       | |
 480 \  idle_____     _s_     _s_     _s_         _o_     _o___s_     _s_     _s_     _s_     _s_     _s_     _s_     _s_     _s_idle
 481 \           |   |   |   |   |   |   |       ^   |   ^       |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
 482 \           v___|   v_o_|   v_o_|   v_o___s_|   |_s_|       v_o_|   v_o_|   v_o_|   v_o_|   v_o_|   v_o_|   v_o_|   v_o_|
 483 \           S   i   R   i   R   i   R       R   i   R       R   i   R   i   R   i   R   i   R   i   R   i   R   i   R   i
 484 \ samples :       1       2       3       4       5       6       7       8       9       10      11      12      13      14
 485 \
 486 \
 487 \       0,888 ms
 488 \       |<->|<--------------------------------routine time = 13 3/4 cycles = 24.447 ms----------------------------------->|
 489 \       |       |       |       |       |       |       |       |       |       |       |       |       |       |       | |
 490 \       |  ST1  | ST2/C6| Toggle|  A4   |  A3   |  A2   |   A1  |  A0   |  C5   |  C4   |  C3   |  C2   |  C1   |  C0   | |
 491 \       |   1   |   1   |   1   |   1   |   0   |   0   |   1   |   1   |   1   |   1   |   1   |   1   |   1   |   0   | |
 492 \       |       |       |       |       |       |       |       |       |       |       |       |       |       |       | |
 493 \  idle_____     _s_     _s_     ___         _o_     _o___s_     _s_     _s_     _s_     _s_     _s_     _s_         _o___s_idle
 494 \           |   |   |   |   |   |   |       ^   |   ^       |   |   |   |   |   |   |   |   |   |   |   |   |       ^
 495 \           v___|   v_o_|   v_o_|   v_o___s_|   |_s_|       v_o_|   v_o_|   v_o_|   v_o_|   v_o_|   v_o_|   v_o___s_|
 496 \           S   i   R   i   R   i   R       R   i   R       R   i   R   i   R   i   R   i   R   i   R   i   R       R
 497 \ samples :       1       2       3       4       5       6       7       8       9       10      11      12      13      14
 498
 499
 500 \ S = Wake up on RC5_Int at 1/2 cycle : clear and start timer
 501 \ i = useless RC5_Int (not periodic) at 4/4 cycle
 502 \ s = sample RC5_intput at (1/2+3/4) = 5/4 cycle = 1/4 cycle+1 and clear useless RC5_Int
 503 \ R = usefull (periodic) RC5_Int at 6/4 cycle = 1/2 cycle+1 : cycle value = timer value then clear it and restart it
 504 \ o = RC5_Int time out at 7/4 cycle = 3/4 cycle+1, used to detect (samples<14) truncated RC5_message
 505
 506 \ see also : http://www.sbprojects.com/knowledge/ir/rc5.php
 507 \            http://laurent.deschamps.free.fr/ir/rc5/rc5.htm
 508 \ Code RC5 : http://en.wikipedia.org/wiki/RC-5
 509
 510
 511 \ ---------------------------------------------------------------------------------------------------------------------\
 512 \ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
 513 \ slave can strech SCL low after Start Condition and after any bit.
 514 \
 515 \ address Ack/Nack is generated by the slave on SDA line (released by the master)
 516 \ Two groups of eight addresses (000xxxy and 1111xxxy) are not allowed (reserved)
 517 \ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
 518 \ data Ack/Nack are generated by the receiver (master or slave) on SDA line
 519 \ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
 520 \ Stop or restart conditions must be generated by master after a Nack bit.
 521 \ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions.
 522 \
 523 \
 524 \             first byte = address + R/W flag    | byte data (one, for example)
 525 \     __      _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_     _
 526 \ SDA   \____/_MSB_R9_____R9_..._R9_LSB_R9__R10__x_ACK_x_MSB_R9_____R9_..._R9_____R9_LSB_R9_ACK_R9___/
 527 \     _____     _     _           _     _     _     _     _           _     _     _     ___
 528 \ SCL      \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
 529 \       ^   ^                             ^     ^                             ^     ^    ^
 530 \       |   |SSL                          |SSL  |SSL                          |SSL  |SSL |
 531 \       |                                                                                |
 532 \       |Start Condition                                                                 |stoP Condition
 533 \
 534 \             first byte = address + R/W flag    | byte data (one, for example)
 535 \     __      _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_ ___
 536 \ SDA   \____/_MSB_R9_____R9_..._R9_LSB_R9__R10__x_ACK_x_MSB_R9_____R9_..._R9_____R9_LSB_R9_ACK_R9   \____...
 537 \     _____     _     _           _     _     _     _     _           _     _     _     ____
 538 \ SCL      \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/    \_...
 539 \       ^   ^                             ^     ^                             ^     ^    ^
 540 \       |   |SSL                          |SSL  |SSL                          |SSL  |SSL |
 541 \       |                                                                                |
 542 \       |Start Condition                                                                 |reStart Condition
 543 \
 544 \ SSL : Slave can strech SCL low
 545 \ tHIGH : SCL high time
 546 \ tLOW : SCL low time
 547 \ tBUF : SDA high time between Stop and Start conditions
 548 \ tHD:STA : Start_Condition SCL high time after SDA is low
 549 \ tSU:STO : Stop_Condition SCL high time before SDA rise
 550 \ tSU:STA : Start_Condition SCL high time before SDA fall
 551 \ tHD:DAT : SDA data change time after SCL is low
 552 \ the SDA line must be strobe just after SCL is high
 553 \ the SDA data must be change just after SCL is low
 554 \ standard mode (up to 100 kHz) :   tHIGH   =   tHD:STA =   tSU:STO =   4µs
 555 \                                   tLOW    =   tSU:STA =   tBUF    =   4,7µs
 556 \                                   tHD:DAT <=  3,45 µs
 557 \ -------------------------------------------------------------------------------------------------------------------\
 558