2 ; MSP430fr2433 minimal declarations for Fast FORTH usage
3 DEVICE = "MSP430FR2433"
5 ; ----------------------------------------------
6 ; MSP430FR2433 MEMORY MAP
7 ; ----------------------------------------------
8 ; 0000-0FFF = peripherals (4 KB)
9 ; 1000-17FF = ROM bootstrap loader BSL1 (2k)
10 ; 1800-19FF = info B (FRAM 512 B)
11 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
13 ; 2000-2FFF = RAM (4 KB)
15 ; C400-FF7F = code memory (FRAM 15232 B)
16 ; FF80-FFFF = interrupt vectors (FRAM 128 B)
17 ; FFC00-FFFFF = BSL2 (2k)
18 ; ----------------------------------------------
19 PAGESIZE .equ 512 ; MPU unit
20 ; ----------------------------------------------
22 ; ----------------------------------------------
25 ; ----------------------------------------------
27 ; ----------------------------------------------
29 INFOBSTART .equ 01800h
32 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
34 ; ----------------------------------------------
36 ; ----------------------------------------------
40 ; ----------------------------------------------
42 ; ----------------------------------------------
43 PROGRAMSTART .equ 0C400h ; Code space start
44 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
45 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
46 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked
47 BSL_SIG1 .equ 0FF84h ;
48 BSL_SIG2 .equ 0FF86h ;
49 JTAG_PASSWORD .equ 0FF88h ; 256 bits
50 BSL_PASSWORD .equ 0FFE0h ; 256 bits
51 INTVECT .equ 0FFDAh ; FFDA-FFFF
53 ; ----------------------------------------------
55 ; ----------------------------------------------
56 ; Interrupt Vectors and signatures - MSP430FR243x
57 ; ----------------------------------------------
60 ;;Start of JTAG and BSL signatures
61 ; .word 0FFFFh ; JTAG signature 1
62 ; .word 0FFFFh ; JTAG signature 2
63 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
64 ; .word 0FFFFh ; BSL signature 2
66 ; .org INTVECT ; FFDA-FFFF 18 vectors + reset
68 ; .word reset ; FFDAh - P2
69 ; .word reset ; FFDCh - P1
70 ; .word reset ; FFDEh - ADC10
71 ; .word reset ; FFE0h - eUSCI_B0
72 ; .word reset ; FFE2h - eUSCI_A1
73 ; .word reset ; FFE4h - eUSCI_A0
74 ; .word reset ; FFE6h - WDT
75 ; .word reset ; FFE8h - RTC
76 ; .word reset ; FFEAh - TA3_x
77 ; .word reset ; FFECh - TA3_0
78 ; .word reset ; FFEEh - TA2_x
79 ; .word reset ; FFF0h - TA2_0
80 ; .word reset ; FFF2h - TA1_x
81 ; .word reset ; FFF4h - TA1_0
82 ; .word reset ; FFF6h - TA0_x
83 ; .word reset ; FFF8h - TA0_0
84 ; .word reset ; FFFAh - UserNMI
85 ; .word reset ; FFFCh - SysNMI
86 ; .word reset ; FFFEh - Reset
88 ; ----------------------------------------------------------------------
89 ; MSP430FR2433 Peripheral File Map
90 ; ----------------------------------------------------------------------
91 SFR_SFR .equ 0100h ; Special function
92 PMM_SFR .equ 0120h ; PMM
93 SYS_SFR .equ 0140h ; SYS
94 CS_SFR .equ 0180h ; Clock System
95 FRAM_SFR .equ 01A0h ; FRAM control
97 WDT_A_SFR .equ 01CCh ; Watchdog
98 PA_SFR .equ 0200h ; PORT1/2
99 PB_SFR .equ 0220h ; PORT3
106 eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
107 eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
108 eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
109 BACK_MEM_SFR .equ 0660h
110 ADC10_B_SFR .equ 0700h
113 ; ----------------------------------------------------------------------
114 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
115 ; ----------------------------------------------------------------------
119 PM5CTL0 .equ PMM_SFR + 10h ; Power mode 5 control register 0
120 LOCKLPM5 .equ 1 ; bit position
122 ; ----------------------------------------------------------------------
123 ; POWER ON RESET SYS config
124 ; ----------------------------------------------------------------------
125 SYSCTL .equ SYS_SFR + 00h ; System control
126 SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area
127 SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control
128 SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0
129 SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1
130 SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0
131 SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1
132 SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator
133 SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator
134 SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator
135 SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator
136 SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0
137 SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1
138 SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2
144 ; ----------------------------------------------------------------------
145 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
146 ; ----------------------------------------------------------------------
148 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
150 ; WDTCTL Control Bits
152 WDTHOLD .equ 0080h ; WDT - Timer hold
153 WDTCNTCL .equ 0008h ; WDT timer counter clear
156 ; ----------------------------------------------------------------------
158 ; ----------------------------------------------------------------------
160 FRCTL0 .equ FRAM_SFR + 00h ; FRAM Controller Control 0
161 FRCTL0_H .equ FRAM_SFR + 01h ; FRAM Controller Control 0 high byte
163 ; ----------------------------------------------------------------------
164 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
165 ; ----------------------------------------------------------------------
167 CSCTL0 .equ CS_SFR + 00h ; Clock System Control Register 0
168 CSCTL1 .equ CS_SFR + 02h ; Clock System Control Register 1
169 CSCTL2 .equ CS_SFR + 04h ; Clock System Control Register 2
170 CSCTL3 .equ CS_SFR + 06h ; Clock System Control Register 3
171 CSCTL4 .equ CS_SFR + 08h ; Clock System Control Register 4
172 CSCTL5 .equ CS_SFR + 0Ah ; Clock System Control Register 5
173 CSCTL6 .equ CS_SFR + 0Ch ; Clock System Control Register 6
174 CSCTL7 .equ CS_SFR + 0Eh ; Clock System Control Register 7
175 CSCTL8 .equ CS_SFR + 10h ; Clock System Control Register 8
177 ; ----------------------------------------------------------------------
178 ; POWER ON RESET AND INITIALIZATION : PORT1/2
179 ; ----------------------------------------------------------------------
181 PAIN .equ PA_SFR + 00h ; Port A Input
182 PAOUT .equ PA_SFR + 02h ; Port A Output
183 PADIR .equ PA_SFR + 04h ; Port A Direction
184 PAREN .equ PA_SFR + 06h ; Port A Resistor Enable
185 PASEL0 .equ PA_SFR + 0Ah ; Port A Selection 0
186 PASEL1 .equ PA_SFR + 0Ch ; Port A Selection 1
187 PASELC .equ PA_SFR + 16h ; Port A Complement Selection
188 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
189 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
190 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt Flag
192 P1IN .equ PA_SFR + 00h ; Port 1 Input
193 P1OUT .equ PA_SFR + 02h ; Port 1 Output
194 P1DIR .equ PA_SFR + 04h ; Port 1 Direction
195 P1REN .equ PA_SFR + 06h ; Port 1 Resistor Enable
196 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 Selection 0
197 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 Selection 1
198 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
199 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
200 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
201 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt Flag
203 P2IN .equ PA_SFR + 01h ; Port 2 Input
204 P2OUT .equ PA_SFR + 03h ; Port 2 Output
205 P2DIR .equ PA_SFR + 05h ; Port 2 Direction
206 P2REN .equ PA_SFR + 07h ; Port 2 Resistor Enable
207 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 Selection 0
208 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 Selection 1
209 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
210 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
211 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag
212 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
214 ; ----------------------------------------------------------------------
215 ; POWER ON RESET AND INITIALIZATION : PORT3
216 ; ----------------------------------------------------------------------
218 P3IN .set PB_SFR + 00h ; Port 3 Input */
219 P3OUT .set PB_SFR + 02h ; Port 3 Output
220 P3DIR .set PB_SFR + 04h ; Port 3 Direction
221 P3REN .set PB_SFR + 06h ; Port 3 Resistor Enable
222 P3SEL0 .set PB_SFR + 0Ah ; Port 3 Selection 0
223 P3SEL1 .set PB_SFR + 0Ch ; Port 3 Selection 1
226 ; ----------------------------------------------------------------------
228 ; ----------------------------------------------------------------------
229 RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control
230 RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector
231 RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo
232 RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter
234 ; ----------------------------------------------------------------------
236 ; ----------------------------------------------------------------------
238 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
239 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
240 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
241 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
242 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
243 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
244 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
245 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
246 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
247 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
248 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
249 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
250 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
251 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
252 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
253 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
254 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
255 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
256 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
257 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
258 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
259 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
260 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
265 UCSWRST .equ 1 ; eUSCI Software Reset
266 UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
267 UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
268 UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
269 UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
273 ; ----------------------------------------------------------------------
275 ; ----------------------------------------------------------------------
278 TERMCTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
279 TERMBRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
280 TERMMCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
281 TERMRXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
282 TERMTXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
283 TERMIE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
284 TERMIFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
285 TERMVEC .equ 0FFE4h ; interrupt vector for eUSCI_A0
289 ; ----------------------------------------------------------------------
291 ; ----------------------------------------------------------------------
293 TERMCTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
294 TERMBRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
295 TERMMCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
296 TERMRXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
297 TERMTXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
298 TERMIE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
299 TERMIFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
300 TERMVEC .equ 0FFE2h ; interrupt vector for eUSCI_A1
304 SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; USCI_B0 Control Word Register 0
305 SD_BRW .equ eUSCI_A1_SFR + 06h ; USCI_B0 Baud Word Rate 0
306 SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; USCI_B0 Receive Buffer 8
307 SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
308 SD_IFG .equ eUSCI_A1_SFR + 1Ch ; USCI_B0 Interrupt Flags Register
311 ; ----------------------------------------------------------------------
313 ; ----------------------------------------------------------------------
315 I2CTERM_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
316 I2CTERM_CTLW1 .equ eUSCI_B0_SFR + 02h ; USCI_B0 Control Word Register 1
317 I2CTERM_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
318 I2CTERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
319 I2CTERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
320 I2CTERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0
321 I2CTERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register
322 I2CTERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address
323 I2CTERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable
324 I2CTERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
325 I2CTERMVEC .equ 0FFE0h ; interrupt vector for eUSCI_B0
328 .IFDEF UCB0_I2CM ; used by UART2MICC.asm
329 TERM2IIC_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
330 TERM2IIC_CTLW1 .equ eUSCI_B0_SFR + 02h ; USCI_B0 Control Word Register 1
331 TERM2IIC_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
332 TERM2IIC_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word
333 TERM2IIC_STAT .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Byte
334 TERM2IIC_BCNT .equ eUSCI_B0_SFR + 09h ; USCI_B0 Byte Counter Register Byte
335 TERM2IIC_TBCNT .equ eUSCI_B0_SFR + 0Ah ; USCI_B0 Byte Counter Threshold Register
336 TERM2IIC_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
337 TERM2IIC_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
338 TERM2IIC_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0
339 TERM2IIC_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address
340 TERM2IIC_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable
341 TERM2IIC_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
345 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
346 SD_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
347 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
348 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
349 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
352 UCB0STATW .equ eUSCI_B0_SFR + 08h ; eUSCI_B0 Status words