1 ; MSP430fr2x4x.inc : MSP430FR2xxx and MSP430FR4xxx declarations
4 .IF DEVICE = "MSP430FR2433"
6 ; ----------------------------------------------------------------------
7 ; MSP430FR2433 Peripheral File Map
8 ; ----------------------------------------------------------------------
9 SFR_SFR .equ 0100h ; Special function
10 PMM_SFR .equ 0120h ; PMM
11 SYS_SFR .equ 0140h ; SYS
12 CS_SFR .equ 0180h ; Clock System
13 FRAM_SFR .equ 01A0h ; FRAM control
15 WDT_A_SFR .equ 01CCh ; Watchdog
16 PA_SFR .equ 0200h ; PORT1/2
17 PB_SFR .equ 0220h ; PORT3
24 eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
25 eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
26 eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
27 BACK_MEM_SFR .equ 0660h
28 ADC10_B_SFR .equ 0700h
31 ; ----------------------------------------------
32 ; MSP430FR2433 MEMORY MAP
33 ; ----------------------------------------------
34 ; 0000-0FFF = peripherals (4 KB)
35 ; 1000-17FF = ROM bootstrap loader BSL1 (2k)
36 ; 1800-19FF = info B (FRAM 512 B)
37 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
39 ; 2000-2FFF = RAM (4 KB)
41 ; C400-FF7F = code memory (FRAM 15232 B)
42 ; FF80-FFFF = interrupt vectors (FRAM 128 B)
43 ; FFC00-FFFFF = BSL2 (2k)
44 ; ----------------------------------------------
45 PAGESIZE .equ 512 ; MPU unit
46 ; ----------------------------------------------
48 ; ----------------------------------------------
51 ; ----------------------------------------------
53 ; ----------------------------------------------
55 INFOBSTART .equ 01800h
58 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
60 ; ----------------------------------------------
62 ; ----------------------------------------------
65 ; ----------------------------------------------
67 ; ----------------------------------------------
68 PROGRAMSTART .equ 0C400h ; Code space start
69 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
70 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
71 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked
72 BSL_SIG1 .equ 0FF84h ;
73 BSL_SIG2 .equ 0FF86h ;
74 JTAG_PASSWORD .equ 0FF88h ; 256 bits
75 INTVECT .equ 0FFDAh ; FFDA-FFFF
76 BSL_PASSWORD .equ 0FFE0h ; 256 bits
77 ; ----------------------------------------------
79 ; ----------------------------------------------
80 ; Interrupt Vectors and signatures - MSP430FR243x
81 ; ----------------------------------------------
84 ;;Start of JTAG and BSL signatures
85 ; .word 0 ; JTAG signature 1
86 ; .word 0 ; JTAG signature 2
87 ; .word 0 ; BSL signature 1
88 ; .word 0 ; BSL signature 2
90 .org INTVECT ; FFDA-FFFF 18 vectors + reset
92 .word reset ; FFDAh - P2
93 .word reset ; FFDCh - P1
94 .word reset ; FFDEh - ADC10
95 .word reset ; FFE0h - eUSCI_B0
96 .word reset ; FFE2h - eUSCI_A1
97 TERMVEC .word TERMINAL_INT ; FFE4h - eUSCI_A0
98 .word reset ; FFE6h - WDT
99 .word reset ; FFE8h - RTC
100 .word reset ; FFEAh - TA3_x
101 .word reset ; FFECh - TA3_0
102 .word reset ; FFEEh - TA2_x
103 .word reset ; FFF0h - TA2_0
104 .word reset ; FFF2h - TA1_x
105 .word reset ; FFF4h - TA1_0
106 .word reset ; FFF6h - TA0_x
107 .word reset ; FFF8h - TA0_0
108 .word reset ; FFFAh - UserNMI
109 .word reset ; FFFCh - SysNMI
110 RST_ADR .word reset ; FFFEh - Reset
112 ; ----------------------------------------------------------------------
114 ; ----------------------------------------------------------------------
116 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
117 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
118 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
119 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
120 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
121 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
122 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
123 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
124 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
125 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
126 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
127 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
128 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
129 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
130 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
131 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
132 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
133 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
134 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
135 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
136 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
137 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
138 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
141 .ENDIF ; MSP430FR2433
145 .IF DEVICE = "MSP430FR4133"
147 ; ----------------------------------------------------------------------
148 ; EXP430FR4133 Peripheral File Map
149 ; ----------------------------------------------------------------------
150 SFR_SFR .set 0100h ; Special function
151 PMM_SFR .set 0120h ; PMM
152 SYS_SFR .set 0140h ; SYS
153 CS_SFR .set 0180h ; Clock System
154 FRAM_SFR .set 01A0h ; FRAM control
156 WDT_A_SFR .set 01CCh ; Watchdog
157 PA_SFR .set 0200h ; PORT1/2
158 PB_SFR .set 0220h ; PORT3/4
159 PC_SFR .set 0240h ; PORT5/6
160 PD_SFR .set 0260h ; PORT7/8
161 CTIO0_SFR .set 02E0h ; Capacitive Touch IO
165 eUSCI_A0_SFR .set 0500h ; eUSCI_A0
166 eUSCI_B0_SFR .set 0540h ; eUSCI_B0
168 BACK_MEM_SFR .set 0660h
169 ADC10_B_SFR .equ 0700h
171 ; ----------------------------------------------
172 ; MSP430FR4133 MEMORY MAP
173 ; ----------------------------------------------
174 ; 0000-0FFF = peripherals (4 KB)
175 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
176 ; 1800-19FF = info B (FRAM 512 B)
177 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
179 ; 2000-27FF = RAM (2 KB)
181 ; C400-FF7F = code memory (FRAM 15232 B)
182 ; FF80-FFFF = interrupt vectors (FRAM 128 B)
183 ; ----------------------------------------------
184 PAGESIZE .equ 512 ; MPU unit
185 ; ----------------------------------------------
187 ; ----------------------------------------------
188 INFOSTART .equ 01800h
189 INFOBSTART .equ 01800h
192 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
194 ; ----------------------------------------------
196 ; ----------------------------------------------
199 ; ----------------------------------------------
201 ; ----------------------------------------------
202 PROGRAMSTART .equ 0C400h ; Code space start
203 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
204 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
205 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked
206 BSL_SIG1 .equ 0FF84h ;
207 BSL_SIG2 .equ 0FF86h ;
208 JTAG_PASSWORD .equ 0FF88h ; 256 bits
209 INTVECT .equ 0FFE2h ; FFE2-FFFF
210 BSL_PASSWORD .equ 0FFE0h ; 256 bits
211 ; ----------------------------------------------
212 ; ----------------------------------------------
213 ; Interrupt Vectors and signatures - MSP430FR4133
214 ; ----------------------------------------------
217 ;;Start of JTAG and BSL signatures
218 ; .word 0 ; JTAG signature 1
219 ; .word 0 ; JTAG signature 2
220 ; .word 0 ; BSL signature 1
221 ; .word 0 ; BSL signature 2
223 .org INTVECT ; FFE2-FFFF 14 vectors + reset
225 .word reset ; FFE2h - LCD
226 .word reset ; FFE4h - P2
227 .word reset ; FFE6h - P1
228 .word reset ; FFE8h - ADC10
229 .word reset ; FFEAh - eUSCI_B0
230 TERMVEC .word TERMINAL_INT ; FFECh - eUSCI_A0
231 .word reset ; FFEEh - WDT
232 .word reset ; FFF0h - RTC
233 .word reset ; FFF2h - TA1_x
234 .word reset ; FFF4h - TA1_0
235 .word reset ; FFF6h - TA0_x
236 .word reset ; FFF8h - TA0_0
237 .word reset ; FFFAh - UserNMI
238 .word reset ; FFFCh - SysNMI
239 RST_ADR .word reset ; FFFEh - Reset
242 ; ----------------------------------------------------------------------
243 ; POWER ON RESET AND INITIALIZATION : PORT3/4
244 ; ----------------------------------------------------------------------
247 PBIN .set PB_SFR + 00h ; Port B Input
248 PBOUT .set PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
249 PBDIR .set PB_SFR + 04h ; Port B Direction
250 PBREN .set PB_SFR + 06h ; Port B Resistor Enable
251 PBSEL0 .set PB_SFR + 0Ah ; Port B Selection 0
252 PBSEL1 .set PB_SFR + 0Ch ; Port B Selection 1
253 PBSELC .set PB_SFR + 16h ; Port B Complement Selection
255 P4IN .set PB_SFR + 01h ; Port 4 Input */
256 P4OUT .set PB_SFR + 03h ; Port 4 Output
257 P4DIR .set PB_SFR + 05h ; Port 4 Direction
258 P4REN .set PB_SFR + 07h ; Port 4 Resistor Enable
259 P4SEL0 .set PB_SFR + 0Bh ; Port 4 Selection 0
260 P4SEL1 .set PB_SFR + 0Dh ; Port 4 Selection 1
261 P4SELC .set PB_SFR + 17h ; Port 4 Complement Selection
264 ; ----------------------------------------------------------------------
265 ; POWER ON RESET AND INITIALIZATION : PORT5/6
266 ; ----------------------------------------------------------------------
269 PCIN .set PC_SFR + 00h ; Port C Input
270 PCOUT .set PC_SFR + 02h ; Port C Output 1/0 or pullup/pulldown resistor
271 PCDIR .set PC_SFR + 04h ; Port C Direction
272 PCREN .set PC_SFR + 06h ; Port C Resistor Enable
273 PCSEL0 .set PC_SFR + 0Ah ; Port C Selection 0
274 PCSEL1 .set PC_SFR + 0Ch ; Port C Selection 1
275 PCSELC .set PC_SFR + 16h ; Port C Complement Selection
277 P5IN .set PC_SFR + 00h ; Port 5 Input */
278 P5OUT .set PC_SFR + 02h ; Port 5 Output
279 P5DIR .set PC_SFR + 04h ; Port 5 Direction
280 P5REN .set PC_SFR + 06h ; Port 5 Resistor Enable
281 P5SEL0 .set PC_SFR + 0Ah ; Port 5 Selection 0
282 P5SEL1 .set PC_SFR + 0Ch ; Port 5 Selection 1
283 P5SELC .set PC_SFR + 16h ; Port 5 Complement Selection
285 P6IN .set PC_SFR + 01h ; Port 6 Input */
286 P6OUT .set PC_SFR + 03h ; Port 6 Output
287 P6DIR .set PC_SFR + 05h ; Port 6 Direction
288 P6REN .set PC_SFR + 07h ; Port 6 Resistor Enable
289 P6SEL0 .set PC_SFR + 0Bh ; Port 6 Selection 0
290 P6SEL1 .set PC_SFR + 0Dh ; Port 6 Selection 1
291 P6SELC .set PC_SFR + 17h ; Port 6 Complement Selection
293 ; ----------------------------------------------------------------------
294 ; POWER ON RESET AND INITIALIZATION : PORT7/8
295 ; ----------------------------------------------------------------------
298 PDIN .set PD_SFR + 00h ; Port D Input
299 PDOUT .set PD_SFR + 02h ; Port D Output 1/0 or pullup/pulldown resistor
300 PDDIR .set PD_SFR + 04h ; Port D Direction
301 PDREN .set PD_SFR + 06h ; Port D Resistor Enable
302 PDSEL0 .set PD_SFR + 0Ah ; Port D Selection 0
303 PDSEL1 .set PD_SFR + 0Ch ; Port D Selection 1
304 PDSELC .set PD_SFR + 16h ; Port D Complement Selection
306 P7IN .set PD_SFR + 00h ; Port 7 Input */
307 P7OUT .set PD_SFR + 02h ; Port 7 Output
308 P7DIR .set PD_SFR + 04h ; Port 7 Direction
309 P7REN .set PD_SFR + 06h ; Port 7 Resistor Enable
310 P7SEL0 .set PD_SFR + 0Ah ; Port 7 Selection 0
311 P7SEL1 .set PD_SFR + 0Ch ; Port 7 Selection 1
312 P7SELC .set PD_SFR + 16h ; Port 7 Complement Selection
314 P8IN .set PD_SFR + 01h ; Port 8 Input */
315 P8OUT .set PD_SFR + 03h ; Port 8 Output
316 P8DIR .set PD_SFR + 05h ; Port 8 Direction
317 P8REN .set PD_SFR + 07h ; Port 8 Resistor Enable
318 P8SEL0 .set PD_SFR + 0Bh ; Port 8 Selection 0
319 P8SEL1 .set PD_SFR + 0Dh ; Port 8 Selection 1
320 P8SELC .set PD_SFR + 17h ; Port 8 Complement Selection
322 .ENDIF ; MSP_EXP430FR4133
326 ;=======================================================================
328 ;=======================================================================
330 UCSWRST .equ 1 ; eUSCI Software Reset
331 UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
332 UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
333 UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
334 UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
336 ; ----------------------------------------------------------------------
337 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
338 ; ----------------------------------------------------------------------
342 PM5CTL0 .equ PMM_SFR + 10h ; Power mode 5 control register 0
343 LOCKLPM5 .equ 1 ; bit position
345 ; ----------------------------------------------------------------------
346 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
347 ; ----------------------------------------------------------------------
349 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
351 ; WDTCTL Control Bits
353 WDTHOLD .equ 0080h ; WDT - Timer hold
354 WDTCNTCL .equ 0008h ; WDT timer counter clear
357 ; ----------------------------------------------------------------------
358 ; POWER ON RESET AND INITIALIZATION : PORT1/2
359 ; ----------------------------------------------------------------------
361 PAIN .equ PA_SFR + 00h ; Port A Input
362 PAOUT .equ PA_SFR + 02h ; Port A Output
363 PADIR .equ PA_SFR + 04h ; Port A Direction
364 PAREN .equ PA_SFR + 06h ; Port A Resistor Enable
365 PASEL0 .equ PA_SFR + 0Ah ; Port A Selection 0
366 PASEL1 .equ PA_SFR + 0Ch ; Port A Selection 1
367 PASELC .equ PA_SFR + 16h ; Port A Complement Selection
368 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
369 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
370 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt Flag
372 P1IN .equ PA_SFR + 00h ; Port 1 Input
373 P1OUT .equ PA_SFR + 02h ; Port 1 Output
374 P1DIR .equ PA_SFR + 04h ; Port 1 Direction
375 P1REN .equ PA_SFR + 06h ; Port 1 Resistor Enable
376 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 Selection 0
377 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 Selection 1
378 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
379 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
380 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
381 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt Flag
383 P2IN .equ PA_SFR + 01h ; Port 2 Input
384 P2OUT .equ PA_SFR + 03h ; Port 2 Output
385 P2DIR .equ PA_SFR + 05h ; Port 2 Direction
386 P2REN .equ PA_SFR + 07h ; Port 2 Resistor Enable
387 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 Selection 0
388 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 Selection 1
389 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
390 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
391 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag
392 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
394 ; ----------------------------------------------------------------------
395 ; POWER ON RESET AND INITIALIZATION : PORT3
396 ; ----------------------------------------------------------------------
398 P3IN .equ PB_SFR + 00h ; Port 3 Input */
399 P3OUT .equ PB_SFR + 02h ; Port 3 Output
400 P3DIR .equ PB_SFR + 04h ; Port 3 Direction
401 P3REN .equ PB_SFR + 06h ; Port 3 Resistor Enable
402 P3SEL0 .equ PB_SFR + 0Ah ; Port 3 Selection 0
403 P3SEL1 .equ PB_SFR + 0Ch ; Port 3 Selection 1
405 ; ----------------------------------------------------------------------
407 ; ----------------------------------------------------------------------
409 FRCTL0 .equ FRAM_SFR + 00h ; FRAM Controller Control 0
410 FRCTL0_H .equ FRAM_SFR + 01h ; FRAM Controller Control 0 high byte
412 ; ----------------------------------------------------------------------
413 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
414 ; ----------------------------------------------------------------------
416 CSCTL0 .equ CS_SFR + 00h ; Clock System Control Register 0
417 CSCTL1 .equ CS_SFR + 02h ; Clock System Control Register 1
418 CSCTL2 .equ CS_SFR + 04h ; Clock System Control Register 2
419 CSCTL3 .equ CS_SFR + 06h ; Clock System Control Register 3
420 CSCTL4 .equ CS_SFR + 08h ; Clock System Control Register 4
421 CSCTL5 .equ CS_SFR + 0Ah ; Clock System Control Register 5
422 CSCTL6 .equ CS_SFR + 0Ch ; Clock System Control Register 6
423 CSCTL7 .equ CS_SFR + 0Eh ; Clock System Control Register 7
424 CSCTL8 .equ CS_SFR + 10h ; Clock System Control Register 8
428 ; ----------------------------------------------------------------------
430 ; ----------------------------------------------------------------------
431 RTC ; define type of RTC
432 RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control
433 RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector
434 RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo
435 RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter
437 ; ----------------------------------------------------------------------
439 ; ----------------------------------------------------------------------
442 TERMCTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
443 TERMBRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
444 TERMMCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
445 TERMRXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
446 TERMTXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
447 TERMIE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
448 TERMIFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
452 ; ----------------------------------------------------------------------
454 ; ----------------------------------------------------------------------
456 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
457 SD_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
458 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
459 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
460 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
463 ; ----------------------------------------------------------------------
464 ; POWER ON RESET SYS config
465 ; ----------------------------------------------------------------------
466 SYSCTL .equ SYS_SFR + 00h ; System control
467 SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area
468 SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control
469 SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0
470 SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1
471 SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0
472 SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1
473 SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator
474 SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator
475 SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator
476 SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator
477 SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0
478 SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1
479 SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2