2 ; MSP430FR569 minimal declarations for FastForth usage
3 DEVICE = "MSP430FR5969"
5 ; ----------------------------------------------
6 ; MSP430FR5969 MEMORY MAP
7 ; ----------------------------------------------
8 ; 0000-0FFF = peripherals (4 KB)
9 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
10 ; 1800-187F = FRAM info D (128 B)
11 ; 1880-18FF = FRAM info C (128 B)
12 ; 1900-197F = FRAM info B (128 B)
13 ; 1980-19FF = FRAM info A (128 B)
14 ; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
15 ; 1B00-1BFF = unused (256 B)
16 ; 1C00-23FF = RAM (2KB)
17 ; 23FF-43FF = unused (8kB)
18 ; 4400-FF7F = FRAM code memory (FRAM) (MSP430FR59x8/9)
19 ; 8000-FF7F = FRAM code memory (FRAM) (MSP430FR59x7/8/9)
20 ; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
21 ; 10000-13FFF = FRAM (MSP430FR59x9)
23 ; ----------------------------------------------
24 PAGESIZE .equ 512 ; MPU unit
25 ; ----------------------------------------------
27 ; ----------------------------------------------
29 ; ----------------------------------------------
30 ; FRAM ; INFO B, A, TLV
31 ; ----------------------------------------------
42 TLV_ORG .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
44 ; ----------------------------------------------
46 ; ----------------------------------------------
49 ; ----------------------------------------------
51 ; ----------------------------------------------
52 MAIN_ORG .equ 04400h ; Code space start
53 MAIN_LEN .equ 14000h ; 63 k FRAM
54 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
55 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
56 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
57 BSL_SIG1 .equ 0FF84h ;
58 BSL_SIG2 .equ 0FF86h ;
59 JTAG_PASSWORD .equ 0FF88h ; 256 bits max
60 IPE_SIG_VALID .equ 0FF88h ; one word
61 IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
62 VECT_ORG .equ 0FFCCh ; FFCC-FFFF
64 BSL_PASSWORD .equ 0FFE0h ; 256 bits
65 ; ----------------------------------------------
68 ;;Start of JTAG and BSL signatures
69 ; .word 0FFFFh ; JTAG signature 1
70 ; .word 0FFFFh ; JTAG signature 2
71 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
72 ; .word 0FFFFh ; BSL signature 2
74 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
76 ; .org INTVECT ; FFCC-FFFF 25 vectors + reset
77 ; .word reset ; $FFCC - AES
78 ; .word reset ; $FFCE - RTC_B
79 ; .word reset ; $FFD0 - I/O Port 4
80 ; .word reset ; $FFD2 - I/O Port 3
81 ; .word reset ; $FFD4 - TB2_1
82 ; .word reset ; $FFD6 - TB2_0
83 ; .word reset ; $FFD8 - I/O Port P2
84 ; .word reset ; $FFDA - TB1_1
85 ; .word reset ; $FFDC - TB1_0
86 ; .word reset ; $FFDE - I/O Port P1
89 ;; .org BSL_PASSWORD ;Start of BSL PASSWORD
90 ; .word reset ; $FFE0 - TA1_1
91 ; .word reset ; $FFE2 - TA1_0
92 ; .word reset ; $FFE4 - DMA
93 ; .word reset ; $FFE6 - eUSCI_A1
94 ; .word reset ; $FFE8 - TA0_1
95 ; .word reset ; $FFEA - TA0_0
96 ; .word reset ; $FFEC - ADC12_B
97 ; .word reset ; $FFEE - eUSCI_B0
98 ; .word reset ; $FFF0 - eUSCI_A0
99 ; .word reset ; $FFF2 - Watchdog
100 ; .word reset ; $FFF4 - TB0_1
101 ; .word reset ; $FFF6 - TB0_0
102 ; .word reset ; $FFF8 - COMP_D
103 ; .word reset ; $FFFA - userNMI
104 ; .word reset ; $FFFC - sysNMI
105 ; .word reset ; $FFFE - reset
110 ; ----------------------------------------------------------------------
111 ; MSP430FR5969 Peripheral File Map
112 ; ----------------------------------------------------------------------
113 SFR_SFR .set 0100h ; Special function
114 PMM_SFR .set 0120h ; PMM
115 FRAM_SFR .set 0140h ; FRAM control
117 WDT_A_SFR .set 015Ch ; Watchdog
118 CS_SFR .set 0160h ; Clock System
119 SYS_SFR .set 0180h ; SYS
120 REF_SFR .set 01B0h ; REF
121 PA_SFR .set 0200h ; PORT1/2
122 PB_SFR .set 0220h ; PORT3/4
123 PJ_SFR .set 0320h ; PORTJ
128 CTIO0_SFR .set 0430h ; Capacitive Touch IO
130 CTIO1_SFR .set 0470h ; Capacitive Touch IO
133 DMA_CTRL_SFR .set 0500h
134 DMA_CHN0_SFR .set 0510h
135 DMA_CHN1_SFR .set 0520h
136 DMA_CHN2_SFR .set 0530h
137 MPU_SFR .set 05A0h ; memory protect unit
138 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
139 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
140 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
141 ADC12_B_SFR .set 0800h
142 COMP_E_SFR .set 08C0h
145 ; ----------------------------------------------------------------------
146 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
147 ; ----------------------------------------------------------------------
151 PM5CTL0 .set PMM_SFR + 10h ; Power mode 5 control register 0
154 ; ----------------------------------------------------------------------
156 ; ----------------------------------------------------------------------
157 FRCTL0 .set FRAM_SFR + 00h ; FRAM Controller Control 0
158 FRCTL0_H .set FRAM_SFR + 01h ; FRAM Controller Control 0 high byte
160 ; ----------------------------------------------------------------------
161 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
162 ; ----------------------------------------------------------------------
164 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
166 ; WDTCTL Control Bits
168 WDTHOLD .equ 0080h ; WDT - Timer hold
169 WDTCNTCL .equ 0008h ; WDT timer counter clear
171 ; ----------------------------------------------------------------------
172 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
173 ; ----------------------------------------------------------------------
175 CSCTL0 .equ CS_SFR + 00h ; CS Control Register 0
176 CSCTL0_H .equ CS_SFR + 01h ; CS Control Register 0 high byte
177 CSCTL1 .equ CS_SFR + 02h ; CS Control Register 1
178 CSCTL2 .equ CS_SFR + 04h ; CS Control Register 2
179 CSCTL3 .equ CS_SFR + 06h ; CS Control Register 3
181 ; CSCTL0 Control Bits
182 CSKEY .equ 0A5h ; CS Password
183 ; CSCTL1 Control Bits
185 DCOFSEL0 .equ 0002h ; DCO frequency select Bit: 0
186 DCOFSEL1 .equ 0004h ; DCO frequency select Bit: 1
187 DCOFSEL2 .equ 0008h ; DCO frequency select Bit: 2
188 DCOFSEL3 .equ 000Ch ; DCO frequency select Bit: 21
189 ; CSCTL2 Control Bits
190 SELA_LFXCLK .equ 0000h ; 0 : ACLK Source Select LFXCLK
191 SELA_VLOCLK .equ 0100h ; 1 ACLK Source Select VLOCLK 10kHz
192 SELS_DCOCLK .equ 0030h ; 3 : SMCLK Source Select DCOCLK
193 SELM_DCOCLK .equ 0003h ; 3 : MCLK Source Select DCOCLK
194 ; CSCTL3 Control Bits
195 DIVA_0 .equ 0000h ; ACLK Source Divider 0
196 DIVS_0 .equ 0000h ; SMCLK Source Divider 0
197 DIVM_0 .equ 0000h ; MCLK Source Divider 0
198 DIVA_2 .equ 0100h ; ACLK Source Divider 0
199 DIVS_2 .equ 0010h ; SMCLK Source Divider 0
200 DIVM_2 .equ 0001h ; MCLK Source Divider 0
201 DIVA_4 .equ 0200h ; ACLK Source Divider 0
202 DIVS_4 .equ 0020h ; SMCLK Source Divider 0
203 DIVM_4 .equ 0002h ; MCLK Source Divider 0
204 DIVA_8 .equ 0300h ; ACLK Source Divider 0
205 DIVS_8 .equ 0030h ; SMCLK Source Divider 0
206 DIVM_8 .equ 0003h ; MCLK Source Divider 0
207 DIVA_16 .equ 0400h ; ACLK Source Divider 0
208 DIVS_16 .equ 0040h ; SMCLK Source Divider 0
209 DIVM_16 .equ 0004h ; MCLK Source Divider 0
210 DIVA_32 .equ 0500h ; ACLK Source Divider 0
211 DIVS_32 .equ 0050h ; SMCLK Source Divider 0
212 DIVM_32 .equ 0005h ; MCLK Source Divider 0
214 ; ----------------------------------------------------------------------
215 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
216 ; ----------------------------------------------------------------------
217 SYSUNIV .equ SYS_SFR + 001Ah
218 SYSSNIV .equ SYS_SFR + 001Ch
219 SYSRSTIV .equ SYS_SFR + 001Eh
221 ; ----------------------------------------------------------------------
222 ; POWER ON RESET AND INITIALIZATION : REF
223 ; ----------------------------------------------------------------------
225 REFCTL equ REF_SFR + 00h ; REF Shared Reference control register 0
227 ; REFCTL0 Control Bits
228 REFON equ 0001h ; REF Reference On
229 REFTCOFF equ 0008h ; REF Temp.Sensor off
231 ; ----------------------------------------------------------------------
232 ; POWER ON RESET AND INITIALIZATION : PORT1/2
233 ; ----------------------------------------------------------------------
235 PAIN .equ PA_SFR + 00h ; Port A INput
236 PAOUT .equ PA_SFR + 02h ; Port A OUTput
237 PADIR .equ PA_SFR + 04h ; Port A DIRection
238 PAREN .equ PA_SFR + 06h ; Port A Resistor ENable
239 PASEL0 .equ PA_SFR + 0Ah ; Port A SELection 0
240 PASEL1 .equ PA_SFR + 0Ch ; Port A SELection 1
241 PASELC .equ PA_SFR + 16h ; Port A SELection Complement
242 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
243 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
244 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt FlaG
246 P1IN .equ PA_SFR + 00h ; Port 1 INput
247 P1OUT .equ PA_SFR + 02h ; Port 1 OUTput
248 P1DIR .equ PA_SFR + 04h ; Port 1 DIRection
249 P1REN .equ PA_SFR + 06h ; Port 1 Resistor ENable
250 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 SELection 0
251 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 SELection 1
252 P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement
253 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
254 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
255 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG
256 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
258 P2IN .equ PA_SFR + 01h ; Port 2 INput
259 P2OUT .equ PA_SFR + 03h ; Port 2 OUTput
260 P2DIR .equ PA_SFR + 05h ; Port 2 DIRection
261 P2REN .equ PA_SFR + 07h ; Port 2 Resistor ENable
262 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 SELection 0
263 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 SELection 1
264 P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement
265 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
266 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
267 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt FlaG
268 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
270 ; ----------------------------------------------------------------------
271 ; POWER ON RESET AND INITIALIZATION : PORT3/4
272 ; ----------------------------------------------------------------------
274 PBIN .equ PB_SFR + 00h ; Port B Input
275 PBOUT .equ PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
276 PBDIR .equ PB_SFR + 04h ; Port B Direction
277 PBREN .equ PB_SFR + 06h ; Port B Resistor Enable
278 PBSEL0 .equ PB_SFR + 0Ah ; Port B Selection 0
279 PBSEL1 .equ PB_SFR + 0Ch ; Port B Selection 1
280 PBSELC .equ PB_SFR + 16h ; Port B Complement Selection
281 PBIES .equ PB_SFR + 18h ; Port B Interrupt Edge Select
282 PBIE .equ PB_SFR + 1Ah ; Port B Interrupt Enable
283 PBIFG .equ PB_SFR + 1Ch ; Port B Interrupt Flag
285 P3IN .equ PB_SFR + 00h ; Port 3 Input */
286 P3OUT .equ PB_SFR + 02h ; Port 3 Output
287 P3DIR .equ PB_SFR + 04h ; Port 3 Direction
288 P3REN .equ PB_SFR + 06h ; Port 3 Resistor Enable
289 P3SEL0 .equ PB_SFR + 0Ah ; Port 3 Selection 0
290 P3SEL1 .equ PB_SFR + 0Ch ; Port 3 Selection 1
291 P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection
292 P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select
293 P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable
294 P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag
295 P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word
297 P4IN .equ PB_SFR + 01h ; Port 4 Input */
298 P4OUT .equ PB_SFR + 03h ; Port 4 Output
299 P4DIR .equ PB_SFR + 05h ; Port 4 Direction
300 P4REN .equ PB_SFR + 07h ; Port 4 Resistor Enable
301 P4SEL0 .equ PB_SFR + 0Bh ; Port 4 Selection 0
302 P4SEL1 .equ PB_SFR + 0Dh ; Port 4 Selection 1
303 P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection
304 P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select
305 P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable
306 P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag
307 P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word
309 ; ----------------------------------------------------------------------
310 ; POWER ON RESET AND INITIALIZATION : PORTJ
311 ; ----------------------------------------------------------------------
313 PJIN .equ PJ_SFR + 00h ; Port J INput
314 PJOUT .equ PJ_SFR + 02h ; Port J OUTput
315 PJDIR .equ PJ_SFR + 04h ; Port J DIRection
316 PJREN .equ PJ_SFR + 06h ; Port J Resistor ENable
317 PJSEL0 .equ PJ_SFR + 0Ah ; Port 2 SELection 0
318 PJSEL1 .equ PJ_SFR + 0Ch ; Port 2 SELection 1
319 PJSELC .equ PJ_SFR + 16h ; Port 2 SELection Complement; PJ 5-0 usage
321 ; ----------------------------------------------------------------------
323 ; ----------------------------------------------------------------------
324 RTCCTL01 .equ RTC_B_SFR + 00h
325 RTCCTL0 .equ RTC_B_SFR + 00h
326 RTCCTL1 .equ RTC_B_SFR + 01h
327 RTCCTL23 .equ RTC_B_SFR + 02h
328 RTCPS0CTL .equ RTC_B_SFR + 08h
329 RTCPS1CTL .equ RTC_B_SFR + 0Ah
330 RTCPS .equ RTC_B_SFR + 0Ch
331 RTCIV .equ RTC_B_SFR + 0Eh
332 RTCSEC .equ RTC_B_SFR + 10h
333 RTCMIN .equ RTC_B_SFR + 11h
334 RTCHOUR .equ RTC_B_SFR + 12h
335 RTCDOW .equ RTC_B_SFR + 13h
336 RTCDAY .equ RTC_B_SFR + 14h
337 RTCMON .equ RTC_B_SFR + 15h
338 RTCYEAR .equ RTC_B_SFR + 16h
343 ; ----------------------------------------------------------------------
345 ; ----------------------------------------------------------------------
347 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
348 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
349 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
350 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
351 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
352 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
353 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
354 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
355 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
356 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
357 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
358 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
359 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
360 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
361 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
362 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
363 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
364 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
365 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
366 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
367 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
368 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
369 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
372 MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0
373 MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1
374 MPUSEGB2 .equ MPU_SFR + 04h ; MPU Segmentation Border 2
375 MPUSEGB1 .equ MPU_SFR + 06h ; MPU Segmentation Border 1
376 MPUSAM .equ MPU_SFR + 08h ; MPU access management
377 MPUIPC0 .equ MPU_SFR + 0Ah ; MPU IP control 0
378 MPUIPSEGB2 .equ MPU_SFR + 0Ch ; MPU IP Encapsulation Segment Border 2
379 MPUIPSEGB1 .equ MPU_SFR + 0Eh ; MPU IP Encapsulation Segment Border 1
382 UCSWRST .equ 1 ; eUSCI Software Reset
383 UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
384 UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
385 UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
386 UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
389 ; ----------------------------------------------------------------------
391 ; ----------------------------------------------------------------------
394 TERM_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
395 TERM_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
396 TERM_MCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
397 TERM_STATW .equ eUSCI_A0_SFR + 0Ah ; eUSCI_A0 status Word Register
398 TERM_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
399 TERM_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
400 TERM_IE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
401 TERM_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
402 TERM_VEC .equ 0FFF0h ; interrupt vector for eUSCI_A0
406 SD_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
407 SD_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
408 SD_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer 8
409 SD_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer 8
410 SD_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
413 ; ----------------------------------------------------------------------
415 ; ----------------------------------------------------------------------
418 TERM_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
419 TERM_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
420 TERM_MCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
421 TERM_STATW .equ eUSCI_A1_SFR + 0Ah ; eUSCI_A1 status Word Register
422 TERM_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
423 TERM_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
424 TERM_IE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
425 TERM_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
426 TERM_VEC .equ 0FFE6h ; interrupt vector for eUSCI_A1
430 SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
431 SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
432 SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
433 SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
434 SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
438 ; ----------------------------------------------------------------------
440 ; ----------------------------------------------------------------------
442 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; eUSCI_B0 Control Word Register 0
443 SD_BRW .equ eUSCI_B0_SFR + 06h ; eUSCI_B0 Baud Word Rate 0
444 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; eUSCI_B0 Receive Buffer 8
445 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; eUSCI_B0 Transmit Buffer 8
446 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; eUSCI_B0 Interrupt Flags Register