1 ; MSP430FR5x6x.inc : MSP430FR5xxx and MSP430FR6xxx declarations (MSP430FR57xx excluded)
4 .IF DEVICE = "MSP430FR5948"
6 ; ----------------------------------------------------------------------
7 ; MSP430FR5948 Peripheral File Map
8 ; ----------------------------------------------------------------------
9 SFR_SFR .set 0100h ; Special function
10 PMM_SFR .set 0120h ; PMM
11 FRAM_SFR .set 0140h ; FRAM control
13 WDT_A_SFR .set 015Ch ; Watchdog
14 CS_SFR .set 0160h ; Clock System
15 SYS_SFR .set 0180h ; SYS
16 REF_SFR .set 01B0h ; REF
17 PA_SFR .set 0200h ; PORT1/2
18 PB_SFR .set 0220h ; PORT3/4
19 PJ_SFR .set 0320h ; PORTJ
24 CTIO0_SFR .set 0430h ; Capacitive Touch IO
26 CTIO1_SFR .set 0470h ; Capacitive Touch IO
29 DMA_CTRL_SFR .set 0500h
30 DMA_CHN0_SFR .set 0510h
31 DMA_CHN1_SFR .set 0520h
32 DMA_CHN2_SFR .set 0530h
33 MPU_SFR .set 05A0h ; memory protect unit
34 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
35 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
36 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
37 ADC12_B_SFR .set 0800h
41 ; ----------------------------------------------
42 ; MSP430FR5948 MEMORY MAP
43 ; ----------------------------------------------
44 ; 0000-0FFF = peripherals (4 KB)
45 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
46 ; 1800-187F = FRAM info D (128 B)
47 ; 1880-18FF = FRAM info C (128 B)
48 ; 1900-197F = FRAM info B (128 B)
49 ; 1980-19FF = FRAM info A (128 B)
50 ; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
51 ; 1B00-1BFF = unused (256 B)
52 ; 1C00-23FF = RAM (2KB)
53 ; 23FF-43FF = unused (8kB)
54 ; 4400-FF7F = FRAM code memory (FRAM) (MSP430FR59x8/9)
55 ; 8000-FF7F = FRAM code memory (FRAM) (MSP430FR59x7/8/9)
56 ; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
58 ; ----------------------------------------------
59 PAGESIZE .equ 512 ; MPU unit
60 ; ----------------------------------------------
62 ; ----------------------------------------------
64 ; ----------------------------------------------
65 ; FRAM ; INFO B, A, TLV
66 ; ----------------------------------------------
68 INFODSTART .equ 01800h
70 INFOCSTART .equ 01880h
72 INFOBSTART .equ 01900h
74 INFOASTART .equ 01980h
76 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
78 ; ----------------------------------------------
80 ; ----------------------------------------------
83 ; ----------------------------------------------
85 ; ----------------------------------------------
86 PROGRAMSTART .equ 04400h ; Code space start
87 FRAMEND .equ 0FFFFh ; 48 k FRAM
88 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
89 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
90 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
91 BSL_SIG1 .equ 0FF84h ;
92 BSL_SIG2 .equ 0FF86h ;
93 JTAG_PASSWORD .equ 0FF88h ; 256 bits max
94 IPE_SIG_VALID .equ 0FF88h ; one word
95 IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
96 INTVECT .equ 0FFCCh ; FFCC-FFFF
97 BSL_PASSWORD .equ 0FFE0h ; 256 bits
98 ; ----------------------------------------------
100 ;;Start of JTAG and BSL signatures
101 ; .word 0 ; JTAG signature 1
102 ; .word 0 ; JTAG signature 2
103 ; .word 0;5555h ; BSL signature 1; disable BSL
104 ; .word 0 ; BSL signature 2
106 ; ----------------------------------------------
107 ; Interrupt Vectors and signatures - MSP430FR5948
108 ; ----------------------------------------------
110 .org INTVECT ; FFCC-FFFF 25 vectors + reset
111 .word reset ; $FFCC - AES
112 .word reset ; $FFCE - RTC_B
113 .word reset ; $FFD0 - I/O Port 4
114 .word reset ; $FFD2 - I/O Port 3
115 .word reset ; $FFD4 - TB2_1
116 .word reset ; $FFD6 - TB2_0
117 .word reset ; $FFD8 - I/O Port P2
118 .word reset ; $FFDA - TB1_1
119 .word reset ; $FFDC - TB1_0
120 .word reset ; $FFDE - I/O Port P1
123 ; .org BSL_PASSWORD ;Start of BSL PASSWORD
124 .word reset ; $FFE0 - TA1_1
125 .word reset ; $FFE2 - TA1_0
126 .word reset ; $FFE4 - DMA
127 .word reset ; $FFE6 - eUSCI_A1
128 .word reset ; $FFE8 - TA0_1
129 .word reset ; $FFEA - TA0_0
130 .word reset ; $FFEC - ADC12_B
131 .word reset ; $FFEE - eUSCI_B0
132 TERMVEC .word TERMINAL_INT ; $FFF0 - eUSCI_A0
133 .word reset ; $FFF2 - Watchdog
134 .word reset ; $FFF4 - TB0_1
135 .word reset ; $FFF6 - TB0_0
136 .word reset ; $FFF8 - COMP_D
137 .word reset ; $FFFA - userNMI
138 .word reset ; $FFFC - sysNMI
139 RST_ADR .word reset ; $FFFE - reset
142 ; ----------------------------------------------------------------------
143 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
144 ; ----------------------------------------------------------------------
145 RTCCTL01 .equ RTC_B_SFR + 00h
146 RTCCTL0 .equ RTC_B_SFR + 00h
147 RTCCTL1 .equ RTC_B_SFR + 01h
148 RTCCTL23 .equ RTC_B_SFR + 02h
149 RTCPS0CTL .equ RTC_B_SFR + 08h
150 RTCPS1CTL .equ RTC_B_SFR + 0Ah
151 RTCPS .equ RTC_B_SFR + 0Ch
152 RTCIV .equ RTC_B_SFR + 0Eh
153 RTCSEC .equ RTC_B_SFR + 10h
154 RTCMIN .equ RTC_B_SFR + 11h
155 RTCHOUR .equ RTC_B_SFR + 12h
156 RTCDOW .equ RTC_B_SFR + 13h
157 RTCDAY .equ RTC_B_SFR + 14h
158 RTCMON .equ RTC_B_SFR + 15h
159 RTCYEAR .equ RTC_B_SFR + 16h
165 .ENDIF ; MSP430FR5948
169 .IF DEVICE = "MSP430FR5969"
171 ; ----------------------------------------------------------------------
172 ; MSP430FR5969 Peripheral File Map
173 ; ----------------------------------------------------------------------
174 SFR_SFR .set 0100h ; Special function
175 PMM_SFR .set 0120h ; PMM
176 FRAM_SFR .set 0140h ; FRAM control
178 WDT_A_SFR .set 015Ch ; Watchdog
179 CS_SFR .set 0160h ; Clock System
180 SYS_SFR .set 0180h ; SYS
181 REF_SFR .set 01B0h ; REF
182 PA_SFR .set 0200h ; PORT1/2
183 PB_SFR .set 0220h ; PORT3/4
184 PJ_SFR .set 0320h ; PORTJ
189 CTIO0_SFR .set 0430h ; Capacitive Touch IO
191 CTIO1_SFR .set 0470h ; Capacitive Touch IO
194 DMA_CTRL_SFR .set 0500h
195 DMA_CHN0_SFR .set 0510h
196 DMA_CHN1_SFR .set 0520h
197 DMA_CHN2_SFR .set 0530h
198 MPU_SFR .set 05A0h ; memory protect unit
199 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
200 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
201 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
202 ADC12_B_SFR .set 0800h
203 COMP_E_SFR .set 08C0h
206 ; ----------------------------------------------
207 ; MSP430FR5969 MEMORY MAP
208 ; ----------------------------------------------
209 ; 0000-0FFF = peripherals (4 KB)
210 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
211 ; 1800-187F = FRAM info D (128 B)
212 ; 1880-18FF = FRAM info C (128 B)
213 ; 1900-197F = FRAM info B (128 B)
214 ; 1980-19FF = FRAM info A (128 B)
215 ; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
216 ; 1B00-1BFF = unused (256 B)
217 ; 1C00-23FF = RAM (2KB)
218 ; 23FF-43FF = unused (8kB)
219 ; 4400-FF7F = FRAM code memory (FRAM) (MSP430FR59x8/9)
220 ; 8000-FF7F = FRAM code memory (FRAM) (MSP430FR59x7/8/9)
221 ; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
222 ; 10000-13FFF = FRAM (MSP430FR59x9)
224 ; ----------------------------------------------
225 PAGESIZE .equ 512 ; MPU unit
226 ; ----------------------------------------------
228 ; ----------------------------------------------
230 ; ----------------------------------------------
231 ; FRAM ; INFO B, A, TLV
232 ; ----------------------------------------------
233 INFOSTART .equ 01800h
234 INFODSTART .equ 01800h
236 INFOCSTART .equ 01880h
238 INFOBSTART .equ 01900h
240 INFOASTART .equ 01980h
242 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
244 ; ----------------------------------------------
246 ; ----------------------------------------------
249 ; ----------------------------------------------
251 ; ----------------------------------------------
252 PROGRAMSTART .equ 04400h ; Code space start
253 FRAMEND .equ 0FFFFh ; 48 k FRAM
254 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
255 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
256 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
257 BSL_SIG1 .equ 0FF84h ;
258 BSL_SIG2 .equ 0FF86h ;
259 JTAG_PASSWORD .equ 0FF88h ; 256 bits max
260 IPE_SIG_VALID .equ 0FF88h ; one word
261 IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
262 INTVECT .equ 0FFCCh ; FFCC-FFFF
263 BSL_PASSWORD .equ 0FFE0h ; 256 bits
264 ; ----------------------------------------------
266 ;;Start of JTAG and BSL signatures
267 ; .word 0 ; JTAG signature 1
268 ; .word 0 ; JTAG signature 2
269 ; .word 0;5555h ; BSL signature 1, disable BSL
270 ; .word 0 ; BSL signature 2
272 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
274 .org INTVECT ; FFCC-FFFF 25 vectors + reset
275 .word reset ; $FFCC - AES
276 .word reset ; $FFCE - RTC_B
277 .word reset ; $FFD0 - I/O Port 4
278 .word reset ; $FFD2 - I/O Port 3
279 .word reset ; $FFD4 - TB2_1
280 .word reset ; $FFD6 - TB2_0
281 .word reset ; $FFD8 - I/O Port P2
282 .word reset ; $FFDA - TB1_1
283 .word reset ; $FFDC - TB1_0
284 .word reset ; $FFDE - I/O Port P1
287 ; .org BSL_PASSWORD ;Start of BSL PASSWORD
288 .word reset ; $FFE0 - TA1_1
289 .word reset ; $FFE2 - TA1_0
290 .word reset ; $FFE4 - DMA
291 .word reset ; $FFE6 - eUSCI_A1
292 .word reset ; $FFE8 - TA0_1
293 .word reset ; $FFEA - TA0_0
294 .word reset ; $FFEC - ADC12_B
295 .word reset ; $FFEE - eUSCI_B0
296 TERMVEC .word TERMINAL_INT ; $FFF0 - eUSCI_A0
297 .word reset ; $FFF2 - Watchdog
298 .word reset ; $FFF4 - TB0_1
299 .word reset ; $FFF6 - TB0_0
300 .word reset ; $FFF8 - COMP_D
301 .word reset ; $FFFA - userNMI
302 .word reset ; $FFFC - sysNMI
303 RST_ADR .word reset ; $FFFE - reset
305 ; ----------------------------------------------------------------------
306 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
307 ; ----------------------------------------------------------------------
308 RTCCTL01 .equ RTC_B_SFR + 00h
309 RTCCTL0 .equ RTC_B_SFR + 00h
310 RTCCTL1 .equ RTC_B_SFR + 01h
311 RTCCTL23 .equ RTC_B_SFR + 02h
312 RTCPS0CTL .equ RTC_B_SFR + 08h
313 RTCPS1CTL .equ RTC_B_SFR + 0Ah
314 RTCPS .equ RTC_B_SFR + 0Ch
315 RTCIV .equ RTC_B_SFR + 0Eh
316 RTCSEC .equ RTC_B_SFR + 10h
317 RTCMIN .equ RTC_B_SFR + 11h
318 RTCHOUR .equ RTC_B_SFR + 12h
319 RTCDOW .equ RTC_B_SFR + 13h
320 RTCDAY .equ RTC_B_SFR + 14h
321 RTCMON .equ RTC_B_SFR + 15h
322 RTCYEAR .equ RTC_B_SFR + 16h
327 .ENDIF ; MSP430FR5969
334 .IF DEVICE = "MSP430FR5994"
336 ; ----------------------------------------------------------------------
337 ; MSP430FR5994 Peripheral File Map
338 ; ----------------------------------------------------------------------
339 SFR_SFR .set 0100h ; Special function
340 PMM_SFR .set 0120h ; PMM
341 FRAM_SFR .set 0140h ; FRAM control
344 WDT_A_SFR .set 015Ch ; Watchdog
345 CS_SFR .set 0160h ; Clock System
346 SYS_SFR .set 0180h ; SYS
347 REF_SFR .set 01B0h ; REF
348 PA_SFR .set 0200h ; PORT1/2
349 PB_SFR .set 0220h ; PORT3/4
350 PC_SFR .set 0240h ; PORT3/4
351 PD_SFR .set 0260h ; PORT3/4
352 PJ_SFR .set 0320h ; PORTJ
357 CTIO0_SFR .set 0430h ; Capacitive Touch IO
359 CTIO1_SFR .set 0470h ; Capacitive Touch IO
362 DMA_CTRL_SFR .set 0500h
363 DMA_CHN0_SFR .set 0510h
364 DMA_CHN1_SFR .set 0520h
365 DMA_CHN2_SFR .set 0530h
366 DMA_CHN3_SFR .set 0540h
367 DMA_CHN4_SFR .set 0550h
368 DMA_CHN5_SFR .set 0560h
369 MPU_SFR .set 05A0h ; memory protect unit
370 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
371 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
372 eUSCI_A2_SFR .set 0600h ; eUSCI_A1
373 eUSCI_A3_SFR .set 0620h ; eUSCI_A1
374 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
375 eUSCI_B1_SFR .set 0680h ; eUSCI_B0
376 eUSCI_B2_SFR .set 06C0h ; eUSCI_B0
377 eUSCI_B3_SFR .set 0700h ; eUSCI_B0
379 ADC12_B_SFR .set 0800h
380 COMP_E_SFR .set 08C0h
385 ; ----------------------------------------------
386 ; MSP430FR5994 MEMORY MAP
387 ; ----------------------------------------------
388 ; 000A-001F = tiny RAM
389 ; 0020-0FFF = peripherals (4 KB)
390 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
391 ; 1800-187F = FRAM info D (128 B)
392 ; 1880-18FF = FRAM info C (128 B)
393 ; 1900-197F = FRAM info B (128 B)
394 ; 1980-19FF = FRAM info A (128 B)
395 ; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
396 ; 1B00-1BFF = unused (256 B)
397 ; 1C00-2BFF = RAM (4KB)
398 ; 2C00-3BFF = sharedRAM (4kB)
399 ; 4400-FF7F = FRAM code memory (FRAM) (MSP430FR59x8/9)
400 ; 8000-FF7F = FRAM code memory (FRAM) (MSP430FR59x7/8/9)
401 ; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
403 ; ----------------------------------------------
404 PAGESIZE .equ 512 ; MPU unit
405 ; ----------------------------------------------
407 ; ----------------------------------------------
409 ; ----------------------------------------------
410 ; FRAM ; INFO B, A, TLV
411 ; ----------------------------------------------
412 INFOSTART .equ 01800h
413 INFODSTART .equ 01800h
415 INFOCSTART .equ 01880h
417 INFOBSTART .equ 01900h
419 INFOASTART .equ 01980h
421 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
423 ; ----------------------------------------------
425 ; ----------------------------------------------
430 SharedRAMSTART .equ 02C00h
431 SharedRAMEND .equ 03BFFh
432 ; ----------------------------------------------
434 ; ----------------------------------------------
435 PROGRAMSTART .equ 04000h ; Code space start
436 FRAMEND .equ 043FFFh ; 256 k FRAM
437 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
438 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
439 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
440 BSL_SIG1 .equ 0FF84h ;
441 BSL_SIG2 .equ 0FF86h ;
442 JTAG_PASSWORD .equ 0FF88h ; 256 bits max
443 IPE_SIG_VALID .equ 0FF88h ; one word
444 IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
445 INTVECT .equ 0FFB4h ; FFB4-FFFF
446 BSL_PASSWORD .equ 0FFE0h ; 256 bits
447 ; ----------------------------------------------
449 ;;Start of JTAG and BSL signatures
450 ; .word 0 ; JTAG signature 1
451 ; .word 0 ; JTAG signature 2
452 ; .word 0;5555h ; BSL signature 1, disable BSL
453 ; .word 0 ; BSL signature 2
455 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
457 .org INTVECT ; FFB4-FFFF 37 vectors + reset
458 .word reset ; 0FFB4h - LEA_Vec
459 .word reset ; 0FFB6h - P8_Vec
460 .word reset ; 0FFB8h - P7_Vec
461 .word reset ; 0FFBAh - eUSCI_B3_Vec
462 .word reset ; 0FFBCh - eUSCI_B2_Vec
463 .word reset ; 0FFBEh - eUSCI_B1_Vec
464 .word reset ; 0FFC0h - eUSCI_A3_Vec
465 .word reset ; 0FFC2h - eUSCI_A2_Vec
466 .word reset ; 0FFC4h - P6_Vec
467 .word reset ; 0FFC6h - P5_Vec
468 .word reset ; 0FFC8h - TA4_x_Vec
469 .word reset ; 0FFCAh - TA4_0_Vec
470 .word reset ; 0FFCCh - AES_Vec
471 .word reset ; 0FFCEh - RTC_C_Vec
472 .word reset ; 0FFD0h - P4_Vec=
473 .word reset ; 0FFD2h - P3_Vec=
474 .word reset ; 0FFD4h - TA3_x_Vec
475 .word reset ; 0FFD6h - TA3_0_Vec
476 .word reset ; 0FFD8h - P2_Vec
477 .word reset ; 0FFDAh - TA2_x_Vec
478 .word reset ; 0FFDCh - TA2_0_Vec
479 .word reset ; 0FFDEh - P1_Vec=
480 ; .org BSL_PASSWORD ;Start of BSL PASSWORD
481 .word reset ; 0FFE0h - TA1_x_Vec
482 .word reset ; 0FFE2h - TA1_0_Vec
483 .word reset ; 0FFE4h - DMA_Vec
484 .word reset ; 0FFE6h - eUSCI_A1_Vec
485 .word reset ; 0FFE8h - TA0_x_Vec
486 .word reset ; 0FFEAh - TA0_0_Vec
487 .word reset ; 0FFECh - ADC12_B_Vec
488 .word reset ; 0FFEEh - eUSCI_B0_Vec
489 TERMVEC .word TERMINAL_INT ; 0FFF0h - eUSCI_A0_Vec
490 .word reset ; 0FFF2h - WDT_Vec
491 .word reset ; 0FFF4h - TB0_x_Vec
492 .word reset ; 0FFF6h - TB0_0_Vec
493 .word reset ; 0FFF8h - COMP_E_Vec
494 .word reset ; 0FFFAh - U_NMI_Vec
495 .word reset ; 0FFFCh - S_NMI_Vec
496 RST_ADR .word reset ; 0FFFEh - RST_Vec
499 ; ----------------------------------------------------------------------
500 ; POWER ON RESET AND INITIALIZATION : PORT5/6
501 ; ----------------------------------------------------------------------
503 PCIN .equ PC_SFR + 00h ; Port C Input
504 PCOUT .equ PC_SFR + 02h ; Port C Output
505 PCDIR .equ PC_SFR + 04h ; Port C Direction
506 PCREN .equ PC_SFR + 06h ; Port C Resistor Enable
507 PCSEL0 .equ PC_SFR + 0Ah ; Port C Selection 0
508 PCSEL1 .equ PC_SFR + 0Ch ; Port C Selection 1
509 PCSELC .equ PC_SFR + 16h ; Port C Complement Selection
510 PCIES .equ PC_SFR + 18h ; Port C Interrupt Edge Select
511 PCIE .equ PC_SFR + 1Ah ; Port C Interrupt Enable
512 PCIFG .equ PC_SFR + 1Ch ; Port C Interrupt Flag
514 P5IN .equ PC_SFR + 00h ; Port 5 Input
515 P5OUT .equ PC_SFR + 02h ; Port 5 Output
516 P5DIR .equ PC_SFR + 04h ; Port 5 Direction
517 P5REN .equ PC_SFR + 06h ; Port 5 Resistor Enable
518 P5SEL0 .equ PC_SFR + 0Ah ; Port 5 Selection 0
519 P5SEL1 .equ PC_SFR + 0Ch ; Port 5 Selection 1
520 P5IV .equ PC_SFR + 0Eh ; Port 5 Interrupt Vector word
521 P5SELC .set PC_SFR + 16h ; Port 5 Complement Selection
522 P5IES .equ PC_SFR + 18h ; Port 5 Interrupt Edge Select
523 P5IE .equ PC_SFR + 1Ah ; Port 5 Interrupt Enable
524 P5IFG .equ PC_SFR + 1Ch ; Port 5 Interrupt Flag
526 P6IN .equ PC_SFR + 01h ; Port 6 Input
527 P6OUT .equ PC_SFR + 03h ; Port 6 Output
528 P6DIR .equ PC_SFR + 05h ; Port 6 Direction
529 P6REN .equ PC_SFR + 07h ; Port 6 Resistor Enable
530 P6SEL0 .equ PC_SFR + 0Bh ; Port 6 Selection 0
531 P6SEL1 .equ PC_SFR + 0Dh ; Port 6 Selection 1
532 P6SELC .set PC_SFR + 17h ; Port 6 Complement Selection
533 P6IES .equ PC_SFR + 19h ; Port 6 Interrupt Edge Select
534 P6IE .equ PC_SFR + 1Bh ; Port 6 Interrupt Enable
535 P6IFG .equ PC_SFR + 1Dh ; Port 6 Interrupt Flag
536 P6IV .equ PC_SFR + 1Eh ; Port 6 Interrupt Vector word
538 ; ----------------------------------------------------------------------
539 ; POWER ON RESET AND INITIALIZATION : PORT7/8
540 ; ----------------------------------------------------------------------
542 PDIN .equ PD_SFR + 00h ; Port D Input
543 PDOUT .equ PD_SFR + 02h ; Port D Output
544 PDDIR .equ PD_SFR + 04h ; Port D Direction
545 PDREN .equ PD_SFR + 06h ; Port D Resistor Enable
546 PDSEL0 .equ PD_SFR + 0Ah ; Port D Selection 0
547 PDSEL1 .equ PD_SFR + 0Ch ; Port D Selection 1
548 PDSELC .equ PD_SFR + 16h ; Port D Complement Selection
549 PDIES .equ PD_SFR + 18h ; Port D Interrupt Edge Select
550 PDIE .equ PD_SFR + 1Ah ; Port D Interrupt Enable
551 PDIFG .equ PD_SFR + 1Ch ; Port D Interrupt Flag
553 P7IN .equ PD_SFR + 00h ; Port 7 Input
554 P7OUT .equ PD_SFR + 02h ; Port 7 Output
555 P7DIR .equ PD_SFR + 04h ; Port 7 Direction
556 P7REN .equ PD_SFR + 06h ; Port 7 Resistor Enable
557 P7SEL0 .equ PD_SFR + 0Ah ; Port 7 Selection 0
558 P7SEL1 .equ PD_SFR + 0Ch ; Port 7 Selection 1
559 P7IV .equ PD_SFR + 0Eh ; Port 7 Interrupt Vector word
560 P7SELC .set PD_SFR + 16h ; Port 7 Complement Selection
561 P7IES .equ PD_SFR + 18h ; Port 7 Interrupt Edge Select
562 P7IE .equ PD_SFR + 1Ah ; Port 7 Interrupt Enable
563 P7IFG .equ PD_SFR + 1Ch ; Port 7 Interrupt Flag
565 P8IN .equ PD_SFR + 01h ; Port 8 Input
566 P8OUT .equ PD_SFR + 03h ; Port 8 Output
567 P8DIR .equ PD_SFR + 05h ; Port 8 Direction
568 P8REN .equ PD_SFR + 07h ; Port 8 Resistor Enable
569 P8SEL0 .equ PD_SFR + 0Bh ; Port 8 Selection 0
570 P8SEL1 .equ PD_SFR + 0Dh ; Port 8 Selection 1
571 P8SELC .set PD_SFR + 16h ; Port 8 Complement Selection
572 P8IES .equ PD_SFR + 19h ; Port 8 Interrupt Edge Select
573 P8IE .equ PD_SFR + 1Bh ; Port 8 Interrupt Enable
574 P8IFG .equ PD_SFR + 1Dh ; Port 8 Interrupt Flag
575 P8IV .equ PD_SFR + 1Eh ; Port 8 Interrupt Vector word
577 ; ----------------------------------------------------------------------
578 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
579 ; ----------------------------------------------------------------------
580 RTCCTL0_L .set RTC_C_SFR + 00h
581 RTCCTL0_H .set RTC_C_SFR + 01h
582 RTCCTL1 .set RTC_C_SFR + 02h
583 RTCCTL3 .set RTC_C_SFR + 03h
584 RTCOCAL .set RTC_C_SFR + 04h
585 RTCTCMP .set RTC_C_SFR + 06h
586 RTCPS0CTL .set RTC_C_SFR + 08h
587 RTCPS1CTL .set RTC_C_SFR + 0Ah
588 RTCPS .set RTC_C_SFR + 0Ch ; = RT1PS:RT0PS
589 RTCIV .set RTC_C_SFR + 0Eh
590 RTCSEC .set RTC_C_SFR + 10h
591 RTCCNT1 .set RTC_C_SFR + 10h
592 RTCMIN .set RTC_C_SFR + 11h
593 RTCCNT2 .set RTC_C_SFR + 11h
594 RTCHOUR .set RTC_C_SFR + 12h
595 RTCCNT3 .set RTC_C_SFR + 12h
596 RTCDOW .set RTC_C_SFR + 13h
597 RTCCNT4 .set RTC_C_SFR + 13h
598 RTCDAY .set RTC_C_SFR + 14h
599 RTCMON .set RTC_C_SFR + 15h
600 RTCYEAR .set RTC_C_SFR + 16h
605 .ENDIF ; MSP_EXP430FR5994
610 .IF DEVICE = "MSP430FR6989"
612 ; ----------------------------------------------------------------------
613 ; EXP430FR6989 Peripheral File Map
614 ; ----------------------------------------------------------------------
615 SFR_SFR .set 0100h ; Special function
616 PMM_SFR .set 0120h ; PMM
617 FRAM_SFR .set 0140h ; FRAM control
619 RAMC_SFR .set 0158h ; RAM controller
620 WDT_A_SFR .set 015Ch ; Watchdog
621 CS_SFR .set 0160h ; Clock System
622 SYS_SFR .set 0180h ; SYS
623 REF_SFR .set 01B0h ; shared REF
624 PA_SFR .set 0200h ; PORT1/2
625 PB_SFR .set 0220h ; PORT3/4
626 PC_SFR .set 0240h ; PORT5/6
627 PD_SFR .set 0260h ; PORT7/8
628 PE_SFR .set 0280h ; PORT9/10
629 PJ_SFR .set 0320h ; PORTJ
634 CTIO0_SFR .set 0430h ; Capacitive Touch IO
636 CTIO1_SFR .set 0470h ; Capacitive Touch IO
639 DMA_CTRL_SFR .set 0500h
640 DMA_CHN0_SFR .set 0510h
641 DMA_CHN1_SFR .set 0520h
642 DMA_CHN2_SFR .set 0530h
643 MPU_SFR .set 05A0h ; memory protect unit
644 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
645 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
646 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
647 eUSCI_B1_SFR .set 0680h ; eUSCI_B1
648 ADC12_B_SFR .set 0800h
649 COMP_E_SFR .set 08C0h
654 ESI_RAM .set 0E00h ; 128 bytes
656 ; ----------------------------------------------
657 ; MSP430FR6989 MEMORY MAP
658 ; ----------------------------------------------
660 ; 0020-0FFF = peripherals (4 KB)
661 ; 1000-17FF = BootStrap Loader BSL0..3 (ROM 4x512 B)
662 ; 1800-187F = info D (FRAM 128 B)
663 ; 1880-18FF = info C (FRAM 128 B)
664 ; 1900-197F = info B (FRAM 128 B)
665 ; 1980-19FF = info A (FRAM 128 B)
666 ; 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
667 ; 1B00-1BFF = Boot memory (ROM 256 B)
668 ; 1C00-23FF = RAM (2 KB)
670 ; 4400-FF7F = code memory (FRAM 47999 B)
671 ; FF80-FFFF = interrupt vectors (FRAM 128 B)
673 ; ----------------------------------------------
674 PAGESIZE .equ 512 ; MPU unit
675 ; ----------------------------------------------
676 ; FRAM ; INFO{D,C,B,A},TLV
677 ; ----------------------------------------------
678 INFOSTART .equ 01800h
679 INFODSTART .equ 01800h
681 INFOCSTART .equ 01880h
683 INFOBSTART .equ 01900h
685 INFOASTART .equ 01980h
687 TLVSTAT .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
689 ; ----------------------------------------------
691 ; ----------------------------------------------
694 ; ----------------------------------------------
696 ; ----------------------------------------------
697 PROGRAMSTART .equ 04400h ; Code space start
698 SIGNATURES .equ 0FF80h ; JTAG, BSL and IP Encapsulation signatures 1 and 2
699 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
700 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
701 BSL_SIG1 .equ 0FF84h ;
702 BSL_SIG2 .equ 0FF86h ;
703 JTAG_PASSWORD .equ 0FF86h ; up to 0FFC5h : 256 bits
704 INTVECT .equ 0FFC6h ; FFC6-FFFF
705 BSL_PASSWORD .equ 0FFE0h ; up to 0FFFFh : 256 bits
706 ; ----------------------------------------------
707 ; ----------------------------------------------
708 ; Interrupt Vectors and signatures - MSP430FR6989
709 ; ----------------------------------------------
712 ;;Start of JTAG and BSL signatures
713 ; .word 0 ; JTAG signature 1
714 ; .word 0 ; JTAG signature 2
715 ; .word 0;5555h ; BSL signature 1, disable BSL
716 ; .word 0 ; BSL signature 2
718 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
720 .org INTVECT ; FFC6-FFFF 28 vectors + reset
721 .word reset ; $FFC6 - AES
722 .word reset ; $FFC8 - RTC_C
723 .word reset ; $FFCA - LCD_C
724 .word reset ; $FFCC - I/O Port 4
725 .word reset ; $FFCE - I/O Port 3
726 .word reset ; $FFD0 - TA3_x
727 .word reset ; $FFD2 - TA3_0
728 .word reset ; $FFD4 - I/O Port P2
729 .word reset ; $FFD6 - TA2_x
730 .word reset ; $FFD8 - TA2_0
731 .word reset ; $FFDA - I/O Port P1
732 .word reset ; $FFDC - TA1_x
733 .word reset ; $FFDE - TA1_0
734 ; .org BSL_PASSWORD ;Start of BSL PASSWORD
735 .word reset ; $FFE0 - DMA
736 .word reset ; $FFE2 - eUSCI_B1
737 TERMVEC .word TERMINAL_INT ; $FFE4 - eUSCI_A1
738 .word reset ; $FFE6 - TA0_x
739 .word reset ; $FFE8 - TA0_0
740 .word reset ; $FFEA - ADC12_B
741 .word reset ; $FFEC - eUSCI_B0
742 .word reset ; $FFEE - eUSCI_A0
743 .word reset ; $FFF0 - Extended Scan IF
744 .word reset ; $FFF2 - Watchdog
745 .word reset ; $FFF4 - TB0_x
746 .word reset ; $FFF6 - TB0_0
747 .word reset ; $FFF8 - COMP_E
748 .word reset ; $FFFA - userNMI
749 .word reset ; $FFFC - sysNMI
750 RST_ADR .word reset ; $FFFE - reset
752 ; ----------------------------------------------------------------------
753 ; POWER ON RESET AND INITIALIZATION : PORT5/6
754 ; ----------------------------------------------------------------------
756 PCIN .set PC_SFR + 00h ; Port C Input
757 PCOUT .set PC_SFR + 02h ; Port C Output 1/0 or pullup/pulldown resistor
758 PCDIR .set PC_SFR + 04h ; Port C Direction
759 PCREN .set PC_SFR + 06h ; Port C Resistor Enable
760 PCSEL0 .set PC_SFR + 0Ah ; Port C Selection 0
761 PCSEL1 .set PC_SFR + 0Ch ; Port C Selection 1
762 PCSELC .set PC_SFR + 16h ; Port C Complement Selection
764 P5IN .set PC_SFR + 00h ; Port 5 Input */
765 P5OUT .set PC_SFR + 02h ; Port 5 Output
766 P5DIR .set PC_SFR + 04h ; Port 5 Direction
767 P5REN .set PC_SFR + 06h ; Port 5 Resistor Enable
768 P5SEL0 .set PC_SFR + 0Ah ; Port 5 Selection 0
769 P5SEL1 .set PC_SFR + 0Ch ; Port 5 Selection 1
770 P5SELC .set PC_SFR + 16h ; Port 5 Complement Selection
772 P6IN .set PC_SFR + 01h ; Port 6 Input */
773 P6OUT .set PC_SFR + 03h ; Port 6 Output
774 P6DIR .set PC_SFR + 05h ; Port 6 Direction
775 P6REN .set PC_SFR + 07h ; Port 6 Resistor Enable
776 P6SEL0 .set PC_SFR + 0Bh ; Port 6 Selection 0
777 P6SEL1 .set PC_SFR + 0Dh ; Port 6 Selection 1
778 P6SELC .set PC_SFR + 17h ; Port 6 Complement Selection
780 ; ----------------------------------------------------------------------
781 ; POWER ON RESET AND INITIALIZATION : PORT7/8
782 ; ----------------------------------------------------------------------
784 PDIN .set PD_SFR + 00h ; Port D Input
785 PDOUT .set PD_SFR + 02h ; Port D Output 1/0 or pullup/pulldown resistor
786 PDDIR .set PD_SFR + 04h ; Port D Direction
787 PDREN .set PD_SFR + 06h ; Port D Resistor Enable
788 PDSEL0 .set PD_SFR + 0Ah ; Port D Selection 0
789 PDSEL1 .set PD_SFR + 0Ch ; Port D Selection 1
790 PDSELC .set PD_SFR + 16h ; Port D Complement Selection
792 P7IN .set PD_SFR + 00h ; Port 7 Input */
793 P7OUT .set PD_SFR + 02h ; Port 7 Output
794 P7DIR .set PD_SFR + 04h ; Port 7 Direction
795 P7REN .set PD_SFR + 06h ; Port 7 Resistor Enable
796 P7SEL0 .set PD_SFR + 0Ah ; Port 7 Selection 0
797 P7SEL1 .set PD_SFR + 0Ch ; Port 7 Selection 1
798 P7SELC .set PD_SFR + 16h ; Port 7 Complement Selection
800 P8IN .set PD_SFR + 01h ; Port 8 Input */
801 P8OUT .set PD_SFR + 03h ; Port 8 Output
802 P8DIR .set PD_SFR + 05h ; Port 8 Direction
803 P8REN .set PD_SFR + 07h ; Port 8 Resistor Enable
804 P8SEL0 .set PD_SFR + 0Bh ; Port 8 Selection 0
805 P8SEL1 .set PD_SFR + 0Dh ; Port 8 Selection 1
806 P8SELC .set PD_SFR + 17h ; Port 8 Complement Selection
808 ; ----------------------------------------------------------------------
809 ; POWER ON RESET AND INITIALIZATION : PORT9/10
810 ; ----------------------------------------------------------------------
812 PEIN .set PE_SFR + 00h ; Port E Input
813 PEOUT .set PE_SFR + 02h ; Port E Output 1/0 or pullup/pulldown resistor
814 PEDIR .set PE_SFR + 04h ; Port E Direction
815 PEREN .set PE_SFR + 06h ; Port E Resistor Enable
816 PESEL0 .set PE_SFR + 0Ah ; Port E Selection 0
817 PESEL1 .set PE_SFR + 0Ch ; Port E Selection 1
818 PESELC .set PE_SFR + 16h ; Port E Complement Selection
820 P9IN .set PE_SFR + 00h ; Port 9 Input */
821 P9OUT .set PE_SFR + 02h ; Port 9 Output
822 P9DIR .set PE_SFR + 04h ; Port 9 Direction
823 P9REN .set PE_SFR + 06h ; Port 9 Resistor Enable
824 P9SEL0 .set PE_SFR + 0Ah ; Port 9 Selection 0
825 P9SEL1 .set PE_SFR + 0Ch ; Port 9 Selection 1
826 P9SELC .set PE_SFR + 16h ; Port 9 Complement Selection
828 P10IN .set PE_SFR + 01h ; Port 10 Input */
829 P10OUT .set PE_SFR + 03h ; Port 10 Output
830 P10DIR .set PE_SFR + 05h ; Port 10 Direction
831 P10REN .set PE_SFR + 07h ; Port 10 Resistor Enable
832 P10SEL0 .set PE_SFR + 0Bh ; Port 10 Selection 0
833 P10SEL1 .set PE_SFR + 0Dh ; Port 10 Selection 1
834 P10SELC .set PE_SFR + 17h ; Port 10 Complement Selection
836 ; ----------------------------------------------------------------------
837 ; POWER ON RESET AND INITIALIZATION : RTC_C REGISTERS
838 ; ----------------------------------------------------------------------
839 RTCCTL0_L .set RTC_C_SFR + 00h
840 RTCCTL0_H .set RTC_C_SFR + 01h
841 RTCCTL1 .set RTC_C_SFR + 02h
842 RTCCTL3 .set RTC_C_SFR + 03h
843 RTCOCAL .set RTC_C_SFR + 04h
844 RTCTCMP .set RTC_C_SFR + 06h
845 RTCPS0CTL .set RTC_C_SFR + 08h
846 RTCPS1CTL .set RTC_C_SFR + 0Ah
847 RTCPS .set RTC_C_SFR + 0Ch ; = RT1PS:RT0PS
848 RTCIV .set RTC_C_SFR + 0Eh
849 RTCSEC .set RTC_C_SFR + 10h
850 RTCCNT1 .set RTC_C_SFR + 10h
851 RTCMIN .set RTC_C_SFR + 11h
852 RTCCNT2 .set RTC_C_SFR + 11h
853 RTCHOUR .set RTC_C_SFR + 12h
854 RTCCNT3 .set RTC_C_SFR + 12h
855 RTCDOW .set RTC_C_SFR + 13h
856 RTCCNT4 .set RTC_C_SFR + 13h
857 RTCDAY .set RTC_C_SFR + 14h
858 RTCMON .set RTC_C_SFR + 15h
859 RTCYEAR .set RTC_C_SFR + 16h
864 .ENDIF ; MSP430FR6989
872 ;=======================================================================
874 ;=======================================================================
876 UCSWRST .equ 1 ; eUSCI Software Reset
877 UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
878 UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
879 UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
880 UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
883 ; ----------------------------------------------------------------------
884 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
885 ; ----------------------------------------------------------------------
889 PM5CTL0 .set PMM_SFR + 10h ; Power mode 5 control register 0
892 ; ----------------------------------------------------------------------
893 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
894 ; ----------------------------------------------------------------------
896 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
898 ; WDTCTL Control Bits
900 WDTHOLD .equ 0080h ; WDT - Timer hold
901 WDTCNTCL .equ 0008h ; WDT timer counter clear
903 ; ----------------------------------------------------------------------
904 ; POWER ON RESET AND INITIALIZATION : PORT1/2
905 ; ----------------------------------------------------------------------
907 PAIN .equ PA_SFR + 00h ; Port A INput
908 PAOUT .equ PA_SFR + 02h ; Port A OUTput
909 PADIR .equ PA_SFR + 04h ; Port A DIRection
910 PAREN .equ PA_SFR + 06h ; Port A Resistor ENable
911 PASEL0 .equ PA_SFR + 0Ah ; Port A SELection 0
912 PASEL1 .equ PA_SFR + 0Ch ; Port A SELection 1
913 PASELC .equ PA_SFR + 16h ; Port A SELection Complement
914 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
915 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
916 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt FlaG
918 P1IN .equ PA_SFR + 00h ; Port 1 INput
919 P1OUT .equ PA_SFR + 02h ; Port 1 OUTput
920 P1DIR .equ PA_SFR + 04h ; Port 1 DIRection
921 P1REN .equ PA_SFR + 06h ; Port 1 Resistor ENable
922 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 SELection 0
923 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 SELection 1
924 P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement
925 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
926 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
927 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG
928 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
930 P2IN .equ PA_SFR + 01h ; Port 2 INput
931 P2OUT .equ PA_SFR + 03h ; Port 2 OUTput
932 P2DIR .equ PA_SFR + 05h ; Port 2 DIRection
933 P2REN .equ PA_SFR + 07h ; Port 2 Resistor ENable
934 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 SELection 0
935 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 SELection 1
936 P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement
937 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
938 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
939 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt FlaG
940 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
942 ; ----------------------------------------------------------------------
943 ; POWER ON RESET AND INITIALIZATION : PORT3/4
944 ; ----------------------------------------------------------------------
946 PBIN .equ PB_SFR + 00h ; Port B Input
947 PBOUT .equ PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
948 PBDIR .equ PB_SFR + 04h ; Port B Direction
949 PBREN .equ PB_SFR + 06h ; Port B Resistor Enable
950 PBSEL0 .equ PB_SFR + 0Ah ; Port B Selection 0
951 PBSEL1 .equ PB_SFR + 0Ch ; Port B Selection 1
952 PBSELC .equ PB_SFR + 16h ; Port B Complement Selection
953 PBIES .equ PB_SFR + 18h ; Port B Interrupt Edge Select
954 PBIE .equ PB_SFR + 1Ah ; Port B Interrupt Enable
955 PBIFG .equ PB_SFR + 1Ch ; Port B Interrupt Flag
957 P3IN .equ PB_SFR + 00h ; Port 3 Input */
958 P3OUT .equ PB_SFR + 02h ; Port 3 Output
959 P3DIR .equ PB_SFR + 04h ; Port 3 Direction
960 P3REN .equ PB_SFR + 06h ; Port 3 Resistor Enable
961 P3SEL0 .equ PB_SFR + 0Ah ; Port 3 Selection 0
962 P3SEL1 .equ PB_SFR + 0Ch ; Port 3 Selection 1
963 P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection
964 P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select
965 P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable
966 P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag
967 P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word
969 P4IN .equ PB_SFR + 01h ; Port 4 Input */
970 P4OUT .equ PB_SFR + 03h ; Port 4 Output
971 P4DIR .equ PB_SFR + 05h ; Port 4 Direction
972 P4REN .equ PB_SFR + 07h ; Port 4 Resistor Enable
973 P4SEL0 .equ PB_SFR + 0Bh ; Port 4 Selection 0
974 P4SEL1 .equ PB_SFR + 0Dh ; Port 4 Selection 1
975 P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection
976 P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select
977 P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable
978 P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag
979 P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word
981 ; ----------------------------------------------------------------------
982 ; POWER ON RESET AND INITIALIZATION : PORTJ
983 ; ----------------------------------------------------------------------
985 PJIN .equ PJ_SFR + 00h ; Port J INput
986 PJOUT .equ PJ_SFR + 02h ; Port J OUTput
987 PJDIR .equ PJ_SFR + 04h ; Port J DIRection
988 PJREN .equ PJ_SFR + 06h ; Port J Resistor ENable
989 PJSEL0 .equ PJ_SFR + 0Ah ; Port 2 SELection 0
990 PJSEL1 .equ PJ_SFR + 0Ch ; Port 2 SELection 1
991 PJSELC .equ PJ_SFR + 16h ; Port 2 SELection Complement; PJ 5-0 usage
993 ; ----------------------------------------------------------------------
995 ; ----------------------------------------------------------------------
996 FRCTL0 .set FRAM_SFR + 00h ; FRAM Controller Control 0
997 FRCTL0_H .set FRAM_SFR + 01h ; FRAM Controller Control 0 high byte
999 ; ----------------------------------------------------------------------
1000 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
1001 ; ----------------------------------------------------------------------
1003 CSCTL0 .equ CS_SFR + 00h ; CS Control Register 0
1004 CSCTL0_H .equ CS_SFR + 01h ; CS Control Register 0 high byte
1005 CSCTL1 .equ CS_SFR + 02h ; CS Control Register 1
1006 CSCTL2 .equ CS_SFR + 04h ; CS Control Register 2
1007 CSCTL3 .equ CS_SFR + 06h ; CS Control Register 3
1009 ; CSCTL0 Control Bits
1010 CSKEY .equ 0A5h ; CS Password
1011 ; CSCTL1 Control Bits
1013 DCOFSEL0 .equ 0002h ; DCO frequency select Bit: 0
1014 DCOFSEL1 .equ 0004h ; DCO frequency select Bit: 1
1015 DCOFSEL2 .equ 0008h ; DCO frequency select Bit: 2
1016 DCOFSEL3 .equ 000Ch ; DCO frequency select Bit: 21
1017 ; CSCTL2 Control Bits
1018 SELA_LFXCLK .equ 0000h ; 0 : ACLK Source Select LFXCLK
1019 SELA_VLOCLK .equ 0100h ; 1 ACLK Source Select VLOCLK 10kHz
1020 SELS_DCOCLK .equ 0030h ; 3 : SMCLK Source Select DCOCLK
1021 SELM_DCOCLK .equ 0003h ; 3 : MCLK Source Select DCOCLK
1022 ; CSCTL3 Control Bits
1023 DIVA_0 .equ 0000h ; ACLK Source Divider 0
1024 DIVS_0 .equ 0000h ; SMCLK Source Divider 0
1025 DIVM_0 .equ 0000h ; MCLK Source Divider 0
1026 DIVA_2 .equ 0100h ; ACLK Source Divider 0
1027 DIVS_2 .equ 0010h ; SMCLK Source Divider 0
1028 DIVM_2 .equ 0001h ; MCLK Source Divider 0
1029 DIVA_4 .equ 0200h ; ACLK Source Divider 0
1030 DIVS_4 .equ 0020h ; SMCLK Source Divider 0
1031 DIVM_4 .equ 0002h ; MCLK Source Divider 0
1032 DIVA_8 .equ 0300h ; ACLK Source Divider 0
1033 DIVS_8 .equ 0030h ; SMCLK Source Divider 0
1034 DIVM_8 .equ 0003h ; MCLK Source Divider 0
1035 DIVA_16 .equ 0400h ; ACLK Source Divider 0
1036 DIVS_16 .equ 0040h ; SMCLK Source Divider 0
1037 DIVM_16 .equ 0004h ; MCLK Source Divider 0
1038 DIVA_32 .equ 0500h ; ACLK Source Divider 0
1039 DIVS_32 .equ 0050h ; SMCLK Source Divider 0
1040 DIVM_32 .equ 0005h ; MCLK Source Divider 0
1042 ; ----------------------------------------------------------------------
1043 ; POWER ON RESET AND INITIALIZATION : REF
1044 ; ----------------------------------------------------------------------
1046 REFCTL equ REF_SFR + 00h ; REF Shared Reference control register 0
1048 ; REFCTL0 Control Bits
1049 REFON equ 0001h ; REF Reference On
1050 REFTCOFF equ 0008h ; REF Temp.Sensor off
1052 ; ----------------------------------------------------------------------
1054 ; ----------------------------------------------------------------------
1056 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
1057 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
1058 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
1059 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
1060 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
1061 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
1062 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
1063 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
1064 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
1065 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
1066 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
1067 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
1068 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
1069 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
1070 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
1071 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
1072 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
1073 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
1074 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
1075 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
1076 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
1077 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
1078 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
1081 ; ----------------------------------------------------------------------
1083 ; ----------------------------------------------------------------------
1086 TERMCTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
1087 TERMBRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
1088 TERMMCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
1089 TERMRXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
1090 TERMTXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
1091 TERMIE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
1092 TERMIFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
1096 SD_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
1097 SD_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
1098 SD_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer 8
1099 SD_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer 8
1100 SD_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
1103 ; ----------------------------------------------------------------------
1105 ; ----------------------------------------------------------------------
1108 TERMCTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
1109 TERMBRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
1110 TERMMCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
1111 TERMRXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
1112 TERMTXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
1113 TERMIE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
1114 TERMIFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
1118 SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
1119 SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
1120 SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
1121 SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
1122 SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
1126 ; ----------------------------------------------------------------------
1128 ; ----------------------------------------------------------------------
1130 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; eUSCI_B0 Control Word Register 0
1131 SD_BRW .equ eUSCI_B0_SFR + 06h ; eUSCI_B0 Baud Word Rate 0
1132 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; eUSCI_B0 Receive Buffer 8
1133 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; eUSCI_B0 Transmit Buffer 8
1134 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; eUSCI_B0 Interrupt Flags Register
1139 ; ----------------------------------------------------------------------
1140 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
1141 ; ----------------------------------------------------------------------
1143 SYSUNIV .equ SYS_SFR + 001Ah
1144 SYSSNIV .equ SYS_SFR + 001Ch
1145 SYSRSTIV .equ SYS_SFR + 001Eh