1 ; -*- coding: utf-8 -*-
3 ; Fast Forth For Texas Instrument MSP430FR5739
4 ; Tested on MSP-EXP430FR2433 launchpad
6 ; Copyright (C) <2017> <J.M. THOORENS>
8 ; This program is free software: you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
21 ; ======================================================================
22 ; INIT MSP-EXP430FR2433 board
23 ; ======================================================================
28 ; "TXD" <--- P1.4 == UCA0TXD <-- UCA0TXDBUf
29 ; "RXD" ---> P1.5 == UCA0RXD --> UCA0RXDBUF
68 ; ======================================================================
69 ; MSP-EXP430FR2433 LAUNCHPAD <--> OUTPUT WORLD
70 ; ======================================================================
72 ; +--4k7-< DeepRST switch <-- GND
74 ; P1.4 - UCA0 TXD J101.6 - <-+-> RX UARTtoUSB bridge
75 ; P1.5 - UCA0 RXD J101.8 - <---- TX UARTtoUSB bridge
76 ; P1.0 - RTS J1.2 - ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
77 ; P1.1 - CTS J2.19 - <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
79 ; P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Master_Slave
80 ; P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Master_Slave
82 ; P2.2 - ACLK J2.18 - <---- TSSOP32236 (IR RC5)
84 ; P2.0 - J2.11 - ----> SD_CS (Card Select)
85 ; P2.1 - J2.12 - <---- SD_CD (Card Detect)
86 ; P2.4 - UCA1 CLK J1.7 - ----> SD_CLK
87 ; P2.5 - UCA1 SOMI J2.14 - <---- SD_SDO
88 ; P2.6 - UCA1 SIMO J2.15 - ----> SD_SDI
90 ; P3.1 - J2.13 - ----> SCL I2C Soft_Master
91 ; P3.2 - J2.17 - <---> SDA I2C Soft_Master
94 ; P2.0 - J2.11 - <---- I2CTERM_SLA0
95 ; P2.1 - J2.12 - <---- I2CTERM_SLA1
96 ; P2.2 - ACLK J2.18 - <---- I2CTERM_SLA2
98 ; ----------------------------------------------------------------------
99 ; INIT order : WDT, GPIOs, FRAM, Clock, UARTs...
100 ; ----------------------------------------------------------------------
102 ; ----------------------------------------------------------------------
103 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
104 ; ----------------------------------------------------------------------
106 ; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
108 ; ----------------------------------------------------------------------
109 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
110 ; ----------------------------------------------------------------------
113 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
115 ; ----------------------------------------------------------------------
116 ; POWER ON RESET AND INITIALIZATION : I/O
117 ; ----------------------------------------------------------------------
119 ; ----------------------------------------------------------------------
120 ; POWER ON RESET AND INITIALIZATION : PORT1/2
121 ; ----------------------------------------------------------------------
123 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
129 ; P1.4 - TXD TERMINAL + DEEP_RST
130 ; P1.5 - RXD TERMINAL
131 ; P1.0 - RTS TERMINAL
132 ; P1.1 - CTS TERMINAL
136 TXD .equ 10h ; P1.4 = TXD + FORTH Deep_RST pin
145 SD_SEL .equ PASEL0 ; to configure UCA1
146 SD_REN .equ PAREN ; to configure pullup resistors
147 SD_BUS .equ 07000h ; pins P2.4 as UCA1CLK, P2.5 as UCA1SOMI & P2.6 as UCA1SIMO
150 ; P2.1 <--- SD_CD (Card Detect)
153 ; P2.0 ---> SD_CS (Card Select)
160 TXD .equ 40h ; P2.6 = TXD + FORTH Deep_RST pin
163 TERM_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
168 MOV #-1,&PAREN ; all inputs with pull resistors
169 MOV #00003h,&PADIR ; all pins as input else LED1/LED2 as output
170 MOV #0FFFCh,&PAOUT ; all pins with pullup resistors and LED1/LED2 = output low
172 .IFDEF TERMINAL4WIRES
173 ; RTS output is wired to the CTS input of UART2USB bridge
174 ; configure RTS as output high to disable RX TERM during start FORTH
175 HANDSHAKOUT .equ P1OUT
178 ; BIS.B #RTS,&P1DIR ; RTS as output high
179 BIS.B #RTS,&P1OUT ; RTS as output high
180 .IFDEF TERMINAL5WIRES
181 ; CTS input must be wired to the RTS output of UART2USB bridge
182 ; configure CTS as input low (true) to avoid lock when CTS is not wired
184 BIC.B #CTS,&P1DIR ; CTS input pulled down
185 ; BIC.B #CTS,&P1OUT ; CTS input pulled down
186 .ENDIF ; TERMINAL5WIRES
187 .ENDIF ; TERMINAL4WIRES
190 .IFDEF UCB0_TERM ; for MSP_EXP430FR2433_I2C
191 I2CM_BUS .equ 0Ch ; P1.2=SDA P1.3=SCL
197 .IFDEF UCB0_I2CM ; for TERM2IIC add-on
198 I2CT_BUS .equ 0Ch ; P1.2=SDA P1.3=SCL
204 I2CT_SLA_BUS .equ 07h ; P2.0 P2.1 P2.1
205 I2CT_SLA_IN .equ P2IN
206 I2CT_SLA_OUT .equ P2OUT
207 I2CT_SLA_DIR .equ P2DIR
208 I2CT_SLA_REN .equ P2REN
212 ; ----------------------------------------------------------------------
213 ; POWER ON RESET AND INITIALIZATION : PORT3
214 ; ----------------------------------------------------------------------
216 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
219 MOV.B #-1,&P3OUT ; OUT1 for all pins
220 BIS.B #-1,&P3REN ; all pins with pull resistors
223 ; ----------------------------------------------------------------------
225 ; ----------------------------------------------------------------------
228 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
229 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
230 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
233 ; ----------------------------------------------------------------------
234 ; POWER ON RESET SYS config
235 ; ----------------------------------------------------------------------
238 ; BIC #1,&SYSCFG0 ; enable write program in FRAM
239 MOV #0A500h,&SYSCFG0 ; enable write MAIN and INFO
241 ; ----------------------------------------------------------------------
242 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
243 ; ----------------------------------------------------------------------
245 ; CS code for EXP430FR2433
247 ; to measure REFO frequency, output ACLK on P2.2:
250 ; result : REFO = 32.69kHz
252 ; ===================================================================
253 ; need to adjust FLLN (and DCO) for each device of MSP430fr2xxx family ?
254 ; (no problem with MSP430FR5xxx families without FLL).
255 ; ===================================================================
257 ; .IF FREQUENCY = 0.5
259 ; MOV #0D6h,&CSCTL0 ; preset DCO = 0xD6 (measured value @ 0x180 ; to measure, type 0x180 @ U.)
261 ; MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
262 ;; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
263 ;; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh
264 ; ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz
265 ;; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh
266 ; ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz
267 ; MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
268 ; ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
269 ;; =====================================
272 ; .ELSEIF FREQUENCY = 1
274 ; MOV #00B4h,&CSCTL0 ; preset DCO = 0xB4 (measured value @ 0x180 ; to measure, type HEX 0x180 ?)
276 ; MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
277 ;; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
278 ;; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh
279 ; ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz
280 ; MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh
281 ; ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz
282 ;; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
283 ; ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
284 ;; =====================================
287 ; .ELSEIF FREQUENCY = 2
289 ; MOV #00B4h,&CSCTL0 ; preset DCO = 0xB4 (measured value @ 0x180 ; to measure, type HEX 0x180 ?)
291 ; MOV #0003h,&CSCTL1 ; Set 2MHZ DCORSEL,disable DCOFTRIM,Modulation
292 ;; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
293 ;; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh
294 ; ; fCOCLKDIV = 32768 x (59+1) = 1.996 MHz ; measured : MHz
295 ;; MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch
296 ; ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz
297 ; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
298 ; ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz
299 ;; =====================================
302 ; .ELSEIF FREQUENCY = 4
304 ; MOV #00D2h,&CSCTL0 ; preset DCO = 0xD2 (measured value @ 0x180)
306 ; MOV #0005h,&CSCTL1 ; Set 4MHZ DCORSEL,disable DCOFTRIM,Modulation
307 ;; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
308 ;; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h
309 ; ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz
311 ; MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h
312 ; ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz
314 ;; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
315 ; ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
316 ;; =====================================
319 ; .ELSEIF FREQUENCY = 8
322 ; MOV #00F3h,&CSCTL0 ; preset DCO = 0xF2 (measured value @ 0x180)
324 ; MOV #0007h,&CSCTL1 ; Set 8MHZ DCORSEL,disable DCOFTRIM,Modulation
325 ;; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
326 ;; MOV #00F2h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F2h
327 ; ; fCOCLKDIV = 32768 x (242+1) = 7.963 MHz ; measured : 7.943MHz
328 ;; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h
329 ; ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz
330 ; MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h
331 ; ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz
333 ;; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h
334 ; ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz
336 ;; MOV #00F8h,&CSCTL2 ; don't work with cp2102 (by low value)
337 ;; MOV #00FAh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh
339 ;; =====================================
342 ; .ELSEIF FREQUENCY = 16
344 ; MOV #0129h,&CSCTL0 ; preset DCO = 0x129 (measured value @ 0x180)
346 ; MOV #000Bh,&CSCTL1 ; Set 16MHZ DCORSEL,disable DCOFTRIM,Modulation
347 ;; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
348 ;; MOV #01E6h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h
349 ; ; fCOCLKDIV = 32768 x 486+1) = 15.958 MHz ; measured : 15.92MHz
350 ;; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
351 ; ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz
352 ;; MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
353 ; ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz
354 ; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
355 ; ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
356 ;; =====================================
361 ; MOV #058h,&CSCTL0 ; preset DCO = measured value @ 0x180 (88)
362 ; MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
363 MOV #1ED1h,&CSCTL0 ; preset MOD=31, DCO = measured value @ 0x180 (209)
364 MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
365 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
366 ; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh
367 ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz
368 ; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh
369 ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz
370 MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
371 ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
372 ; =====================================
375 .ELSEIF FREQUENCY = 1
377 ; MOV #100h,&CSCTL0 ; preset DCO = 256
378 ; MOV #00B1h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
379 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
380 MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
381 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
382 ; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh
383 ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz
384 MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh
385 ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz
386 ; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
387 ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
388 ; =====================================
391 .ELSEIF FREQUENCY = 2
393 ; MOV #100h,&CSCTL0 ; preset DCO = 256
394 ; MOV #00B3h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
395 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
396 MOV #00B2h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
397 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
398 ; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh
399 ; fCOCLKDIV = 32768 x (59+1) = 1.996 MHz ; measured : MHz
400 MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch
401 ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz
402 ; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
403 ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz
404 ; =====================================
407 .ELSEIF FREQUENCY = 4
409 ; MOV #100h,&CSCTL0 ; preset DCO = 256
410 ; MOV #00B5h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
411 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
412 MOV #00B4h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
413 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
414 ; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h
415 ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz
417 MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h
418 ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz
420 ; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
421 ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
422 ; =====================================
425 .ELSEIF FREQUENCY = 8
427 ; MOV #100h,&CSCTL0 ; preset DCO = 256
428 ; MOV #00B7h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
429 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
430 MOV #00B6h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
431 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
432 ; MOV #00F2h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F2h
433 ; fCOCLKDIV = 32768 x (242+1) = 7.963 MHz ; measured : 7.943MHz
434 ; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h
435 ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz
436 MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h
437 ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz
439 ; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h
440 ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz
442 ; MOV #00F8h,&CSCTL2 ; don't work with cp2102 (by low value)
443 ; MOV #00FAh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh
445 ; =====================================
448 .ELSEIF FREQUENCY = 12
450 ; MOV #100h,&CSCTL0 ; preset DCO = 256
451 ; MOV #00B9h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
452 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
453 MOV #00B8h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
454 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
455 ; MOV #016Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h
456 ; fCOCLKDIV = 32768 x 364+1) = 12.960 MHz ; measured : 11.xxxMHz
457 ; MOV #016Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
458 ; fCOCLKDIV = 32768 x 365+1) = 11.993 MHz ; measured : 11.xxxMHz
459 MOV #016Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
460 ; fCOCLKDIV = 32768 x 366+1) = 12.025 MHz ; measured : 12.xxxMHz
461 ; MOV #016Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
462 ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz
463 ; =====================================
466 .ELSEIF FREQUENCY = 16
468 ; MOV #100h,&CSCTL0 ; preset DCO = 256
469 ; MOV #00BBh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
470 MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255
471 MOV #00BAh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI
472 ; ===================================== ; fCOCLKDIV = REFO x (FLLN+1)
473 ; MOV #01E6h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h
474 ; fCOCLKDIV = 32768 x 486+1) = 15.958 MHz ; measured : 15.92MHz
475 ; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h
476 ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz
477 MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h
478 ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz
479 ; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
480 ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
481 ; =====================================
485 .error "bad frequency setting, only 0.5,1,2,4,8,12,16 MHz"
489 ; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
490 MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
492 BIS #0010h,&CSCTL3 ; FLL select REFCLOCK
493 ; MOV #0100h,&CSCTL4 ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value)
496 BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
497 ; MOV &SAVE_SYSRSTIV,TOS ;
498 ; CMP #2,TOS ; POWER ON ?
499 ; JZ ClockWaitX ; yes
500 ; RRUM #1,X ; wait only 250 ms
501 ClockWaitX MOV #5209,Y ; wait 0.5s before starting after POR
503 ClockWaitY SUB #1,Y ;1
504 JNZ ClockWaitY ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
505 SUB #1,X ; x 32 @ 1 MHZ = 500ms
506 JNZ ClockWaitX ; time to stabilize power source ( 500ms )
508 ;WAITFLL BIT #300h,&CSCTL7 ; wait FLL lock