1 ; -*- coding: utf-8 -*-
4 ; Fast Forth For Texas Instrument MSP430FR5994
6 ; Copyright (C) <2014> <J.M. THOORENS>
8 ; This program is free software: you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
22 ; ======================================================================
23 ; MSP_EXP430FR5994 board
24 ; ======================================================================
26 ; J101 Target <---> eZ-FET
30 ; P2.1 UCA0_RX 8-7 <---- TX UARTtoUSB bridge
31 ; +--4k7-< DeepRST <-- GND
33 ; P2.0 UCA0_TX 6-5 <-+-> RX UARTtoUSB bridge
38 ; P5.6 - sw1 <--- LCD contrast + (finger :-)
39 ; P5.5 - sw2 <--- LCD contrast - (finger ;-)
47 ; P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236)
48 ; P6.1/UCA3RXD/UCA3SOMI -------------------------> 4 LCD_RS
49 ; P6.0/UCA3TXD/UCA3SIMO -------------------------> 5 LCD_R/W
50 ; P6.2/UCA3CLK -------------------------> 6 LCD_EN0
51 ; P1.3/TA1.2/UCB0STE/A3/C3
54 ; P7.1/UCB2SOMI/UCB2SCL ---> SCL I2C MASTER/SLAVE
55 ; P7.0/UCB2SIMO/UCB2SDA <--> SDA I2C MASTER/SLAVE
60 ; P3.0/A12/C12 <------------------------> 11 LCD_DB4
61 ; P3.1/A13/C13 <------------------------> 12 LCD_DB5
62 ; P3.2/A14/C14 <------------------------> 13 LCD_DB5
63 ; P3.3/A15/C15 <------------------------> 14 LCD_DB7
64 ; P1.4/TB0.1/UCA0STE/A4/C4
65 ; P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
75 ; P2.6/TB0.1/UCA1RXD/UCA1SOMI
76 ; P2.5/TB0.0/UCA1TXD/UCA1SIMO
78 ; P4.2/A10 RTS ----> CTS UARTtoUSB bridge (optional hardware control flow)
79 ; P4.1/A9 CTS <---- RTS UARTtoUSB bridge (optional hardware control flow)
83 ; P5.7/UCA2STE/TA4.1/MCLK
87 ; P5.0/UCB1SIMO/UCB1SDA
88 ; P5.1/UCB1SOMI/UCB1SCL
90 ; P8.2 <--> SDA I2C SOFTWARE MASTER
91 ; P8.1 <--> SCL I2C SOFTWARE MASTER
94 ; P7.2/UCB2CLK <--- SD_CD
95 ; P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 ---> SD_MOSI
96 ; P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 <--- SD_MISO
98 ; P2.2/TB0.2/UCB0CLK ---> SD_CLK
109 ; -----------------------------------------------
111 ; -----------------------------------------------
113 ; <-------+---0V0----------> 1 LCD_Vss
114 ; >------ | --3V6-----+----> 2 LCD_Vdd
121 ; TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
122 ; -------------------------> 4 LCD_RS
123 ; -------------------------> 5 LCD_R/W
124 ; -------------------------> 6 LCD_EN0
125 ; <------------------------> 11 LCD_DB4
126 ; <------------------------> 12 LCD_DB5
127 ; <------------------------> 13 LCD_DB5
128 ; <------------------------> 14 LCD_DB7
132 ; ----------------------------------------------------------------------
133 ; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
134 ; ----------------------------------------------------------------------
136 ; ----------------------------------------------------------------------
137 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
138 ; ----------------------------------------------------------------------
140 ; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
142 ; ----------------------------------------------------------------------
143 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
144 ; ----------------------------------------------------------------------
146 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
148 ; ----------------------------------------------------------------------
149 ; POWER ON RESET AND INITIALIZATION : I/O
150 ; ----------------------------------------------------------------------
152 ; ----------------------------------------------------------------------
153 ; POWER ON RESET AND INITIALIZATION : PORT1/2
154 ; ----------------------------------------------------------------------
156 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
158 ; PORT1 FastForth usage
162 ; PORT2 FastForth usage
164 Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
165 Deep_RST .equ 1 ; P2.0 = TX
166 TERM_TXRX .equ 003h ; P2.1 = RX
170 ; PORTx default wanted state : pins as input with pullup resistor
172 BIS #3,&PADIR ; all pins 0 as input else LEDs
173 MOV #0FFFCh,&PAOUT ; all pins high else LEDs
174 BIC #3,&PAREN ; all pins 1 with pull resistors else LEDs
176 ; ----------------------------------------------------------------------
177 ; POWER ON RESET AND INITIALIZATION : PORT3/4
178 ; ----------------------------------------------------------------------
180 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
182 ; PORT3 FastForth usage
184 ; PORT4 FastForth usage
187 .IFDEF TERMINALCTSRTS
189 ; RTS output is wired to the CTS input of UART2USB bridge
190 ; CTS is not used by FORTH terminal
191 ; configure RTS as output high to disable RX TERM during start FORTH
195 HANDSHAKOUT .equ P4OUT
197 BIS #00400h,&PBDIR ; all pins as input else P4.2
198 BIS #-1,&PBREN ; all input pins with resistor
199 MOV #-1,&PBOUT ; that acts as pull up, and P4.2 as output HIGH
203 ; PORTx default wanted state : pins as input with pullup resistor
204 MOV #-1,&PBOUT ; OUT1
205 BIS #-1,&PBREN ; REN1 all pullup resistors
209 ; ----------------------------------------------------------------------
210 ; POWER ON RESET AND INITIALIZATION : PORT5/6
211 ; ----------------------------------------------------------------------
213 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
215 ; PORT5 FastForth usage
216 ; P5.6 Switch S1 used for hard reset (WIPE+COLD)
218 SWITCHIN .set P5IN ; port
219 s1 .set 020h ; P5.5 bit position
221 ; PORT6 FastForth usage
224 ; PORTx default wanted state : pins as input with pullup resistor
226 MOV #-1,&PCOUT ; all pins output high
227 BIS #-1,&PCREN ; all pins with pull resistors
229 ; ----------------------------------------------------------------------
230 ; POWER ON RESET AND INITIALIZATION : PORT7/8
231 ; ----------------------------------------------------------------------
233 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
235 ; PORT7 FastForth usage
237 ; PORT8 FastForth usage
240 ; PORTx default wanted state : pins as input with pullup resistor
242 MOV #-1,&PDOUT ; all pins output high
243 BIS #-1,&PDREN ; all pins with pull resistors
246 ; ----------------------------------------------------------------------
247 ; POWER ON RESET AND INITIALIZATION : PORTJ
248 ; ----------------------------------------------------------------------
250 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
252 ; PORTJ FastForth usage
254 ; PORTx default wanted state : pins as input with pullup resistor
256 MOV.B #-1,&PJREN ; enable pullup/pulldown resistors
257 BIS.B #-1,&PJOUT ; pullup resistors
260 ; ----------------------------------------------------------------------
262 ; ----------------------------------------------------------------------
265 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
266 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
267 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
270 ; ----------------------------------------------------------------------
271 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
272 ; ----------------------------------------------------------------------
274 ; DCOCLK: Internal digitally controlled oscillator (DCO).
275 ; Startup clock system in max. DCO setting ~8MHz
278 ; CS code for MSP430FR5969
279 MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
282 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
283 MOV #DIVA_0 + DIVS_32 + DIVM_32,&CSCTL3
286 .ELSEIF FREQUENCY = 0.5
287 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
288 MOV #DIVA_2 + DIVS_2 + DIVM_2,&CSCTL3 ; set all dividers as 2
291 .ELSEIF FREQUENCY = 1
292 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
293 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
296 .ELSEIF FREQUENCY = 2
297 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
298 MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
301 .ELSEIF FREQUENCY = 4
302 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
303 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
306 .ELSEIF FREQUENCY = 8
307 ; MOV #DCOFSEL2+DCOFSEL1,&CSCTL1 ; Set 8MHZ DCO setting (default value)
308 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
311 .ELSEIF FREQUENCY = 16
312 MOV #DCORSEL+DCOFSEL2,&CSCTL1 ; Set 16MHZ DCO setting
313 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
317 .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
321 MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
323 MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
325 MOV.B #01h, &CSCTL0_H ; Lock CS Registers
327 BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
328 CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
330 .word 0759h ; no RRUM #2,X --> wait only 125 ms
331 ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
332 ClockWaitY SUB #1,Y ;
333 JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
334 SUB #1,X ; x 4 @ 1 MHZ
335 JNZ ClockWaitX ; time to stabilize power source ( 1s )
337 ; ----------------------------------------------------------------------
338 ; POWER ON RESET AND INITIALIZATION : REF
339 ; ----------------------------------------------------------------------
343 ; ----------------------------------------------------------------------
344 ; POWER ON RESET AND INITIALIZATION : RTC_C REGISTERS
345 ; ----------------------------------------------------------------------
348 ; LFXIN : PJ.4, LFXOUT : PJ.5
349 BIS.B #010h,&PJSEL0 ; SEL0 for only LFXIN
350 MOV.B #0A5h,&RTCCTL0_H ; unlock RTC_C
351 BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_C
354 ; ----------------------------------------------------------------------
355 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
356 ; ----------------------------------------------------------------------