1 ; -*- coding: utf-8 -*-
3 ; config file for MY_MSP430FR5738 board
5 ; Copyright (C) <2014> <J.M. THOORENS>
7 ; This program is free software: you can redistribute it and/or modify
8 ; it under the terms of the GNU General Public License as published by
9 ; the Free Software Foundation, either version 3 of the License, or
10 ; (at your option) any later version.
12 ; This program is distributed in the hope that it will be useful,
13 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ; GNU General Public License for more details.
17 ; You should have received a copy of the GNU General Public License
18 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
21 ; ======================================================================
22 ; MY_MSP430FR5738 board
23 ; ======================================================================
25 ; MSP430FR5738 XTAL 32768 Hz
26 ; 1 --- PJ.4 --- LFXIN
27 ; 2 --- PJ.5 --- LFXOUT
29 ; MSP430FR5738 PROG 6PINS UART 4PINS
30 ; --- VCC <-> 2 "3v3" <-> 1 "3v3"
31 ; 20 --- P2.1 <-- 6 "RXD" <-- 2 "RXD"
32 ; +--4k7-< DeepRST <-- GND
34 ; 19 --- P2.0 <+> 1 "TXD" --> 3 "TXD"
35 ; --- VSS <-> 5 "GND" <-> 4 "GND"
36 ; 17 --- TEST --- 3 "TST"
37 ; 18 --- RST --- 4 "RST"
40 ; oriented to UART 4PINS
43 ; 1 "3v3" <-> DVCC,AVCC
44 ; 2 "SCL" <-> pin23 = P1.7 == UCB0RXD --> UCB0RXDBUF
45 ; 3 "SDA" <-> pin22 = P1.6 == UCB0TXD <-- UCB0TXDBUf
46 ; 4 "GND" <-> DVSS,AVSS
49 ; 1 <-> pin5 P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
50 ; 2 <-> pin6 P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
51 ; 3 <-> pin7 P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
52 ; 4 <-> pin8 P1.3/TA1.2/UCB0STE/A3/CD3
53 ; 5 <-> pin9 P1.4/TB0.1/UCA0STE/A4/CD4
54 ; 6 <-> pin10 P1.5/TB0.2/UCA0CLK/A5/CD5
55 ; 7 <-> pin22 P1.6/UCB0SIMO/UCB0SDA/TA0.0
56 ; 8 <-> pin23 P1.7/UCB0SOMI/UCB0SCL/TA1.0
59 ; 1 <-> pin19 P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
60 ; 2 <-> pin20 P2.1/UCA0RXD/UCA0SOMI/TB0.0
61 ; 3 <-> pin21 P2.2/UCB0CLK
62 ; 4 <-> pin27 P2.3/TA0.0/A6/CD10
63 ; 5 <-> pin28 P2.4/TA1.0/A7/CD11
64 ; 6 <-> pin15 P2.5/TB0.0
71 ; 3 <-> pin11 PJ.0/TDO/TB0OUTH/SMCLK/CD6
72 ; 4 <-> pin12 PJ.1/TDI/TCLK/MCLK/CD7
73 ; 5 <-> pin13 PJ.2/TMS/ACLK/CD8
74 ; 6 <-> pin14 PJ.3/TCK/CD9
80 ; PJ.5 <->XOUT LF XTAL
82 ; Vcc <------------------------- Vcc \
83 ; RST <------------------------> RST \ TI_PROGRM
84 ; TST <------------------------> TST / INTERFACE
85 ; Vss <------------------------> Gnd /
87 ; Vcc <------------------------- Vcc \
88 ; P2.0 TX0 ---------------------> RX \ UARTtoUSB
89 ; P2.1 RX0 <--------------------- TX / CP2102
90 ; Vss <------------------------> Gnd /
92 ; GND <-------+---0V0----------> 1 LCD_Vss
93 ; VCC <------ | --3V6-----+----> 2 LCD_Vdd
100 ; P1.5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
101 ; P1.4 >------------------------> 4 LCD_RS
102 ; P1.3 >------------------------> 5 LCD_R/W
103 ; P1.2 >------------------------> 6 LCD_EN
105 ; P1.1 >------------------------> 5 SCL I2C MASTER
106 ; P1.0 >------------------------> 6 SDA I2C MASTER | IR_RC5 receiver
108 ; PJ.0 <------------------------> 11 LCD_DB4
109 ; PJ.1 <------------------------> 12 LCD_DB5
110 ; PJ.2 <------------------------> 13 LCD_DB5
111 ; PJ.3 <------------------------> 14 LCD_DB7
113 ; P2.5 ---> S2 LCD contrast +
114 ; P2.6 ---> S1 LCD contrast - | HARD WIPE
118 ; VCC P1.1 ---> red SD_CardAdapter VCC
119 ; GND P1.2 <--> black SD_CardAdapter GND
120 ; P1.6/UCB0SIMO/UCB0SDA/TA0.0 P1.7 ---> grey SD_CardAdapter SDI (MOSI)
121 ; P1.7/UCB0SOMI/UCB0SCL/TA1.0 <--- purple SD_CardAdapter SDO (MISO)
122 ; P2.2/UCB0CLK ---> orange SD_CardAdapter CLK (SCK)
123 ; P2.3/TA0.0/A6/CD10 <--- violin SD_CardAdapter CD (Card Detect)
124 ; P2.4/TA1.0/A7/CD11 ---> brown SD_CardAdapter CS (Card Select)
131 ; ----------------------------------------------------------------------
132 ; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
133 ; ----------------------------------------------------------------------
135 ; ----------------------------------------------------------------------
136 ; POWER ON RESET AND INITIALIZATION : LOCK I/O as high impedance state
137 ; ----------------------------------------------------------------------
139 BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
141 ; ----------------------------------------------------------------------
142 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
143 ; ----------------------------------------------------------------------
146 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
148 ; ----------------------------------------------------------------------
149 ; POWER ON RESET AND INITIALIZATION : I/O
150 ; ----------------------------------------------------------------------
152 ; ----------------------------------------------------------------------
153 ; POWER ON RESET AND INITIALIZATION PAIN=PORT2:PORT1
154 ; ----------------------------------------------------------------------
156 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
162 Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
163 Deep_RST .equ 1 ; P2.0 = TX
164 TERM_TXRX .equ 003h ; P2.1 = RX
168 .IFDEF TERMINALCTSRTS
169 ;configure P2.2 as RTS output high
171 HANDSHAKOUT .equ P2OUT
173 BIS.B #RTS,&HANDSHAKOUT
176 ; PORTx default wanted state : pins as input with pullup resistor
178 MOV #-1,&PAOUT ; all pins 1
179 BIS #-1,&PAREN ; all pins 1 with pull resistors
181 ; ----------------------------------------------------------------------
182 ; POWER ON RESET AND INITIALIZATION : PORTJ
183 ; ----------------------------------------------------------------------
185 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
189 ; PORTx default wanted state : pins as input with pullup resistor
191 MOV.B #-1,&PJOUT ; pullup resistors
192 BIS.B #-1,&PJREN ; enable pullup/pulldown resistors
194 ; ----------------------------------------------------------------------
196 ; ----------------------------------------------------------------------
198 ; ----------------------------------------------------------------------
199 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
200 ; ----------------------------------------------------------------------
202 ; DCOCLK: Internal digitally controlled oscillator (DCO).
204 MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
207 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
208 MOV #DIVA_0 + DIVS_16 + DIVM_16,&CSCTL3
211 .ELSEIF FREQUENCY = 1
212 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
213 MOV #DIVA_0 + DIVS_8 + DIVM_8,&CSCTL3
216 .ELSEIF FREQUENCY = 2
217 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
218 MOV #DIVA_0 + DIVS_4 + DIVM_4,&CSCTL3
221 .ELSEIF FREQUENCY = 4
222 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
223 MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
226 .ELSEIF FREQUENCY = 8
227 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
228 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
231 .ELSEIF FREQUENCY = 16
232 MOV #DCORSEL,&CSCTL1 ; Set 16MHZ DCO setting
233 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
236 .ELSEIF FREQUENCY = 24
237 MOV #DCORSEL+DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 24 MHZ DCO setting
238 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
242 .error "bad frequency setting, only 0.5,1,2,4,8,16,24 MHz"
246 MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
248 MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
250 MOV.B #01h, &CSCTL0_H ; Lock CS Registers
252 BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
253 CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
255 .word 0759h ; no RRUM #2,X --> wait only 125 ms
256 ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
257 ClockWaitY SUB #1,Y ;
258 JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
259 SUB #1,X ; x 4 @ 1 MHZ
260 JNZ ClockWaitX ; time to stabilize power source ( 1s )
262 ; ----------------------------------------------------------------------
263 ; POWER ON RESET AND INITIALIZATION : REF
264 ; ----------------------------------------------------------------------
268 ; ----------------------------------------------------------------------
269 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
270 ; ----------------------------------------------------------------------
273 ; LF Xtal XIN : PJ.4, LF Xtal XOUT : PJ.5
274 BIS.B #010h,&PJSEL0 ; SEL0 for only XIN
275 BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B