1 ; -*- coding: utf-8 -*-
4 ; Fast Forth For Texas Instrument MSP430FR5739
6 ; Copyright (C) <2014> <J.M. THOORENS>
8 ; This program is free software: you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
21 ; ======================================================================
22 ; MY_MSP430FR5948_1 : MSP430FR5948 TSSOP38 to DIP28 board MAP
23 ; may be remplaced by MSP430FR5939 TSSOP 38
24 ; Version 1 : added a 4k7 resistor on RX signal between Si8622EC and PROG6PINS
25 ; SD_CS and SD_CD are inverted
26 ; ======================================================================
28 ; MSP430FR5948 XTAL 32768 Hz
29 ; 1 --- PJ.4 --- LFXIN
30 ; 2 --- PJ.5 --- LFXOUT
32 ; MSP430FR5948 PROG 6PINS ISOLATED UARTtoUSB bridge
33 ; 34 --- DVCC <-> 2 "3v3" --------> 1 Vdd1 <| SI |> Vdd2 8 <-- 3v3
34 ; 24 --- P2.1 <-- 6 "RX0" <----4k7- 2 A1 <| 86 |> B1 7 <-- TXD
35 ; 23 --- P2.0 <-> 1 "TX0" <--+----> 3 A2 <| 22 |> B2 6 --> RXD
36 ; 33 --- DVSS <-> 5 "GND" <- | ---> 4 Gnd1 <| EC |> Gnd2 5 <-- GND
37 ; 21 --- TEST --- 3 "TST" |
38 ; 22 --- RST --- 4 "RST" |
39 ; +-4k7- DeepRST <-- GND
42 ; DIP28 1 --- 4 AVCC --- ferrite bead --- DVCC 34
43 ; DIP28 2 --- 3 AVSS --- ferrite bead --- DVSS 33
46 ; 4, --- AVCC --- 1 ; +
47 ; 3,38 --- AVSS --- 2 ; -
49 ; 37 --- P2.4 --- 4 ; TA1.0/UCA1CLK/A7/C11
50 ; 36 --- P2.3 --- 5 ; TA0.0/UCA1STE/A6/C10
51 ; 30 --- P1.6 --- 6 ; TB0.3/UCB0SIMO/UCB0SDA/TA0.0
52 ; 31 --- P1.7 --- 7 ; TB0.4/UCB0SOMI/UCB0SCL/TA1.0
53 ; 29 --- P3.7 --- 8 ; TB0.6
54 ; 28 --- P3.6 --- 9 ; TB0.5
55 ; 27 --- P3.5 --- 10 ; TB0.4/COUT
56 ; 26 --- P3.4 --- 11 ; TB0.3/SMCLK
57 ; 20 --- P2.6 --- 12 ; TB0.1/UCA1RXD/UCA1SOMI
58 ; 25 --- P2.2 --- 13 ; TB0.2/UCB0CLK
59 ; 19 --- P2.5 --- 14 ; TB0.0/UCA1TXD/UCA1SIMO
60 ; 15 --- PJ.0 --- 15 ; TDO/TB0OUTH/SMCLK/SRSCG1/C6
61 ; 16 --- PJ.1 --- 16 ; TDI/TCLK/MCLK/SRSCG0/C7
62 ; 17 --- PJ.2 --- 17 ; TMS/ACLK/SROSCOFF/C8
63 ; 18 --- PJ.3 --- 18 ; TCK/SRCPUOFF/C9
64 ; 14 --- P1.5 --- 19 ; TB0.2/UCA0CLK/A5/C5
65 ; 13 --- P1.4 --- 20 ; TB0.1/UCA0STE/A4/C4
66 ; 12 --- P1.3 --- 21 ; TA1.2/UCB0STE/A3/C3
67 ; 10 --- P3.2 --- 22 ; A14/C14
68 ; 11 --- P3.3 --- 23 ; A15/C15
69 ; 9 --- P3.1 --- 24 ; A13/C13
70 ; 8 --- P3.0 --- 25 ; A12/C12
71 ; 5 --- P1.0 --- 26 ; TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
72 ; 6 --- P1.1 --- 27 ; TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
73 ; 7 --- P1.2 --- 28 ; TA1.1/TA0CLK/COUT/A2/C2
78 ; P1.2 - DIP.28 <------------------------> SDA I2C SOFTWARE MASTER
79 ; P1.3 - DIP.21 <------------------------> SCL I2C SOFTWARE MASTER
82 ; P1.6 - DIP.6 UCB0 SDA/SIMO <------------> SDA I2C MASTER/SLAVE
83 ; P1.7 - DIP.7 UCB0 SCL/SOMI <------------> SCL I2C MASTER/SLAVE
86 ; VCC - -------------------------> VCC SD_CardAdapter
87 ; P2.2 - DIP.13 -------------------------> TB0.2 LCD_Vo
88 ; P2.3 - DIP.5 -------------------------> SD_CardAdapter DAT3/CS (Card Select) (CD at power up)
89 ; P2.4 - DIP.4 UCA1/CLK ---------------> SD_CardAdapter SCK
90 ; P2.5 - DIP.14 UCA1/SIMO ---------------> SD_CardAdapter CMD/SDI (MOSI)
91 ; P2.6 - DIP.12 UCA1/SOMI <--------------- SD_CardAdapter DAT0/SDO (MISO)
92 ; P2.7 - -------------------------> SD_CardAdapter CD (CardDetect)
93 ; VSS - <------------------------> GND SD_CardAdapter
96 ; P3.0 - DIP.25 -------------------------> 4 LCD_RS
97 ; P3.1 - DIP.24 -------------------------> 5 LCD_R/W
98 ; P3.2 - DIP.23 -------------------------> 6 LCD_EN
99 ; P3.3 - DIP.22 <------------------------- OUT IR_Receiver (1 TSOP32236)
100 ; P3.4 - DIP.11 -------------------------> sw1 (hard reset)
101 ; P3.5 - DIP.10 -------------------------> sw2
106 ; PJ.0 - DIP.15 <------------------------> 11 LCD_DB4
107 ; PJ.1 - DIP.16 <------------------------> 12 LCD_DB5
108 ; PJ.2 - DIP.17 <------------------------> 13 LCD_DB5
109 ; PJ.3 - DIP.18 <------------------------> 14 LCD_DB7
114 ; ----------------------------------------------------------------------
115 ; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
116 ; ----------------------------------------------------------------------
118 ; ----------------------------------------------------------------------
119 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
120 ; ----------------------------------------------------------------------
122 ; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
124 ; ----------------------------------------------------------------------
125 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
126 ; ----------------------------------------------------------------------
128 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
130 ; ----------------------------------------------------------------------
131 ; POWER ON RESET AND INITIALIZATION : I/O
132 ; ----------------------------------------------------------------------
134 ; ----------------------------------------------------------------------
135 ; POWER ON RESET AND INITIALIZATION : PORT1/2
136 ; ----------------------------------------------------------------------
138 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
144 Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
145 Deep_RST .equ 1 ; P2.0
150 .IFDEF TERMINALCTSRTS
151 .error "CTS/RTS Control Flow not implemented"
154 ; PORTx default wanted state : pins as input with pullup resistor
156 MOV #-1,&PAOUT ; OUT1
157 BIS #-1,&PAREN ; REN1 all pullup resistors
159 ; ----------------------------------------------------------------------
160 ; POWER ON RESET AND INITIALIZATION : PORT3/4
161 ; ----------------------------------------------------------------------
163 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
169 ; PORTx default wanted state : pins as input with pullup resistor
171 MOV #-1,&PBOUT ; pullup
172 BIS #-1,&PBREN ; all pullup resistors
174 ; ----------------------------------------------------------------------
175 ; POWER ON RESET AND INITIALIZATION : PORTJ
176 ; ----------------------------------------------------------------------
178 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
182 ; PORTx default wanted state : pins as input with pullup resistor
185 BIS.B #-1,&PJREN ; pullup resistors on unused pins
187 ; ----------------------------------------------------------------------
189 ; ----------------------------------------------------------------------
192 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
193 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
194 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
197 ; ----------------------------------------------------------------------
198 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
199 ; ----------------------------------------------------------------------
201 ; DCOCLK: Internal digitally controlled oscillator (DCO).
202 ; Startup clock system in max. DCO setting ~8MHz
205 ; CS code for MSP430FR5948
206 MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
209 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
210 MOV #DIVA_2 + DIVS_2 + DIVM_2,&CSCTL3 ; set all dividers as 2
213 .ELSEIF FREQUENCY = 1
214 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
215 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
218 .ELSEIF FREQUENCY = 2
219 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
220 MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
223 .ELSEIF FREQUENCY = 4
224 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
225 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
228 .ELSEIF FREQUENCY = 8
229 ; MOV #DCOFSEL2+DCOFSEL1,&CSCTL1 ; Set 8MHZ DCO setting (default value)
230 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
233 .ELSEIF FREQUENCY = 16
234 MOV #DCORSEL+DCOFSEL2,&CSCTL1 ; Set 16MHZ DCO setting
235 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
239 .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
243 MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
245 MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
247 MOV.B #01h, &CSCTL0_H ; Lock CS Registers
249 BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
250 CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
252 .word 0759h ; no RRUM #2,X --> wait only 125 ms
253 ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
254 ClockWaitY SUB #1,Y ;
255 JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
256 SUB #1,X ; x 4 @ 1 MHZ
257 JNZ ClockWaitX ; time to stabilize power source ( 1s )
259 ; ----------------------------------------------------------------------
260 ; POWER ON RESET AND INITIALIZATION : REF
261 ; ----------------------------------------------------------------------
265 ; ----------------------------------------------------------------------
266 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
267 ; ----------------------------------------------------------------------
270 ; LF Xtal XIN : PJ.4, LF Xtal XOUT : PJ.5
271 BIS.B #010h,&PJSEL0 ; SEL0 for only XIN
272 BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
275 ; ----------------------------------------------------------------------
276 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
277 ; ----------------------------------------------------------------------