1 ; -*- coding: utf-8 -*-
4 ; Fast Forth For Texas Instrument MSP430FR5994
6 ; Copyright (C) <2014> <J.M. THOORENS>
8 ; This program is free software: you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
22 ; ======================================================================
23 ; MSP_EXP430FR5994 board
24 ; ======================================================================
26 ; J101 Target <---> eZ-FET
30 ; P2.1 UCA0_RX 8-7 <---- TX UARTtoUSB bridge
31 ; +--4k7-< DeepRST <-- GND
33 ; P2.0 UCA0_TX 6-5 <-+-> RX UARTtoUSB bridge
38 ; P5.6 - sw1 <--- LCD contrast + (finger :-)
39 ; P5.5 - sw2 <--- LCD contrast - (finger ;-)
47 ; P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236)
48 ; P6.1/UCA3RXD/UCA3SOMI -------------------------> 4 LCD_RS
49 ; P6.0/UCA3TXD/UCA3SIMO -------------------------> 5 LCD_R/W
50 ; P6.2/UCA3CLK -------------------------> 6 LCD_EN0
51 ; P1.3/TA1.2/UCB0STE/A3/C3
54 ; P7.1/UCB2SOMI/UCB2SCL ---> SCL I2C MASTER/SLAVE
55 ; P7.0/UCB2SIMO/UCB2SDA <--> SDA I2C MASTER/SLAVE
60 ; P3.0/A12/C12 <------------------------> 11 LCD_DB4
61 ; P3.1/A13/C13 <------------------------> 12 LCD_DB5
62 ; P3.2/A14/C14 <------------------------> 13 LCD_DB5
63 ; P3.3/A15/C15 <------------------------> 14 LCD_DB7
64 ; P1.4/TB0.1/UCA0STE/A4/C4
65 ; P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
75 ; P2.6/TB0.1/UCA1RXD/UCA1SOMI
76 ; P2.5/TB0.0/UCA1TXD/UCA1SIMO
78 ; P4.2/A10 RTS ----> CTS UARTtoUSB bridge (optional hardware control flow)
79 ; P4.1/A9 CTS <---- RTS UARTtoUSB bridge (optional hardware control flow)
83 ; P5.7/UCA2STE/TA4.1/MCLK
87 ; P5.0/UCB1SIMO/UCB1SDA
88 ; P5.1/UCB1SOMI/UCB1SCL
90 ; P8.2 <--> SDA I2C SOFTWARE MASTER
91 ; P8.1 <--> SCL I2C SOFTWARE MASTER
94 ; P7.2/UCB2CLK <--- SD_CD
95 ; P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 ---> SD_MOSI
96 ; P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 <--- SD_MISO
98 ; P2.2/TB0.2/UCB0CLK ---> SD_CLK
109 ; -----------------------------------------------
111 ; -----------------------------------------------
113 ; <-------+---0V0----------> 1 LCD_Vss
114 ; >------ | --3V6-----+----> 2 LCD_Vdd
121 ; TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
122 ; -------------------------> 4 LCD_RS
123 ; -------------------------> 5 LCD_R/W
124 ; -------------------------> 6 LCD_EN0
125 ; <------------------------> 11 LCD_DB4
126 ; <------------------------> 12 LCD_DB5
127 ; <------------------------> 13 LCD_DB5
128 ; <------------------------> 14 LCD_DB7
132 ; ----------------------------------------------------------------------
133 ; INIT order : WDT, GPIOs, FRAM, Clock, RTC, REF
134 ; ----------------------------------------------------------------------
136 ; ----------------------------------------------------------------------
137 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
138 ; ----------------------------------------------------------------------
140 MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
142 ; ----------------------------------------------------------------------
143 ; POWER ON RESET AND INITIALIZATION : I/O
144 ; ----------------------------------------------------------------------
146 ; ----------------------------------------------------------------------
147 ; POWER ON RESET AND INITIALIZATION : PORT1/2
148 ; ----------------------------------------------------------------------
150 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
152 ; PORT1 FastForth usage
156 ; PORTx default wanted state : pins as input with pullup resistor
158 BIS #3,&PADIR ; all pins 0 as input else LEDs
159 MOV #0FFFCh,&PAOUT ; all pins high else LEDs
160 BIC #3,&PAREN ; all pins 1 with pull resistors else LEDs
163 ; PORT2 FastForth usage
165 .IFDEF UCB0_SD ; see device.inc
166 SD_SEL .equ PASEL1 ; to configure UCB0
167 SD_REN .equ PAREN ; to configure pullup resistors
168 SD_BUS .equ 04C0h ; pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0SOMI
171 .IFDEF UCA0_TERM ; see device.inc
172 ; P2.0 UCA0-TXD --> USB2UART RXD
173 ; P2.1 UCA0-RXD <-- USB2UART TXD
174 TXD .equ 1 ; P2.0 = TXD + FORTH Deep_RST pin
175 RXD .equ 2 ; P2.1 = RXD
182 .IFDEF UCA1_TERM ; see device.inc
183 ; P2.5 UCA0-TXD --> USB2UART RXD
184 ; P2.6 UCA0-RXD <-- USB2UART TXD
185 TXD .equ 20h ; P2.5 = TXD + FORTH Deep_RST pin
186 RXD .equ 40h ; P2.6 = RXD
194 ; ----------------------------------------------------------------------
195 ; POWER ON RESET AND INITIALIZATION : PORT3/4
196 ; ----------------------------------------------------------------------
198 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
200 ; PORT3 FastForth usage
202 ; PORT4 FastForth usage
203 SD_CS .equ 1 ; P4.0 as SD_CS
208 MOV #-1,&PBREN ; REN1 all pullup resistors
211 .IFDEF TERMINAL4WIRES
212 .IFDEF TERMINAL5WIRES
213 ; CTS input must be wired to the RTS output of UART2USB bridge
214 ; configure CTS as input low (true) to avoid lock when CTS is not wired
216 BIC.B #CTS,&P4OUT ; CTS input pulled down
217 .ENDIF ; TERMINAL5WIRES
218 ; RTS output is wired to the CTS input of UART2USB bridge
219 ; configure RTS as output high to disable RX TERM during start FORTH
220 HANDSHAKOUT .equ P4OUT
223 BIS.B #RTS,&P4DIR ; RTS as output high
224 .ENDIF ; TERMINAL4WIRES
226 ; ----------------------------------------------------------------------
227 ; POWER ON RESET AND INITIALIZATION : PORT5/6
228 ; ----------------------------------------------------------------------
230 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
232 ; PORT5 FastForth usage
235 SWITCHIN .set P5IN ; port
236 s1 .set 020h ; P5.5 bit position
238 .IFDEF UCB1_SD ; see device.inc
239 SD_SEL .equ PCSEL1 ; to configure UCB0
240 SD_REN .equ PCREN ; to configure pullup resistors
241 SD_BUS .equ 0007h ; pins P5.2 as UCB1CLK, P5.0 as UCB1SIMO & P5.1 as UCB1SOMI
244 ; PORT6 FastForth usage
247 ; PORTx default wanted state : pins as input with pullup resistor
249 MOV #-1,&PCOUT ; all pins output high
250 BIS #-1,&PCREN ; all pins with pull resistors
252 ; ----------------------------------------------------------------------
253 ; POWER ON RESET AND INITIALIZATION : PORT7/8
254 ; ----------------------------------------------------------------------
256 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
258 ; PORT7 FastForth usage
259 SD_CD .equ 4 ; P7.2 as SD_CD
263 ; PORT8 FastForth usage
266 ; PORTx default wanted state : pins as input with pullup resistor
268 MOV #-1,&PDOUT ; all pins output high
269 BIS #-1,&PDREN ; all pins with pull resistors
272 ; ----------------------------------------------------------------------
273 ; POWER ON RESET AND INITIALIZATION : PORTJ
274 ; ----------------------------------------------------------------------
276 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
278 ; PORTJ FastForth usage
280 ; PORTx default wanted state : pins as input with pullup resistor
282 MOV.B #-1,&PJREN ; enable pullup/pulldown resistors
283 BIS.B #-1,&PJOUT ; pullup resistors
286 ; ----------------------------------------------------------------------
288 ; ----------------------------------------------------------------------
291 MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
292 MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
293 MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
296 ; ----------------------------------------------------------------------
297 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
298 ; ----------------------------------------------------------------------
300 ; DCOCLK: Internal digitally controlled oscillator (DCO).
303 ; CS code for MSP430FR5948
304 MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
307 ; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
308 MOV #DIVA_0 + DIVS_32 + DIVM_32,&CSCTL3
311 .ELSEIF FREQUENCY = 0.5
312 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
313 MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3 ; set all dividers as 2
316 .ELSEIF FREQUENCY = 1
317 MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
318 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
321 .ELSEIF FREQUENCY = 2
322 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
323 MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
326 .ELSEIF FREQUENCY = 4
327 MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
328 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
331 .ELSEIF FREQUENCY = 8
332 ; MOV #DCOFSEL2+DCOFSEL1,&CSCTL1 ; Set 8MHZ DCO setting (default value)
333 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
336 .ELSEIF FREQUENCY = 16
337 MOV #DCORSEL+DCOFSEL2,&CSCTL1 ; Set 16MHZ DCO setting
338 MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
342 .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
346 MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
348 MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
350 MOV.B #1, &CSCTL0_H ; Lock CS Registers
352 BIS &SYSRSTIV,&SAVE_SYSRSTIV ; store volatile SYSRSTIV preserving a pending request for DEEP_RST
353 ; MOV &SAVE_SYSRSTIV,TOS ;
354 ; CMP #2,TOS ; POWER ON ?
355 ; JZ ClockWaitX ; yes
356 ; RRUM #2,X ; no: wait only 125 ms
357 ClockWaitX MOV #5209,Y ; wait 0.5s before starting after POWER ON
358 ClockWaitY SUB #1,Y ;1
359 JNZ ClockWaitY ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
360 SUB #1,X ; x 32 @ 1 MHZ = 500ms
361 JNZ ClockWaitX ; time to stabilize power source ( 500ms )
363 ; ----------------------------------------------------------------------
364 ; POWER ON RESET AND INITIALIZATION : RTC_C REGISTERS
365 ; ----------------------------------------------------------------------
367 .IFDEF LF_XTAL ; see device.inc
368 ; LFXIN : PJ.4, LFXOUT : PJ.5
369 BIS.B #010h,&PJSEL0 ; SEL0 for only LFXIN
370 MOV.B #0A5h,&RTCCTL0_H ; unlock RTC_C
371 BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_C
374 ; ----------------------------------------------------------------------
375 ; POWER ON RESET AND INITIALIZATION : REF
376 ; ----------------------------------------------------------------------
380 ; ----------------------------------------------------------------------
381 ; POWER ON RESET AND INITIALIZATION next : see RESET in forthMSP430.asm
382 ; ----------------------------------------------------------------------