prog/MacroAssemblerAS/include/regmsp.inc

   1                 save
   2                 listing off   ; kein Listing \81ber diesen File
   3
   4 ;****************************************************************************
   5 ;*                                                                          *
   6 ;*   AS 1.41 - Datei REGMSP.INC                                             *
   7 ;*                                                                          *
   8 ;*   Sinn : enth\84lt Makro- und Registerdefinitionen f\81r den MSP430          *
   9 ;*                                                                          *
  10 ;*   letzte \8enderungen : 2002-01-11                                         *
  11 ;*                                                                          *
  12 ;****************************************************************************
  13 ;* $Id: regmsp.inc,v 1.3 2008/01/02 22:32:21 alfred Exp $
  14 ;****************************************************************************
  15 ;* $Log: regmsp.inc,v $
  16 ;* Revision 1.3  2008/01/02 22:32:21  alfred
  17 ;* - better heap checking for DOS target
  18 ;*
  19 ;* Revision 1.2  2007/12/31 13:23:53  alfred
  20 ;* - added some bit definitions
  21 ;*
  22 ;****************************************************************************
  23
  24                 ifndef  regmspinc      ; verhindert Mehrfacheinbindung
  25
  26 regmspinc       equ     1
  27
  28                 if      (MOMCPUNAME<>"MSP430")
  29                  fatal  "Falscher Prozessortyp eingestellt: nur MSP430 erlaubt!"
  30                 endif
  31
  32                 if      MOMPASS=1
  33                  message "MSP430-Register+Befehlsdefinitionen (C) 1996/2007 Alfred Arnold, Jose Da Silva"
  34                 endif
  35
  36 ;----------------------------------------------------------------------------
  37 ; Arithmetik
  38
  39 adc             macro   op
  40                 addc.attribute #0,op
  41                 endm
  42
  43 dadc            macro   op
  44                 dadd.attribute #0,op
  45                 endm
  46
  47 dec             macro   op
  48                 sub.attribute #1,op
  49                 endm
  50
  51 decd            macro   op
  52                 sub.attribute #2,op
  53                 endm
  54
  55 inc             macro   op
  56                 add.attribute #1,op
  57                 endm
  58
  59 incd            macro   op
  60                 add.attribute #2,op
  61                 endm
  62
  63 sbc             macro   op
  64                 subc.attribute #0,op
  65                 endm
  66
  67 ;----------------------------------------------------------------------------
  68 ; Logik
  69
  70 inv             macro   op
  71                 xor.attribute #-1,op
  72                 endm
  73
  74 rla             macro   op
  75                 add.attribute op,op
  76                 endm
  77
  78 rlc             macro   op
  79                 addc.attribute op,op
  80                 endm
  81
  82 ;----------------------------------------------------------------------------
  83 ; Daten bewegen ;-)
  84
  85 clr             macro   op
  86                 mov.attribute #0,op
  87                 endm
  88
  89 clrc            macro
  90                 bic     #1,sr
  91                 endm
  92
  93 clrn            macro
  94                 bic     #4,sr
  95                 endm
  96
  97 clrz            macro
  98                 bic     #2,sr
  99                 endm
 100
 101 pop             macro   op
 102                 mov     @sp+,op
 103                 endm
 104
 105 setc            macro
 106                 bis     #1,sr
 107                 endm
 108
 109 setn            macro
 110                 bis     #4,sr
 111                 endm
 112
 113 setz            macro
 114                 bis     #2,sr
 115                 endm
 116
 117 tst             macro   op
 118                 cmp.attribute #0,op
 119                 endm
 120
 121 ;----------------------------------------------------------------------------
 122 ; Sprungbefehle
 123
 124 br              macro   op
 125                 mov     op,pc
 126                 endm
 127
 128 dint            macro
 129                 bic     #8,sr
 130                 endm
 131
 132 eint            macro
 133                 bis     #8,sr
 134                 endm
 135
 136 nop             macro
 137                 .word   04303h         ; den symbolischen Befehl w\81rde AS zur\81ckweisen
 138                 endm
 139
 140 ret             macro
 141                 mov     @sp+,pc
 142                 endm
 143
 144 jlo             macro   label
 145                 jnc     label
 146                 endm
 147
 148 jhs             macro   label
 149                 jc      label
 150                 endm
 151
 152 jeq             macro   label
 153                 jz      label
 154                 endm
 155
 156 ;----------------------------------------------------------------------------
 157 ; General Memory Layout
 158 ; ----------------------
 159 ;
 160 ; 0000 - 000f : Special Function Registers
 161 ; 0010 - 00ff : 8bit Peripheral Modules
 162 ; 0100 - 01ff : 16bit Peripheral Modules
 163 ; 0200 - .... : RAM Memory
 164 ; .... - ffdf : Flash Memory
 165 ; ffe0 - ffff : Interrupt Vector Table
 166 ;
 167 ;----------------------------------------------------------------------------
 168
 169 ;----------------------------------------------------------------------------
 170 ;Status Register
 171
 172 SCG1            equ     128             ; System Clock Generator 1. 1=turn_off_SMCLK
 173 SCG0            equ     64              ; System Clock Generator 0. 1=turn_off_DCO
 174 OSCOFF          equ     32              ; Oscillator Off. 1=turn_off_LFXT1CLK
 175 CPUOFF          equ     16              ; CPU Off. 1=turn_off_CPU        (SR)
 176 GIE             equ     8               ; General Interrupt Enable       (SR)
 177
 178 ;----------------------------------------------------------------------------
 179 ; Special Function Register of MSP430x1xx Family, Byte Access
 180
 181 IE1             equ     000h            ; Interrupt Enable
 182 ACCVIE          equ     32              ; flash-access interrupt enable  (IE1.5)
 183 NMIIE           equ     16              ; NMI enable                     (IE1.4)
 184 OFIE            equ     2               ; Osc-fault-interrupt enable     (IE1.1)
 185 WDTIE           equ     1               ; Watchdog interrupt enable      (IE1.0)
 186
 187 IFG1            equ     002h            ; Interrupt Flag
 188 NMIIFG          equ     16              ; set via !RST/NMI pin           (IFG1.4)
 189 RSTIFG          equ     8               ; External reset interrupt flag  (IFG1.3)
 190 PORIFG          equ     4               ; Power-on-reset interrupt flag  (IFG1.2)
 191 OFIFG           equ     2               ; flag on oscillator fault       (IFG1.1)
 192 WDTIFG          equ     1               ; watchdog or security key violation (IFG1.0)
 193
 194 ME1             equ     004h            ; Modul Enable
 195
 196 ;MSP43012xx devices only, only for MSP43012xx devices.
 197
 198 IE2             equ     001h
 199 UTXIE0          equ     2               ; USART0 transmit int-enable bit (IE2.2)
 200 URXIE0          equ     1               ; USART0 receive int-enable bit  (IE2.1)
 201
 202 IFG2            equ     003h
 203 UTXIFG0         equ     2               ; USART0 and SPI transmit flag   (IFG2.1)
 204 URXIFG0         equ     1               ; USART0 and SPI receive flag    (IFG2.0)
 205
 206 ME2             equ     005h
 207 UTXE0           equ     2               ; USART0 transmit enable bit     (ME2.1)
 208 URXE0           equ     1               ; USART0 receive enable bit      (ME2.0)
 209 USPIE0          equ     1               ; SPI transmit+receive enable    (ME2.0)
 210
 211 ;----------------------------------------------------------------------------
 212 ; Digital I/O, Byte Access
 213
 214 P0IN            equ     010h            ; Leseregister (Pinzustand)
 215 P0OUT           equ     011h            ; Schreibregister (Latches)
 216 P0DIR           equ     012h            ; Richtungsregister
 217 P0IFG           equ     013h            ; Interrupt-Flags
 218 P0IES           equ     014h            ; Interrupf-Flankenwahl
 219 P0IE            equ     015h            ; Interrupt-Freigaben
 220
 221 P3IN            equ     018h            ; Input Register
 222 P3OUT           equ     019h            ; Output Register
 223 P3DIR           equ     01Ah            ; Direction Register
 224 P3SEL           equ     01Bh            ; Function select
 225
 226 P4IN            equ     01Ch            ; Input Register
 227 P4OUT           equ     01Dh            ; Output Register
 228 P4DIR           equ     01Eh            ; Direction Register
 229 P4SEL           equ     01Fh            ; Function select
 230
 231 P1IN            equ     020h            ; Input Register
 232 P1OUT           equ     021h            ; Output Register
 233 P1DIR           equ     022h            ; Direction Register
 234 P1IFG           equ     023h            ; Interrupt Flags
 235 P1IES           equ     024h            ; Interrupt Edge select
 236 P1IE            equ     025h            ; Interrupt enable
 237 P1SEL           equ     026h            ; Function select
 238
 239 P2IN            equ     028h            ; Input Register
 240 P2OUT           equ     029h            ; Output Register
 241 P2DIR           equ     02Ah            ; Direction Register
 242 P2IFG           equ     02Bh            ; Interrupt Flags
 243 P2IES           equ     02Ch            ; Interrupt Edge select
 244 P2IE            equ     02Dh            ; Interrupt enable
 245 P2SEL           equ     02Eh            ; Function select
 246
 247 P5IN            equ     030h            ; Input Register
 248 P5OUT           equ     031h            ; Output Register
 249 P5DIR           equ     032h            ; Direction Register
 250 P5SEL           equ     033h            ; Function select
 251
 252 P6IN            equ     034h            ; Input Register
 253 P6OUT           equ     035h            ; Output Register
 254 P6DIR           equ     036h            ; Direction Register
 255 P6SEL           equ     037h            ; Function select
 256
 257 ;----------------------------------------------------------------------------
 258 ; LCD-Interface
 259
 260 LCDCTL          equ     030h            ; Steuerung
 261 LCD_Start       equ     031h            ; Startadresse
 262 LCD_Stop        equ     03fh            ; Endadresse
 263 __TMP           set     1               ; Einzeldefinitionen
 264                 rept    9
 265 LCD{"\{__TMP}"} equ     030h+__TMP
 266 __TMP           set     __TMP+1
 267                 endm
 268                 rept    6
 269 LCD1{"\{__TMP-10}"} equ 030h+__TMP
 270 __TMP           set     __TMP+1
 271                 endm
 272 ;----------------------------------------------------------------------------
 273 ; Timer
 274
 275 BTCTL           equ     040h            ; Basis-Steuerregister Timer 1
 276
 277 TCCTL           equ     042h
 278 TCPLD           equ     043h            ; Vorladewert
 279 TCDAT           equ     044h            ; Z\84hlwert
 280
 281 BTCNT1          equ     046h            ; Z\84hlregister
 282 BTCNT2          equ     047h
 283
 284 TPCTL           equ     04Bh            ; Timer/Port Steuerregister
 285 TPCNT1          equ     04Ch            ; Z\84hlregister
 286 TPCNT2          equ     04Dh
 287 TPD             equ     04Eh            ; Datenregister
 288 TPE             equ     04Fh            ; Freigaberegister
 289
 290 ;----------------------------------------------------------------------------
 291 ; Taktgenerator
 292
 293 SCFI0           equ     050h            ; Integrator
 294 SCFI1           equ     051h
 295 SCFQCTL         equ     052h            ; Multiplikator Quarzfrequenz
 296 CBCTL           equ     053h            ; Puffersteuerung
 297
 298 ;----------------------------------------------------------------------------
 299 ; EPROM Control Register, Byte Access
 300
 301 EPCTL           equ     054h            ; EPROM-Steuerung
 302
 303 ;----------------------------------------------------------------------------
 304 ; Basic Clock Registers, Byte Access
 305
 306 DCOCTL          equ     056h
 307 DCO2            equ     128             ;DCO freq select, see RSELx     (DCOCTL.7)
 308 DCO1            equ     64              ;                               (DCOCTL.6)
 309 DCO0            equ     32              ;                               (DCOCTL.5)
 310 MOD4            equ     16              ;Modulator selection            (DCOCTL.4)
 311 MOD3            equ     8               ;                               (DCOCTL.3)
 312 MOD2            equ     4               ;                               (DCOCTL.2)
 313 MOD1            equ     2               ;                               (DCOCTL.1)
 314 MOD0            equ     1               ;                               (DCOCTL.0)
 315
 316 BCSCTL1         equ     057h
 317 XT2OFF          equ     128             ; XT2 off. Turn off XT2 oscil    (BCSCTL1.7)
 318 XTS             equ     64              ; LFXT1 mode. 0=LowFreq,1=HiFreq (BCSCTL1.6)
 319 DIVA1           equ     32              ; Divider for ACLK.              (BCSCTL1.5)
 320 DIVA0           equ     16              ; 00=/1, 01=/2, 10=/4, 11=/8     (BCSCTL1.4)
 321 XT5V            equ     8               ; Unused. Always reset to zero   (BCSCTL1.3)
 322 RSEL2           equ     4               ; Resistor select. internal R    (BCSCTL1.2)
 323 RSEL1           equ     2               ; lowest R=0                     (BCSCTL1.1)
 324 RSEL0           equ     1               ;                                (BCSCTL1.0)
 325 RSEL_7          equ     7               ;                                (BCSCTL1.0-2)
 326 RSEL_6          equ     6               ;                                (BCSCTL1.0-2)
 327 RSEL_5          equ     5               ;                                (BCSCTL1.0-2)
 328 RSEL_4          equ     4               ;                                (BCSCTL1.0-2)
 329 RSEL_3          equ     3               ;                                (BCSCTL1.0-2)
 330 RSEL_2          equ     2               ;                                (BCSCTL1.0-2)
 331 RSEL_1          equ     1               ;                                (BCSCTL1.0-2)
 332 RSEL_0          equ     0               ;                                (BCSCTL1.0-2)
 333
 334 BCSCTL2         equ     058h
 335 SELM_3          equ     128+64          ; Select MCLK. 11=LFXT1CLK       (BCSCTL2.6.7)
 336 SELM_2          equ     128             ; MCLK 10=XT2CLK or LFXT1CLK     (BCSCTL2.6.7)
 337 SELM_1          equ     64              ; Select MCLK. 01=DCOCLK         (BCSCTL2.6.7)
 338 SELM_0          equ     0               ; Select MCLK. 00=DCOCLK         (BCSCTL2.6.7)
 339 SELM1           equ     128             ; Select MCLK. 00=01=DCOCLK      (BCSCTL2.7)
 340 SELM0           equ     64              ; 10=XT2CLK or LFXT1CLK=11       (BCSCTL2.6)
 341 DIVM1           equ     32              ; Divider for MCLK,              (BCSCTL2.5)
 342 DIVM0           equ     16              ; 00=/1, 01=/2, 10=/4, 11=/8     (BCSCTL2.4)
 343 SELS            equ     8               ; Select SMCLK 0=DCOCLK,1=XT2CLK (BCSCTL2.3)
 344 DIVS1           equ     4               ; Divider for SMCLK,             (BCSCTL2.2)
 345 DIVS0           equ     2               ; 00=/1, 01=/2, 10=/4, 11=/8     (BCSCTL2.1)
 346 DCOR            equ     1               ; DCO resistor. 0=intern,1=extn  (BCSCTL2.0)
 347
 348 ;----------------------------------------------------------------------------
 349 ; Comparator_A Registers, Byte Access
 350
 351 CACTL1          equ     059h            ; Comparator A control register 1
 352 CACTL2          equ     05Ah            ; Comparator A control register 2
 353 CAPD            equ     05Bh            ; Comparator A port disable
 354
 355 ;----------------------------------------------------------------------------
 356 ; PWM
 357
 358 PWMCTL          equ     058h            ; Z\84hlwert
 359 PWMDTB          equ     059h            ; Pulsweite (Puffer)
 360 PWMDTR          equ     05Ah            ; Pulsweite
 361 PWMCNT          equ     05Bh            ; Steuerung
 362
 363 ;----------------------------------------------------------------------------
 364 ; USART 0
 365
 366 U0CTL           equ     070h
 367 U0TCTL          equ     071h
 368 U0RCTL          equ     072h
 369 U0MCTL          equ     073h
 370 U0BR0           equ     074h
 371 U0BR1           equ     075h
 372 U0RXBUF         equ     076h
 373 U0TXBUF         equ     077h
 374
 375 ;----------------------------------------------------------------------------
 376 ; USART 1
 377
 378 U1CTL           equ     078h
 379 U1TCTL          equ     079h
 380 U1RCTL          equ     07Ah
 381 U1MCTL          equ     07Bh
 382 U1BR0           equ     07Ch
 383 U1BR1           equ     07Dh
 384 U1RXBUF         equ     07Eh
 385 U1TXBUF         equ     07Fh
 386
 387 ;----------------------------------------------------------------------------
 388 ; USART Register Bits
 389
 390 FE              equ     128             ; Framing error (low stop bit)   (UxRCTL.7)
 391 PE              equ     64              ; Parity error (PE=0 if PENA=0)  (UxRCTL.6)
 392 OE              equ     32              ; Overrun error (buffer overrun) (UxRCTL.5)
 393 BRK             equ     16              ; Break detect flag              (UxRCTL.4)
 394 URXEIE          equ     8               ; Rec err chars sets URXIFG)     (UxRCTL.3)
 395 URXWIE          equ     4               ; Rec wakeup int-enable (URXIFG) (UxRCTL.2)
 396 RXWAKE          equ     2               ; Rec wakeup flag                (UxRCTL.1)
 397 RXERR           equ     1               ; Rec error flag (FE,PE,OE,BRK)  (UxRCTL.0)
 398
 399 CKPL            equ     64              ; Clock polarity 0=UCLKI=UCLK    (UxTCTL.6)
 400 SSEL1           equ     32              ; Source 00=UCLKI, 01=ACLK       (UxTCTL.5)
 401 SSEL0           equ     16              ; Source 10=SMCLKI, 11=SMCLK     (UxTCTL.4)
 402 URXSE           equ     8               ; Receive start-edge, 1=enabled  (UxTCTL.3)
 403 TXWAKE          equ     4               ; Transmitter wake, 0=data,1=adr (UxTCTL.2)
 404 TXEPT           equ     1               ; Transmitter empty flag         (UxTCTL.0)
 405
 406 PENA            equ     128             ; Parity enable, 1=enabled       (UxCTL.7)
 407 PEV             equ     64              ; Parity select, 1=even,0=odd    (UxCTL.6)
 408 SPB             equ     32              ; Stop bit, 0=1stop,1=2stop      (UxCTL.5)
 409 CHAR            equ     16              ; Char length, 0=7bit,1=8bit     (UxCTL.4)
 410 LISTEN          equ     8               ; Listen enable, 1=loopback->RX  (UxCTL.3)
 411 SYNC            equ     4               ; synch mode, 0=USART,1=SPI      (UxCTL.2)
 412 MM              equ     2               ; Multiprocessor, 1=use_protocol (UxCTL.1)
 413 SWRST           equ     1               ; software reset, 1=held_reset   (UxCTL.0)
 414
 415 ;----------------------------------------------------------------------------
 416 ; ADC12 low bytes
 417
 418 ADC12MCTL0      equ     080h
 419 ADC12MCTL1      equ     081h
 420 ADC12MCTL2      equ     082h
 421 ADC12MCTL3      equ     083h
 422 ADC12MCTL4      equ     084h
 423 ADC12MCTL5      equ     085h
 424 ADC12MCTL6      equ     086h
 425 ADC12MCTL7      equ     087h
 426 ADC12MCTL8      equ     088h
 427 ADC12MCTL9      equ     089h
 428 ADC12MCTL10     equ     08Ah
 429 ADC12MCTL11     equ     08Bh
 430 ADC12MCTL12     equ     08Ch
 431 ADC12MCTL13     equ     08Dh
 432 ADC12MCTL14     equ     08Eh
 433 ADC12MCTL15     equ     08Fh
 434
 435 ;----------------------------------------------------------------------------
 436 ; LCD Registers
 437
 438 LCDC            equ     090h
 439 __TMP           set     1               ; Einzeldefinitionen
 440                 rept    19
 441 LCDmemory{"\{__TMP}"} equ     LCDC+__TMP
 442 __TMP           set     __TMP+1
 443                 endm
 444
 445 ;----------------------------------------------------------------------------
 446 ; A/D-Wandler, Word Access
 447
 448 AIN             equ     0110h           ; Eingaberegister
 449 AEN             equ     0112h           ; Eingabefreigaben
 450 ACTL            equ     0114h           ; Steuerung
 451 ADAT            equ     0118h           ; Daten
 452
 453 ;----------------------------------------------------------------------------
 454 ; Timer_B Interrupt Vector, Word Access
 455
 456 TBIV            equ     011Eh
 457
 458 ;----------------------------------------------------------------------------
 459 ; Watchdog/Timer, Word Access
 460
 461 WDTCTL          equ     0120h
 462 WDTHOLD         equ     128             ; Watchdog timer hold. 1=stopped (WDTCTL.6)
 463 WDTNMIES        equ     64              ; NMI edge select 0=rise,1=fall  (WDTCTL.6)
 464 WDTNMI          equ     32              ; NMI pin select, 0=!reset,1=NMI (WDTCTL.5)
 465 WDTTMSEL        equ     16              ; mode select 0=watchdog,1=timer (WDTCTL.4)
 466 WDTCNTCL        equ     8               ; Counter clear, 1=clear_counter (WDTCTL.3)
 467 WDTSSEL         equ     4               ; Source select, 0=SMCLK,1=ACLK  (WDTCTL.2)
 468 WDTIS1          equ     2               ; Watchdog timer interval select (WDTCTL.1)
 469 WDTIS0          equ     1               ; 00=32768,01=8192,10=512,11=64  (WDTCTL.0)
 470
 471 ;----------------------------------------------------------------------------
 472 ; Timer_A Interrupt Vector, Word Access
 473
 474 TAIV            equ     012Eh
 475
 476 ;----------------------------------------------------------------------------
 477 ; Flash Control, Word Access
 478
 479 FCTL1           equ     0128h
 480 FCTL2           equ     012Ah
 481 FCTL3           equ     012Ch
 482
 483 ;----------------------------------------------------------------------------
 484 ; Hardware Multiplier, Word Access
 485
 486 MPY             equ     0130h           ; Multiply unsigned
 487 MPYS            equ     0132h           ; Multiply signed
 488 MAC             equ     0134h           ; MPY+ACC
 489 MACS            equ     0136h           ; MPYS+ACC
 490 OP2             equ     0138h           ; Second Operand
 491 ResLo           equ     013Ah           ; Result low word
 492 ResHi           equ     013Ch           ; Result high word
 493 SumExt          equ     013Eh           ; Sum extend
 494
 495 ;----------------------------------------------------------------------------
 496 ; ADC12 high bytes, Word Access
 497
 498 ADC12MEM0       equ     0140h
 499 ADC12MEM1       equ     0142h
 500 ADC12MEM2       equ     0144h
 501 ADC12MEM3       equ     0146h
 502 ADC12MEM4       equ     0148h
 503 ADC12MEM5       equ     014Ah
 504 ADC12MEM6       equ     014Ch
 505 ADC12MEM7       equ     014Eh
 506 ADC12MEM8       equ     0150h
 507 ADC12MEM9       equ     0152h
 508 ADC12MEM10      equ     0154h
 509 ADC12MEM11      equ     0156h
 510 ADC12MEM12      equ     0158h
 511 ADC12MEM13      equ     015Ah
 512 ADC12MEM14      equ     015Ch
 513 ADC12MEM15      equ     015Eh
 514
 515 ;----------------------------------------------------------------------------
 516 ; Timer_A Registers, Word Access
 517
 518 TACTL           equ     0160h
 519 CCTL0           equ     0162h
 520 CCTL1           equ     0164h
 521 CCTL2           equ     0166h
 522 CCTL3           equ     0168h
 523 CCTL4           equ     016Ah
 524 TAR             equ     0170h
 525 CCR0            equ     0172h
 526 CCR1            equ     0174h
 527 CCR2            equ     0176h
 528 CCR3            equ     0178h
 529 CCR4            equ     017Ah
 530
 531 ;----------------------------------------------------------------------------
 532 ; Timer_B Registers, Word Access
 533
 534 TBCTL           equ     0180h
 535 TBCCTL0         equ     0182h
 536 TBCCTL1         equ     0184h
 537 TBCCTL2         equ     0186h
 538 TBCCTL3         equ     0188h
 539 TBCCTL4         equ     018Ah
 540 TBCCTL5         equ     018Ch
 541 TBCCTL6         equ     018Eh
 542 TBR             equ     0190h
 543 TBCCR0          equ     0192h
 544 TBCCR1          equ     0194h
 545 TBCCR2          equ     0196h
 546 TBCCR3          equ     0198h
 547 TBCCR4          equ     019Ah
 548 TBCCR5          equ     019Ch
 549 TBCCR6          equ     019Eh
 550
 551 ;----------------------------------------------------------------------------
 552 ; ADC12 Registers, Byte and Word Access
 553
 554 ADC12CTL0       equ     01A0h
 555 ADC12CTL1       equ     01A2h
 556 ADC12FG         equ     01A4h
 557 ADC12IE         equ     01A6h
 558
 559 ;----------------------------------------------------------------------------
 560
 561                 endif                   ; von IFDEF...
 562                 restore                 ; wieder erlauben