V205; added MSP-EXP430FR2355.

[fast-forth/master.git] / CHIPSTICK_FR2433.asm

diff --git a/CHIPSTICK_FR2433.asm b/CHIPSTICK_FR2433.asm
index f8179fc..a81fc99 100644 (file)
--- a/CHIPSTICK_FR2433.asm
+++ b/CHIPSTICK_FR2433.asm
@@ -255,7 +255,7 @@ NWAITS            = 1
             MOV     #200Fh,&CSCTL2      ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Fh
                                         ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured :  MHz
 ; =====================================
-            MOV     #1,X
+            MOV     #4,X
 
     .ELSEIF FREQUENCY = 0.5
 
@@ -270,7 +270,7 @@ NWAITS            = 1
             MOV     #100Fh,&CSCTL2      ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
                                         ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured :  MHz
 ; =====================================
-            MOV     #2,X
+            MOV     #8,X
 
     .ELSEIF FREQUENCY = 1
 
@@ -285,7 +285,7 @@ NWAITS            = 1
 ;            MOV     #001Fh,&CSCTL2        ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
                                         ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
 ; =====================================
-            MOV     #4,X
+            MOV     #16,X
 
     .ELSEIF FREQUENCY = 2
 
@@ -300,7 +300,7 @@ NWAITS            = 1
             MOV     #003Dh,&CSCTL2        ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
                                         ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured :  MHz
 ; =====================================
-            MOV     #8,X
+            MOV     #32,X
 
     .ELSEIF FREQUENCY = 4
 
@@ -317,7 +317,7 @@ NWAITS            = 1
 ;            MOV     #007Ah,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
                                         ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
 ; =====================================
-            MOV     #16,X
+            MOV     #64,X
 
     .ELSEIF FREQUENCY = 8
 
@@ -345,7 +345,7 @@ NWAITS            = 1
                                         ; fCOCLKDIV = 32768 x (252+1) = 8.290 MHz  <============ why ?
 
 ; =====================================
-            MOV     #32,X
+            MOV     #128,X
 
     .ELSEIF FREQUENCY = 16
 
@@ -362,32 +362,30 @@ NWAITS            = 1
             MOV     #01E9h,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
                                         ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
 ; =====================================
-            MOV     #64,X
+            MOV     #256,X
 
     .ELSEIF
     .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
     .ENDIF
 
     .IFDEF LF_XTAL
-;            MOV     #0000h,&CSCTL3      ; FLL select XT1, FLLREFDIV=0 (default value)
+;           MOV     #0000h,&CSCTL3      ; FLL select XT1, FLLREFDIV=0 (default value)
             MOV     #0000h,&CSCTL4      ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
     .ELSE
             BIS     #0010h,&CSCTL3      ; FLL select REFCLOCK
 ;           MOV     #0100h,&CSCTL4      ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value)
     .ENDIF
 
-
-            BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV with preserving a pending request for DEEP_RST
-            CMP #2,&SAVE_SYSRSTIV   ; POWER ON ?
-            JZ      ClockWaitX      ; yes : wait 800ms to stabilize power source
-            .word   0359h           ; no  : RRUM #1,X --> wait still 400 ms...
+            BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
+;            CMP #2,&SAVE_SYSRSTIV   ; POWER ON ?
+;            JZ      ClockWaitX      ; yes
+;            .word   0759h           ; no  RRUM #2,X --> wait only 125 ms
+ClockWaitX  MOV     #5209,Y         ; wait 0.5s before starting after POR
                                     ;       ...because FLL lock time = 280 ms
-
-ClockWaitX  MOV     #-1,Y           ;
-ClockWaitY  SUB     #1,Y            ; 3 cycles loop
-            JNZ     ClockWaitY      ; 65535 = 196605 cycles delay = 200ms @ 1MHz
-            SUB     #1,X            ;
-            JNZ     ClockWaitX      ;
+ClockWaitY  SUB     #1,Y            ;1
+            JNZ     ClockWaitY      ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
+            SUB     #1,X            ; x 32 @ 1 MHZ = 500ms
+            JNZ     ClockWaitX      ; time to stabilize power source ( 500ms )
 
 ;WAITFLL     BIT #300h,&CSCTL7         ; wait FLL lock
 ;            JNZ WAITFLL