V309

[fast-forth/master.git] / inc / MSP430FR5969.inc

diff --git a/inc/MSP430FR5969.inc b/inc/MSP430FR5969.inc
index fed66a4..1b7f55b 100644 (file)
--- a/inc/MSP430FR5969.inc
+++ b/inc/MSP430FR5969.inc
@@ -26,7 +26,7 @@ DEVICE = "MSP430FR5969"
 ; ----------------------------------------------
 PAGESIZE        .equ 512         ; MPU unit
 ; ----------------------------------------------
-; BSL                         
+; BSL
 ; ----------------------------------------------
 BSL             .equ 1000h
 ; ----------------------------------------------
@@ -65,7 +65,7 @@ BSL_SIG2        .equ 0FF86h      ;
 JTAG_PASSWORD   .equ 0FF88h      ; 256 bits max
 IPE_SIG_VALID   .equ 0FF88h      ; one word
 IPE_STR_PTR_SRC .equ 0FF8Ah      ; one word
-I2CSLA0         .equ 0FFA2h      ; UCBxI2COA0 default value address 
+I2CSLA0         .equ 0FFA2h      ; UCBxI2COA0 default value address
 I2CSLA1         .equ 0FFA4h      ; UCBxI2COA1 default value address
 I2CSLA2         .equ 0FFA6h      ; UCBxI2COA2 default value address
 I2CSLA3         .equ 0FFA8h      ; UCBxI2COA3 default value address
@@ -267,7 +267,7 @@ P1SELC      .equ PA_SFR + 16h    ; Port 1 SELection Complement
 P1IES       .equ PA_SFR + 18h    ; Port 1 Interrupt Edge Select
 P1IE        .equ PA_SFR + 1Ah    ; Port 1 Interrupt Enable
 P1IFG       .equ PA_SFR + 1Ch    ; Port 1 Interrupt FlaG
-P1IV        .equ PA_SFR + 0Eh    ; Port 1 Interrupt Vector word 
+P1IV        .equ PA_SFR + 0Eh    ; Port 1 Interrupt Vector word
 
 P2IN        .equ PA_SFR + 01h    ; Port 2 INput
 P2OUT       .equ PA_SFR + 03h    ; Port 2 OUTput
@@ -279,7 +279,7 @@ P2SELC      .equ PA_SFR + 17h    ; Port 2 SELection Complement
 P2IES       .equ PA_SFR + 19h    ; Port 2 Interrupt Edge Select
 P2IE        .equ PA_SFR + 1Bh    ; Port 2 Interrupt Enable
 P2IFG       .equ PA_SFR + 1Dh    ; Port 2 Interrupt FlaG
-P2IV        .equ PA_SFR + 1Eh    ; Port 2 Interrupt Vector word 
+P2IV        .equ PA_SFR + 1Eh    ; Port 2 Interrupt Vector word
 
 ; ----------------------------------------------------------------------
 ; POWER ON RESET AND INITIALIZATION : PORT3/4
@@ -306,7 +306,7 @@ P3SELC      .equ PB_SFR + 16h    ; Port 3 Complement Selection
 P3IES       .equ PB_SFR + 18h    ; Port 3 Interrupt Edge Select
 P3IE        .equ PB_SFR + 1Ah    ; Port 3 Interrupt Enable
 P3IFG       .equ PB_SFR + 1Ch    ; Port 3 Interrupt Flag
-P3IV        .equ PB_SFR + 0Eh    ; Port 3 Interrupt Vector word 
+P3IV        .equ PB_SFR + 0Eh    ; Port 3 Interrupt Vector word
 
 P4IN        .equ PB_SFR + 01h    ; Port 4 Input */
 P4OUT       .equ PB_SFR + 03h    ; Port 4 Output
@@ -318,7 +318,7 @@ P4SELC      .equ PB_SFR + 17h    ; Port 4 Complement Selection
 P4IES       .equ PB_SFR + 19h    ; Port 4 Interrupt Edge Select
 P4IE        .equ PB_SFR + 1Bh    ; Port 4 Interrupt Enable
 P4IFG       .equ PB_SFR + 1Dh    ; Port 4 Interrupt Flag
-P4IV        .equ PB_SFR + 1Eh    ; Port 4 Interrupt Vector word 
+P4IV        .equ PB_SFR + 1Eh    ; Port 4 Interrupt Vector word
 
 ; ----------------------------------------------------------------------
 ; POWER ON RESET AND INITIALIZATION : PORTJ
@@ -383,14 +383,14 @@ RES3      .equ MPY_SFR + 2Ah    ; 32x32-bit result 3 */
 MPY32CTL0 .equ MPY_SFR + 2Ch    ; MPY32 control register 0
 
 
-MPUCTL0     .equ MPU_SFR + 00h  ; MPU control 0             
-MPUCTL1     .equ MPU_SFR + 02h  ; MPU control 1             
-MPUSEGB2    .equ MPU_SFR + 04h  ; MPU Segmentation Border 2 
-MPUSEGB1    .equ MPU_SFR + 06h  ; MPU Segmentation Border 1 
-MPUSAM      .equ MPU_SFR + 08h  ; MPU access management     
-MPUIPC0     .equ MPU_SFR + 0Ah  ; MPU IP control 0                      
-MPUIPSEGB2  .equ MPU_SFR + 0Ch  ; MPU IP Encapsulation Segment Border 2 
-MPUIPSEGB1  .equ MPU_SFR + 0Eh  ; MPU IP Encapsulation Segment Border 1 
+MPUCTL0     .equ MPU_SFR + 00h  ; MPU control 0
+MPUCTL1     .equ MPU_SFR + 02h  ; MPU control 1
+MPUSEGB2    .equ MPU_SFR + 04h  ; MPU Segmentation Border 2
+MPUSEGB1    .equ MPU_SFR + 06h  ; MPU Segmentation Border 1
+MPUSAM      .equ MPU_SFR + 08h  ; MPU access management
+MPUIPC0     .equ MPU_SFR + 0Ah  ; MPU IP control 0
+MPUIPSEGB2  .equ MPU_SFR + 0Ch  ; MPU IP Encapsulation Segment Border 2
+MPUIPSEGB1  .equ MPU_SFR + 0Eh  ; MPU IP Encapsulation Segment Border 1
 
 
     .IFDEF UCA0_TERM
@@ -437,7 +437,7 @@ TERM_STATW      .equ eUSCI_B0_SFR + 08h     ; USCI_B0 Status Word
 TERM_RXBUF      .equ eUSCI_B0_SFR + 0Ch     ; USCI_B0 Receive Buffer 8
 TERM_TXBUF      .equ eUSCI_B0_SFR + 0Eh     ; USCI_B0 Transmit Buffer 8
 TERM_I2COA0     .equ eUSCI_B0_SFR + 14h     ; USCI_B0 I2C Own Address 0
-TERM_ADDRX      .equ eUSCI_B0_SFR + 1Ch     ; USCI_B0  Received Address Register 
+TERM_ADDRX      .equ eUSCI_B0_SFR + 1Ch     ; USCI_B0  Received Address Register
 TERM_I2CSA      .equ eUSCI_B0_SFR + 20h     ; USCI_B0 I2C Slave Address
 TERM_IE         .equ eUSCI_B0_SFR + 2Ah     ; USCI_B0 Interrupt Enable
 TERM_IFG        .equ eUSCI_B0_SFR + 2Ch     ; USCI_B0 Interrupt Flags Register