V 3.2

[fast-forth/master.git] / inc / MSP430FR5994.inc

diff --git a/inc/MSP430FR5994.inc b/inc/MSP430FR5994.inc
index 575c14a..f873701 100644 (file)
--- a/inc/MSP430FR5994.inc
+++ b/inc/MSP430FR5994.inc
@@ -563,3 +563,16 @@ SD_TXBUF        .equ eUSCI_B0_SFR + 0Eh    ; eUSCI_B0 Transmit Buffer 8
 SD_IFG          .equ eUSCI_B0_SFR + 2Ch    ; eUSCI_B0 Interrupt Flags Register
     .ENDIF ;UCB0_SD
 
+    .IFDEF UCB0_TERM
+I2CTERM_CTLW0       .equ eUSCI_B0_SFR + 00h    ; USCI_B0 Control Word Register 0
+I2CTERM_CTLW1       .equ eUSCI_B0_SFR + 02h    ; USCI_B0 Control Word Register 1
+I2CTERM_BRW         .equ eUSCI_B0_SFR + 06h    ; USCI_B0 Baud Word Rate 0
+I2CTERM_RXBUF       .equ eUSCI_B0_SFR + 0Ch    ; USCI_B0 Receive Buffer 8
+I2CTERM_TXBUF       .equ eUSCI_B0_SFR + 0Eh    ; USCI_B0 Transmit Buffer 8
+I2CTERM_I2COA0      .equ eUSCI_B0_SFR + 14h    ; USCI_B0 I2C Own Address 0
+I2CTERM_ADDRX       .equ eUSCI_B0_SFR + 1Ch    ; USCI_B0  Received Address Register 
+I2CTERM_I2CSA       .equ eUSCI_B0_SFR + 20h    ; USCI_B0 I2C Slave Address
+I2CTERM_IE          .equ eUSCI_B0_SFR + 2Ah    ; USCI_B0 Interrupt Enable
+I2CTERM_IFG         .equ eUSCI_B0_SFR + 2Ch    ; USCI_B0 Interrupt Flags Register
+I2CTERMVEC          .equ 0FFE0h      ; interrupt vector for eUSCI_B0
+    .ENDIF ;UCB0_TERM