Merge branch 'debugging' into net-mjpeg

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/dctmem2cont.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/dctmem2cont.vhd
index 69ffb70..f50492f 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/dctmem2cont.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/dctmem2cont.vhd
@@ -46,7 +46,8 @@ entity dctmem2cont is
       kready2  : in std_logic;
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(15 downto 0);
-      error     : out std_logic
+      error    : out std_logic;
+      startgen : in std_logic
    );
 end;
 
@@ -78,7 +79,7 @@ begin
     yram1 : syncram generic map(tech => memtech, abits => 6, dbits => 16)
                 port map( clk, m1address, m1datain, m1dataout, m1enable, m1write);
 
-comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout)
+comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout, startgen)
       variable v : control_reg;   
       variable vkready1 : std_logic;
       variable verror : std_logic;
@@ -202,7 +203,7 @@ comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout)
    end if;
    
 -- reset part
-   if rst = '0' then
+   if rst = '0' or startgen = '1' then
        v.swf := mem0;
        v.swb := mem0;
        v.mem0state := empty;

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
index 423acf6..22350f4 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
@@ -1107,6 +1107,8 @@ end if;
        v.hreg.rdoffset := '0';
        v.hreg.getval := '0';
        v.hreg.rdval := '0';
+       v.hreg.hselff := '0';
+       v.hreg.hreadyff := '0';
        v.fetch_state := memwait;
        v.dec_state := standby;
        v.fifo_rp := (others => '0');

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffdctycc.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffdctycc.vhd
index 0a70c9f..54ef50f 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffdctycc.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffdctycc.vhd
@@ -110,26 +110,26 @@ begin
    port map(rst => rst, clk => clk, kready1 => kready1, kstrobe1 => kstrobe1, kaddress1 => kaddress1, kdata1 => kdata1, kready2 => kready2,
             kstrobe2 => kstrobe2, kdata2 => kdata2, error =>error(0), samp_fact => jpg_setting.samp_fact,
             kstrobeq1 => kstrobeq, kdataq1 => kdataq1, kdataq2 => kdataq2,
-            kaddq => kaddq, krdq => krdq, krddataq => krddataq);
+            kaddq => kaddq, krdq => krdq, krddataq => krddataq, startgen => startgen);
    
    dct1 : idct1
    port map(rst => rst, clk => clk, ready1 => kready2, strobe1 => kstrobe2, coeffin => kdata2,
-            quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3);
+            quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3, startgen => startgen);
    
    dctmem2 : dctmem2cont
    generic map(memtech => memtech)
    port map(rst => rst, clk => clk, kready1 => kready3, kstrobe1 => kstrobe3, kdata1 => kdata3,
-            kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1) );
+            kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1), startgen => startgen);
    
    dct2 : idct2
    port map(rst => rst, clk => clk, ready1 => kready4, strobe1 => kstrobe4, coeffin => kdata4,
-            outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5); 
+            outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5, startgen => startgen); 
    
    yccmem : yccmemcont
    generic map(memtech => memtech)
    port map(rst => rst, clk => clk, kready1 => kready5, kstrobe1 => kstrobe5, kdata1 => kdata5,
             kready2 => kready6, kstrobe2 => kstrobe6, kdata2 => kdata6, samp_fact => jpg_setting.samp_fact,
-            error => error(2));
+            error => error(2), startgen => startgen);
    
    ycb : yccrgb
    generic map(memtech => memtech, hirq => hirq, mhindex => mhindex,

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
index cb05470..356017b 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
@@ -54,7 +54,9 @@ entity huffmemcont is
       
       kaddq : in std_logic_vector(7 downto 0);
       krdq : in std_logic;
-      krddataq : out std_logic_vector(7 downto 0)
+      krddataq : out std_logic_vector(7 downto 0);
+      
+      startgen : in std_logic
    );
 end;
  
@@ -120,7 +122,7 @@ begin
     qram  : syncram generic map(tech => memtech, abits => 8, dbits => 8)
                 port map( clk, qaddress, qdatain, qdataout, qenable, qwrite);
     
-comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq)
+comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq, samp_fact, startgen)
       variable v : control_reg;   
       variable vkready1 : std_logic;
       variable verror : std_logic;
@@ -331,7 +333,7 @@ debug_bcountup <= bcountup;
 
 
 -- reset part
-   if rst = '0' then
+   if rst = '0' or startgen= '1' then
        v.swf := mem0;
        v.swb := mem0;
        v.mem0state := fill0;

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct1.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct1.vhd
index 921b79c..5b120a4 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct1.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct1.vhd
@@ -37,7 +37,8 @@ entity idct1 is
            quantin : in  std_logic_vector (7 downto 0);
            outdata : out  std_logic_vector (15 downto 0);
            ready2 : in std_logic;
-           strobe2 : out std_logic
+           strobe2 : out std_logic;
+           startgen : in std_logic
            );
 end idct1;
 
@@ -168,7 +169,7 @@ signal r, rin : all_reg;
 
 begin
 
-comb : process(r, rst, strobe1, ready2, coeffin, quantin)
+comb : process(r, rst, strobe1, ready2, coeffin, quantin, startgen)
        variable v : all_reg;
        variable node0 : std_logic_vector(20 downto 0);
        variable node1 : node1_array;
@@ -295,7 +296,7 @@ begin
    end if;
 
 -- reset part
-   if rst = '0' then
+   if rst = '0' or startgen = '1' then
        v.data_reg.inreg := (others => '0');
        for i in 0 to 7 loop
           v.data_reg.accumulator(i) := (others => '0');

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd
index 26ebf7c..75027be 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd
@@ -36,7 +36,8 @@ entity idct2 is
            coeffin : in  std_logic_vector (15 downto 0);
            outdata : out  std_logic_vector (7 downto 0);
            ready2 : in std_logic;
-           strobe2 : out std_logic
+           strobe2 : out std_logic;
+           startgen : in std_logic
            );
 end idct2;
 
@@ -184,7 +185,7 @@ signal r, rin : all_reg;
 
 begin
 
-comb : process(r, rst, strobe1, ready2, coeffin)
+comb : process(r, rst, strobe1, ready2, coeffin, startgen)
        variable v : all_reg;
        variable node1 : node1_array;
        variable node2 : node2_array;
@@ -316,7 +317,8 @@ begin
    end if;
    
 -- reset part
-   if rst = '0' then
+   if rst = '0' or startgen = '1' then
+       v.data_reg.inreg := (others => '0');
        for i in 0 to 7 loop
           v.data_reg.accumulator(i) := (others => '0');
           v.data_reg.result_reg(i) := (others => '0');

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
index e23a78b..21dc7d9 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
@@ -120,15 +120,14 @@ component huffmemcont is
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(11 downto 0);
       error    : out std_logic;
-
       samp_fact : in std_logic;
       kstrobeq1 : in std_logic;
       kdataq1   : in std_logic_vector(7 downto 0);
-      kdataq2   : out std_logic_vector(7 downto 0);
-      
+      kdataq2   : out std_logic_vector(7 downto 0);      
       kaddq : in std_logic_vector(7 downto 0);
       krdq : in std_logic;
-      krddataq : out std_logic_vector(7 downto 0)
+      krddataq : out std_logic_vector(7 downto 0);
+      startgen : in std_logic
    );
 end component;
 
@@ -164,7 +163,8 @@ component dctmem2cont is
       kready2  : in std_logic;
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(15 downto 0);
-      error     : out std_logic
+      error     : out std_logic;
+      startgen  : in std_logic
    );
 end component;
 
@@ -177,7 +177,8 @@ component idct1 is
            quantin : in  std_logic_vector (7 downto 0);
            outdata : out  std_logic_vector (15 downto 0);
            ready2 : in std_logic;
-           strobe2 : out std_logic
+           strobe2 : out std_logic;
+           startgen : in std_logic
            );
 end component;
 
@@ -189,7 +190,8 @@ component idct2 is
            coeffin : in  std_logic_vector (15 downto 0);
            outdata : out  std_logic_vector (7 downto 0);
            ready2 : in std_logic;
-           strobe2 : out std_logic
+           strobe2 : out std_logic;
+           startgen : in std_logic
            );
 end component;
 
@@ -240,7 +242,8 @@ component yccmemcont
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(23 downto 0);
       samp_fact : in std_logic;
-      error     : out std_logic
+      error     : out std_logic;
+      startgen  : in std_logic
    );
 end component;
 

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/yccmemcont.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/yccmemcont.vhd
index 713fac5..015d005 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/yccmemcont.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/yccmemcont.vhd
@@ -46,7 +46,8 @@ entity yccmemcont is
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(23 downto 0);
       samp_fact : in std_logic;
-      error     : out std_logic
+      error     : out std_logic;
+      startgen  : in std_logic
    );
 end;
 -- samp_fact = 0 -> 4:1:1
@@ -92,7 +93,7 @@ crram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)
                  
                  
 comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1dataout, 
-                   cb0dataout, cb1dataout, cr0dataout, cr1dataout)
+                   cb0dataout, cb1dataout, cr0dataout, cr1dataout, startgen)
       variable v : control_reg;     
       variable vkready1 : std_logic;
       variable verror : std_logic;
@@ -306,7 +307,7 @@ comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1datao
    end if;
   
 -- reset part
-   if rst = '0' then
+   if rst = '0' or startgen = '1' then
        v.swf := mem0;
        v.swb := mem0;
        v.mem0state := empty;