1 /* ------------------------------------------------------------------
2 * Copyright (C) 1998-2009 PacketVideo
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
14 * See the License for the specific language governing permissions
15 * and limitations under the License.
16 * -------------------------------------------------------------------
18 /****************************************************************************************
19 Portions of this file are derived from the following 3GPP standard:
22 ANSI-C code for the Adaptive Multi-Rate - Wideband (AMR-WB) speech codec
23 Available from http://www.3gpp.org
25 (C) 2007, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TTA, TTC)
26 Permission to distribute, modify and use this file under the standard license
27 terms listed above has been obtained from the copyright holder.
28 ****************************************************************************************/
30 ------------------------------------------------------------------------------
34 Pathname: ./src/pvamrwbdecoder_basic_op_gcc_armv5.h
38 ------------------------------------------------------------------------------
42 ------------------------------------------------------------------------------
45 ------------------------------------------------------------------------------
48 #ifndef PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H
49 #define PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H
57 #if (defined(PV_ARM_GCC_V5)||defined(PV_ARM_GCC_V4))
59 static inline int16 sub_int16(int16 var1, int16 var2)
61 register int32 L_var_out;
62 register int32 L_var_aux;
63 register int32 ra = (int32)var1;
64 register int32 rb = (int32)var2;
67 "mov %0, %2, lsl #16\n"
68 "mov %1, %3, lsl #16\n"
76 return (int16)L_var_out;
80 static inline int16 add_int16(int16 var1, int16 var2)
82 register int32 L_var_out;
83 register int32 L_var_aux;
84 register int32 ra = (int32)var1;
85 register int32 rb = (int32)var2;
88 "mov %0, %2, lsl #16\n"
89 "mov %1, %3, lsl #16\n"
97 return (int16)L_var_out;
101 static inline int32 mul_32by16(int16 hi, int16 lo, int16 n)
105 register int32 ra = (int32)hi;
106 register int32 rb = (int32)lo;
107 register int32 rc = (int32)n;
111 "smulbb %0, %2, %4\n"
112 "smulbb %1, %3, %4\n"
113 "add %0, %0, %1, asr #15\n"
125 static inline int32 sub_int32(int32 L_var1, int32 L_var2)
127 register int32 L_var_out;
128 register int32 ra = L_var1;
129 register int32 rb = L_var2;
140 static inline int32 add_int32(int32 L_var1, int32 L_var2)
142 register int32 L_var_out;
143 register int32 ra = L_var1;
144 register int32 rb = L_var2;
155 static inline int32 msu_16by16_from_int32(int32 L_var3, int16 var1, int16 var2)
157 register int32 L_var_out;
158 register int32 ra = (int32)var1;
159 register int32 rb = (int32)var2;
160 register int32 rc = L_var3;
163 "smulbb %0, %1, %2\n"
174 static inline int32 mac_16by16_to_int32(int32 L_var3, int16 var1, int16 var2)
176 register int32 L_var_out;
177 register int32 ra = (int32)var1;
178 register int32 rb = (int32)var2;
179 register int32 rc = L_var3;
182 "smulbb %0, %1, %2\n"
193 static inline int32 mul_16by16_to_int32(int16 var1, int16 var2)
195 register int32 L_var_out;
196 register int32 ra = (int32)var1;
197 register int32 rb = (int32)var2;
200 "smulbb %0, %1, %2\n"
210 static inline int16 mult_int16(int16 var1, int16 var2)
212 register int32 L_var_out;
213 register int32 ra = (int32)var1;
214 register int32 rb = (int32)var2;
217 "smulbb %0, %1, %2\n"
218 "mov %0, %0, asr #15"
223 return (int16)L_var_out;
226 static inline int16 amr_wb_round(int32 L_var1)
228 register int32 L_var_out;
229 register int32 ra = (int32)L_var1;
230 register int32 rb = (int32)0x00008000L;
234 "mov %0, %0, asr #16"
238 return (int16)L_var_out;
241 static inline int16 amr_wb_shl1_round(int32 L_var1)
243 register int32 L_var_out;
244 register int32 ra = (int32)L_var1;
245 register int32 rb = (int32)0x00008000L;
250 "mov %0, %0, asr #16"
254 return (int16)L_var_out;
258 static inline int32 fxp_mac_16by16(const int16 L_var1, const int16 L_var2, int32 L_add)
261 register int32 ra = (int32)L_var1;
262 register int32 rb = (int32)L_var2;
263 register int32 rc = (int32)L_add;
266 "smlabb %0, %1, %2, %3"
274 static inline int32 fxp_mul_16by16bb(int16 L_var1, const int16 L_var2)
277 register int32 ra = (int32)L_var1;
278 register int32 rb = (int32)L_var2;
289 #define fxp_mul_16by16(a, b) fxp_mul_16by16bb( a, b)
292 static inline int32 fxp_mul32_by_16(int32 L_var1, const int32 L_var2)
295 register int32 ra = (int32)L_var1;
296 register int32 rb = (int32)L_var2;
306 #define fxp_mul32_by_16b( a, b) fxp_mul32_by_16( a, b)
318 #endif /* PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H */