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35 /****************************************************************************
39 * PURPOSE: Rx Xfer module header file.
41 ****************************************************************************/
46 #include "rxXfer_api.h"
50 #define RX_DESCRIPTOR_SIZE (sizeof(RxIfDescriptor_t))
51 #ifdef PLATFORM_SYMBIAN /* UMAC is using only one buffer and therefore we can't use consecutive reads */
52 #define MAX_CONSECUTIVE_READS 1
54 #define MAX_CONSECUTIVE_READS 8
57 #define MAX_PACKETS_NUMBER 8
58 #define MAX_CONSECUTIVE_READ_TXN 16
60 #define MAX_PACKET_SIZE 4096
64 TI_UINT32 numPacketsRead;
65 TI_UINT32 numBytesRead;
66 TI_UINT32 numPacketsDroppedNoMem;
67 TI_UINT32 numPacketsDroppedPacketIDMismatch;
75 TTxnStruct tTxnStruct;
83 TTxnStruct tTxnStruct;
90 TTxnStruct tTxnStruct;
103 TI_UINT32 aRxPktsDesc[NUM_RX_PKT_DESC]; /* Array of Rx packets short descriptors (see RX_DESC_SET/GET...) */
105 TI_UINT32 uDrvRxCntr;
107 TI_UINT32 uPacketMemoryPoolStart;
109 TRequestForBufferCb RequestForBufferCB;
110 TI_HANDLE RequestForBufferCB_handle;
112 TRegTxn aSlaveRegTxn[MAX_CONSECUTIVE_READ_TXN];
113 TTxnStruct aTxnStruct[MAX_CONSECUTIVE_READ_TXN];
114 TCounterTxn aCounterTxn[MAX_CONSECUTIVE_READ_TXN];
115 TDummyTxn aDummyTxn[MAX_CONSECUTIVE_READ_TXN];
116 TI_BOOL bChipIs1273Pg10;
118 TI_UINT8 aTempBuffer[MAX_PACKET_SIZE];
120 TI_UINT32 uAvailableTxn;
123 RxXferStats_T DbgStats;
129 #endif /* _RX_XFER_H */