1 /****************************************************************************
2 ****************************************************************************
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
10 ****************************************************************************
11 ****************************************************************************/
12 #ifndef __LINUX_MTD_NAND_H
13 #define __LINUX_MTD_NAND_H
15 #include <linux/wait.h>
16 #include <linux/spinlock.h>
17 #include <linux/mtd/mtd.h>
21 #define NAND_MAX_CHIPS 8
23 #define NAND_MAX_OOBSIZE 64
24 #define NAND_MAX_PAGESIZE 2048
32 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
33 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
34 #define NAND_CTRL_CHANGE 0x80
36 #define NAND_CMD_READ0 0
37 #define NAND_CMD_READ1 1
38 #define NAND_CMD_RNDOUT 5
39 #define NAND_CMD_PAGEPROG 0x10
40 #define NAND_CMD_READOOB 0x50
41 #define NAND_CMD_ERASE1 0x60
42 #define NAND_CMD_STATUS 0x70
43 #define NAND_CMD_STATUS_MULTI 0x71
44 #define NAND_CMD_SEQIN 0x80
45 #define NAND_CMD_RNDIN 0x85
46 #define NAND_CMD_READID 0x90
47 #define NAND_CMD_ERASE2 0xd0
48 #define NAND_CMD_RESET 0xff
50 #define NAND_CMD_READSTART 0x30
51 #define NAND_CMD_RNDOUTSTART 0xE0
52 #define NAND_CMD_CACHEDPROG 0x15
54 #define NAND_CMD_DEPLETE1 0x100
55 #define NAND_CMD_DEPLETE2 0x38
56 #define NAND_CMD_STATUS_MULTI 0x71
57 #define NAND_CMD_STATUS_ERROR 0x72
59 #define NAND_CMD_STATUS_ERROR0 0x73
60 #define NAND_CMD_STATUS_ERROR1 0x74
61 #define NAND_CMD_STATUS_ERROR2 0x75
62 #define NAND_CMD_STATUS_ERROR3 0x76
63 #define NAND_CMD_STATUS_RESET 0x7f
64 #define NAND_CMD_STATUS_CLEAR 0xff
66 #define NAND_CMD_NONE -1
68 #define NAND_STATUS_FAIL 0x01
69 #define NAND_STATUS_FAIL_N1 0x02
70 #define NAND_STATUS_TRUE_READY 0x20
71 #define NAND_STATUS_READY 0x40
72 #define NAND_STATUS_WP 0x80
81 #define NAND_ECC_READ 0
83 #define NAND_ECC_WRITE 1
85 #define NAND_ECC_READSYN 2
87 #define NAND_GET_DEVICE 0x80
89 #define NAND_NO_AUTOINCR 0x00000001
91 #define NAND_BUSWIDTH_16 0x00000002
93 #define NAND_NO_PADDING 0x00000004
95 #define NAND_CACHEPRG 0x00000008
97 #define NAND_COPYBACK 0x00000010
99 #define NAND_IS_AND 0x00000020
101 #define NAND_4PAGE_ARRAY 0x00000040
103 #define BBT_AUTO_REFRESH 0x00000080
105 #define NAND_NO_READRDY 0x00000100
107 #define NAND_SAMSUNG_LP_OPTIONS (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
109 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
110 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
111 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
112 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
114 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
116 #define NAND_USE_FLASH_BBT 0x00010000
118 #define NAND_SKIP_BBTSCAN 0x00020000
120 #define NAND_CONTROLLER_ALLOC 0x80000000
134 struct nand_hw_control {
136 struct nand_chip *active;
137 wait_queue_head_t wq;
140 struct nand_ecc_ctrl {
141 nand_ecc_modes_t mode;
148 struct nand_ecclayout *layout;
149 void (*hwctl)(struct mtd_info *mtd, int mode);
150 int (*calculate)(struct mtd_info *mtd,
153 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
156 int (*read_page)(struct mtd_info *mtd,
157 struct nand_chip *chip,
159 void (*write_page)(struct mtd_info *mtd,
160 struct nand_chip *chip,
162 int (*read_oob)(struct mtd_info *mtd,
163 struct nand_chip *chip,
166 int (*write_oob)(struct mtd_info *mtd,
167 struct nand_chip *chip,
171 struct nand_buffers {
172 uint8_t ecccalc[NAND_MAX_OOBSIZE];
173 uint8_t ecccode[NAND_MAX_OOBSIZE];
174 uint8_t oobwbuf[NAND_MAX_OOBSIZE];
175 uint8_t databuf[NAND_MAX_PAGESIZE];
176 uint8_t oobrbuf[NAND_MAX_OOBSIZE];
180 void __iomem *IO_ADDR_R;
181 void __iomem *IO_ADDR_W;
183 uint8_t (*read_byte)(struct mtd_info *mtd);
184 u16 (*read_word)(struct mtd_info *mtd);
185 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
186 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
187 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
188 void (*select_chip)(struct mtd_info *mtd, int chip);
189 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
190 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
191 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
193 int (*dev_ready)(struct mtd_info *mtd);
194 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
195 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
196 void (*erase_cmd)(struct mtd_info *mtd, int page);
197 int (*scan_bbt)(struct mtd_info *mtd);
198 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
201 unsigned int options;
204 int phys_erase_shift;
208 unsigned long chipsize;
216 struct nand_hw_control *controller;
217 struct nand_ecclayout *ecclayout;
219 struct nand_ecc_ctrl ecc;
220 struct nand_buffers buffers;
221 struct nand_hw_control hwcontrol;
223 struct mtd_oob_ops ops;
226 struct nand_bbt_descr *bbt_td;
227 struct nand_bbt_descr *bbt_md;
229 struct nand_bbt_descr *badblock_pattern;
234 #define NAND_MFR_TOSHIBA 0x98
235 #define NAND_MFR_SAMSUNG 0xec
236 #define NAND_MFR_FUJITSU 0x04
237 #define NAND_MFR_NATIONAL 0x8f
238 #define NAND_MFR_RENESAS 0x07
239 #define NAND_MFR_STMICRO 0x20
240 #define NAND_MFR_HYNIX 0xad
242 struct nand_flash_dev {
245 unsigned long pagesize;
246 unsigned long chipsize;
247 unsigned long erasesize;
248 unsigned long options;
251 struct nand_manufacturers {
256 struct nand_bbt_descr {
258 int pages[NAND_MAX_CHIPS];
261 uint8_t version[NAND_MAX_CHIPS];
264 int reserved_block_code;
268 #define NAND_BBT_NRBITS_MSK 0x0000000F
269 #define NAND_BBT_1BIT 0x00000001
270 #define NAND_BBT_2BIT 0x00000002
271 #define NAND_BBT_4BIT 0x00000004
272 #define NAND_BBT_8BIT 0x00000008
274 #define NAND_BBT_LASTBLOCK 0x00000010
276 #define NAND_BBT_ABSPAGE 0x00000020
278 #define NAND_BBT_SEARCH 0x00000040
280 #define NAND_BBT_PERCHIP 0x00000080
282 #define NAND_BBT_VERSION 0x00000100
284 #define NAND_BBT_CREATE 0x00000200
286 #define NAND_BBT_SCANALLPAGES 0x00000400
288 #define NAND_BBT_SCANEMPTY 0x00000800
290 #define NAND_BBT_WRITE 0x00001000
292 #define NAND_BBT_SAVECONTENT 0x00002000
294 #define NAND_BBT_SCAN2NDPAGE 0x00004000
296 #define NAND_BBT_SCAN_MAXBLOCKS 4
298 #define NAND_SMALL_BADBLOCK_POS 5
299 #define NAND_LARGE_BADBLOCK_POS 0
301 struct platform_nand_chip {
305 struct mtd_partition *partitions;
306 struct nand_ecclayout *ecclayout;
308 unsigned int options;
312 struct platform_nand_ctrl {
313 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
314 int (*dev_ready)(struct mtd_info *mtd);
315 void (*select_chip)(struct mtd_info *mtd, int chip);