4 #define VS1011E_OPCODE_READ 0x03
5 #define VS1011E_OPCODE_WRITE 0x02
7 #define REGADDR_MODE 0x00
8 #define REGADDR_STATUS 0x01
9 #define REGADDR_BASS 0x02
10 #define REGADDR_CLOCKF 0x03
11 #define REGADDR_DECODE_TIME 0x04
12 #define REGADDR_AUDATA 0x05
13 #define REGADDR_WRAM 0x06
14 #define REGADDR_WRAMADDR 0x07
15 #define REGADDR_HDAT0 0x08
16 #define REGADDR_HDAT1 0x09
17 #define REGADDR_AIADDR 0x0A
18 #define REGADDR_VOL 0x0B
19 #define REGADDR_AICTRL0 0x0C
20 #define REGADDR_AICTRL1 0x0D
21 #define REGADDR_AICTRL2 0x0E
22 #define REGADDR_AICTRL3 0x0F
24 #define SM_DIFF (1 << 0)
25 #define SM_LAYER12 (1 << 1)
26 #define SM_RESET (1 << 2)
27 #define SM_OUTOFWAV (1 << 3)
28 #define SM_SETTOZERO1 (1 << 4)
29 #define SM_TESTS (1 << 5)
30 #define SM_STREAM (1 << 6)
31 #define SM_SETTOZERO2 (1 << 7)
32 #define SM_DACT (1 << 8)
33 #define SM_SDIORD (1 << 9)
34 #define SM_SDISHARE (1 << 10)
35 #define SM_SDINEW (1 << 11)
36 #define SM_SETTOZERO3 (1 << 12)
37 #define SM_SETTOZERO4 (1 << 13)
39 #define SCI_BASS_BITBASS_ST_AMP 12
40 #define SCI_BASS_BITBASS_ST_FREQ 8
41 #define SCI_BASS_BITBASS_SB_AMP 4
42 #define SCI_BASS_BITBASS_SB_FREQ 0
44 #define VS1011E_VSCTL1() do { *H8_3069F_P4DR |= P4DR_BIT_VSCCS; } while (0)
45 #define VS1011E_VSCTL0() do { *H8_3069F_P4DR &= ~P4DR_BIT_VSCCS; } while (0)
47 #define VS1011E_VSDAT1() do { *H8_3069F_P4DR |= P4DR_BIT_VSDCS; } while (0)
48 #define VS1011E_VSDAT0() do { *H8_3069F_P4DR &= ~P4DR_BIT_VSDCS; } while (0)
50 #define VS1011E_RESET1() do { *H8_3069F_P4DR |= P4DR_BIT_VSRST; } while (0)
51 #define VS1011E_RESET0() do { *H8_3069F_P4DR &= ~P4DR_BIT_VSRST; } while (0)
53 #define VS1011E_CHK_DREQ() (((*H8_3069F_P4DR) & P4DR_BIT_VSDREQ) ? 0 : 1)
55 #define H8_3069F_P4DR ((volatile uint8 *)0xFFFFD3)
56 #define P4DR_BIT_VSCCS (1 << 2)
57 #define P4DR_BIT_VSDCS (1 << 3)
58 #define P4DR_BIT_VSDREQ (1 << 4)
59 #define P4DR_BIT_VSRST (1 << 5)
61 #define H8_3069F_PBDR ((volatile uint8 *)0xFFFFDA)
62 #define PBDR_BIT_SCLK (1 << 5)
63 #define PBDR_BIT_MOSI (1 << 6)
64 #define PBDR_BIT_MISO (1 << 7)
66 #define CS_H() do { *H8_3069F_P4DR |= P4DR_BIT_CS; } while (0) /* Set MMC CS "high" */
67 #define CS_L() do { *H8_3069F_P4DR &= ~P4DR_BIT_CS; } while (0) /* Set MMC CS "low" */
68 #define CK_H() do { *H8_3069F_PBDR |= PBDR_BIT_SCLK; } while (0) /* Set MMC SCLK "high" */
69 #define CK_L() do { *H8_3069F_PBDR &= ~PBDR_BIT_SCLK; } while (0) /* Set MMC SCLK "low" */
70 #define DI_H() do { *H8_3069F_PBDR |= PBDR_BIT_MOSI; } while (0) /* Set MMC DI "high" */
71 #define DI_L() do { *H8_3069F_PBDR &= ~PBDR_BIT_MOSI; } while (0) /* Set MMC DI "low" */
72 #define DO ((*H8_3069F_PBDR & PBDR_BIT_MISO) ? 1 : 0) /* Get MMC DO value (high:true, low:false) */
74 static void _delay_ms(int ms)
77 for (i = 0; i < ms * 10000; i++) {
81 static void _delay_us(int us)
84 for (i = 0; i < us * 10; i++) {
88 static void SPI_TX(uint8 d)
90 if (d & 0x80) DI_H(); else DI_L(); /* bit7 */
92 if (d & 0x40) DI_H(); else DI_L(); /* bit6 */
94 if (d & 0x20) DI_H(); else DI_L(); /* bit5 */
96 if (d & 0x10) DI_H(); else DI_L(); /* bit4 */
98 if (d & 0x08) DI_H(); else DI_L(); /* bit3 */
100 if (d & 0x04) DI_H(); else DI_L(); /* bit2 */
102 if (d & 0x02) DI_H(); else DI_L(); /* bit1 */
104 if (d & 0x01) DI_H(); else DI_L(); /* bit0 */
107 static uint8 SPI_RX()
111 DI_H(); /* Send 0xFF */
113 r = 0; if (DO) r++; /* bit7 */
115 r <<= 1; if (DO) r++; /* bit6 */
117 r <<= 1; if (DO) r++; /* bit5 */
119 r <<= 1; if (DO) r++; /* bit4 */
121 r <<= 1; if (DO) r++; /* bit3 */
123 r <<= 1; if (DO) r++; /* bit2 */
125 r <<= 1; if (DO) r++; /* bit1 */
127 r <<= 1; if (DO) r++; /* bit0 */
133 static void vs1011e_read(uint8 addr, uint16 * stat);
134 static void vs1011e_write(uint8 addr, uint16 stat);
138 vs1011e_reset_by_hardware();
139 vs1011e_reset_by_software();
142 void vs1011e_reset_by_hardware()
144 // Assert vs1011 reset
148 // Deassert CS by setting to high level
152 // Release vs1011 reset
154 // Delay 10ms (2.5ms accordig to datasheet)
156 // Set volume to minimum
157 vs1011e_write(REGADDR_VOL, 0xFFFF);
159 vs1011e_write(REGADDR_CLOCKF, 0x9800);
162 // Set slow sample rate for slow analog part startup
163 vs1011e_write(REGADDR_AUDATA, 10);
166 // Switch on the analog parts
167 vs1011e_write(REGADDR_VOL, 0xFEFE);
168 vs1011e_write(REGADDR_AUDATA, 44101);
169 vs1011e_write(REGADDR_VOL, 0x0202);
172 void vs1011e_reset_by_software()
178 // Set SW reset bit, set VS1011 native mode on SPI
179 vs1011e_write(REGADDR_MODE,
180 SM_LAYER12 | SM_RESET | SM_SDINEW | SM_TESTS);
183 // Rewrite SCI_CLOCKF after soft reset
184 vs1011e_write(REGADDR_CLOCKF, 0x9800);
188 while (VS1011E_CHK_DREQ()) {
193 for (i = 0; i < 1024; i++) {
195 while (VS1011E_CHK_DREQ()) {
203 void vs1011e_cancel_data()
206 while (VS1011E_CHK_DREQ()) {
210 for (i = 0; i < 2048; i++) {
211 while (VS1011E_CHK_DREQ()) {
218 void vs1011e_set_enhancer(uint8 st_amp, uint8 st_freq, uint8 sb_amp,
222 (st_amp << SCI_BASS_BITBASS_ST_AMP) |
223 (st_freq << SCI_BASS_BITBASS_ST_FREQ) |
224 (sb_amp << SCI_BASS_BITBASS_SB_AMP) |
225 (sb_freq << SCI_BASS_BITBASS_SB_FREQ);
226 vs1011e_write(REGADDR_BASS, val);
229 void vs1011e_get_enhancer(uint8 * st_amp, uint8 * st_freq,
230 uint8 * sb_amp, uint8 * sb_freq)
233 vs1011e_read(REGADDR_BASS, &val);
234 *st_amp = (val >> SCI_BASS_BITBASS_ST_AMP) & 0x0F;
235 *st_freq = (val >> SCI_BASS_BITBASS_ST_FREQ) & 0x0F;
236 *sb_amp = (val >> SCI_BASS_BITBASS_SB_AMP) & 0x0F;
237 *sb_freq = (val >> SCI_BASS_BITBASS_SB_FREQ) & 0x0F;
240 void vs1011e_volume_read(uint8 * left, uint8 * right)
243 vs1011e_read(REGADDR_VOL, &val);
248 void vs1011e_volume_write(const uint8 left, const uint8 right)
251 (((uint16) left << 8) & 0xFF00) | (((uint16) right << 0) &
253 vs1011e_write(REGADDR_VOL, val);
256 void vs1011e_play(int8(*func) (uint8 * buf, const uint16 len))
258 #define UNITBYTE (128)
263 * Read the song data.
265 int8 len = func(buf, UNITBYTE);
272 for (i = 0; i < UNITBYTE; i++) {
273 while (VS1011E_CHK_DREQ()) { }
281 void vs1011e_decodetime_read(uint16 * sec)
283 vs1011e_read(REGADDR_DECODE_TIME, sec);
286 void vs1011e_decodetime_write(const uint16 sec)
288 vs1011e_write(REGADDR_DECODE_TIME, sec);
291 void vs1011e_sinetest_init()
293 while (VS1011E_CHK_DREQ()) {
308 void vs1011e_sinetest_fini()
310 while (VS1011E_CHK_DREQ()) {
324 vs1011e_cancel_data();
327 void vs1011e_register_print()
332 xprintf(PSTR("===================\r\n"));
333 for (i = 0; i <= 0x0F; i++) {
334 vs1011e_read(i, &val);
335 xprintf(PSTR("0x%02X: 0x%04X\r\n"), i, val);
337 xprintf(PSTR("===================\r\n"));
341 static void vs1011e_read(uint8 addr, uint16 * stat)
343 while (VS1011E_CHK_DREQ()) {
348 SPI_TX(VS1011E_OPCODE_READ);
352 *stat |= SPI_RX() << 8;
358 static void vs1011e_write(uint8 addr, uint16 stat)
360 while (VS1011E_CHK_DREQ()) {
365 SPI_TX(VS1011E_OPCODE_WRITE);