drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *
 107  * Known bugs:
 108  * We suspect that on some hardware no TX done interrupts are generated.
 109  * This means recovery from netif_stop_queue only happens if the hw timer
 110  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 111  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 112  * If your hardware reliably generates tx done interrupts, then you can remove
 113  * DEV_NEED_TIMERIRQ from the driver_data flags.
 114  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 115  * superfluous timer interrupts from the nic.
 116  */
 117 #define FORCEDETH_VERSION               "0.50"
 118 #define DRV_NAME                        "forcedeth"
 119
 120 #include <linux/module.h>
 121 #include <linux/moduleparam.h>
 122 #include <linux/types.h>
 123 #include <linux/pci.h>
 124 #include <linux/interrupt.h>
 125 #include <linux/netdevice.h>
 126 #include <linux/etherdevice.h>
 127 #include <linux/delay.h>
 128 #include <linux/spinlock.h>
 129 #include <linux/ethtool.h>
 130 #include <linux/timer.h>
 131 #include <linux/skbuff.h>
 132 #include <linux/mii.h>
 133 #include <linux/random.h>
 134 #include <linux/init.h>
 135 #include <linux/if_vlan.h>
 136
 137 #include <asm/irq.h>
 138 #include <asm/io.h>
 139 #include <asm/uaccess.h>
 140 #include <asm/system.h>
 141
 142 #if 0
 143 #define dprintk                 printk
 144 #else
 145 #define dprintk(x...)           do { } while (0)
 146 #endif
 147
 148 /* not present in 2.4 */
 149 #ifndef NETDEV_TX_OK
 150 #define NETDEV_TX_OK    0
 151 #define NETDEV_TX_BUSY  1
 152 #endif
 153
 154 /*
 155  * Hardware access:
 156  */
 157
 158 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 159 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 160 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 161 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 162 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 163 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 164
 165 enum {
 166         NvRegIrqStatus = 0x000,
 167 #define NVREG_IRQSTAT_MIIEVENT  0x040
 168 #define NVREG_IRQSTAT_MASK              0x1ff
 169         NvRegIrqMask = 0x004,
 170 #define NVREG_IRQ_RX_ERROR              0x0001
 171 #define NVREG_IRQ_RX                    0x0002
 172 #define NVREG_IRQ_RX_NOBUF              0x0004
 173 #define NVREG_IRQ_TX_ERR                0x0008
 174 #define NVREG_IRQ_TX_OK                 0x0010
 175 #define NVREG_IRQ_TIMER                 0x0020
 176 #define NVREG_IRQ_LINK                  0x0040
 177 #define NVREG_IRQ_TX_ERROR              0x0080
 178 #define NVREG_IRQ_TX1                   0x0100
 179 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 180 #define NVREG_IRQMASK_CPU               0x0040
 181
 182 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 183                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
 184                                         NVREG_IRQ_TX1))
 185
 186         NvRegUnknownSetupReg6 = 0x008,
 187 #define NVREG_UNKSETUP6_VAL             3
 188
 189 /*
 190  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 191  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 192  */
 193         NvRegPollingInterval = 0x00c,
 194 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 195 #define NVREG_POLL_DEFAULT_CPU  13
 196         NvRegMisc1 = 0x080,
 197 #define NVREG_MISC1_HD          0x02
 198 #define NVREG_MISC1_FORCE       0x3b0f3c
 199
 200         NvRegTransmitterControl = 0x084,
 201 #define NVREG_XMITCTL_START     0x01
 202         NvRegTransmitterStatus = 0x088,
 203 #define NVREG_XMITSTAT_BUSY     0x01
 204
 205         NvRegPacketFilterFlags = 0x8c,
 206 #define NVREG_PFF_ALWAYS        0x7F0008
 207 #define NVREG_PFF_PROMISC       0x80
 208 #define NVREG_PFF_MYADDR        0x20
 209
 210         NvRegOffloadConfig = 0x90,
 211 #define NVREG_OFFLOAD_HOMEPHY   0x601
 212 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 213         NvRegReceiverControl = 0x094,
 214 #define NVREG_RCVCTL_START      0x01
 215         NvRegReceiverStatus = 0x98,
 216 #define NVREG_RCVSTAT_BUSY      0x01
 217
 218         NvRegRandomSeed = 0x9c,
 219 #define NVREG_RNDSEED_MASK      0x00ff
 220 #define NVREG_RNDSEED_FORCE     0x7f00
 221 #define NVREG_RNDSEED_FORCE2    0x2d00
 222 #define NVREG_RNDSEED_FORCE3    0x7400
 223
 224         NvRegUnknownSetupReg1 = 0xA0,
 225 #define NVREG_UNKSETUP1_VAL     0x16070f
 226         NvRegUnknownSetupReg2 = 0xA4,
 227 #define NVREG_UNKSETUP2_VAL     0x16
 228         NvRegMacAddrA = 0xA8,
 229         NvRegMacAddrB = 0xAC,
 230         NvRegMulticastAddrA = 0xB0,
 231 #define NVREG_MCASTADDRA_FORCE  0x01
 232         NvRegMulticastAddrB = 0xB4,
 233         NvRegMulticastMaskA = 0xB8,
 234         NvRegMulticastMaskB = 0xBC,
 235
 236         NvRegPhyInterface = 0xC0,
 237 #define PHY_RGMII               0x10000000
 238
 239         NvRegTxRingPhysAddr = 0x100,
 240         NvRegRxRingPhysAddr = 0x104,
 241         NvRegRingSizes = 0x108,
 242 #define NVREG_RINGSZ_TXSHIFT 0
 243 #define NVREG_RINGSZ_RXSHIFT 16
 244         NvRegUnknownTransmitterReg = 0x10c,
 245         NvRegLinkSpeed = 0x110,
 246 #define NVREG_LINKSPEED_FORCE 0x10000
 247 #define NVREG_LINKSPEED_10      1000
 248 #define NVREG_LINKSPEED_100     100
 249 #define NVREG_LINKSPEED_1000    50
 250 #define NVREG_LINKSPEED_MASK    (0xFFF)
 251         NvRegUnknownSetupReg5 = 0x130,
 252 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 253         NvRegUnknownSetupReg3 = 0x13c,
 254 #define NVREG_UNKSETUP3_VAL1    0x200010
 255         NvRegTxRxControl = 0x144,
 256 #define NVREG_TXRXCTL_KICK      0x0001
 257 #define NVREG_TXRXCTL_BIT1      0x0002
 258 #define NVREG_TXRXCTL_BIT2      0x0004
 259 #define NVREG_TXRXCTL_IDLE      0x0008
 260 #define NVREG_TXRXCTL_RESET     0x0010
 261 #define NVREG_TXRXCTL_RXCHECK   0x0400
 262 #define NVREG_TXRXCTL_DESC_1    0
 263 #define NVREG_TXRXCTL_DESC_2    0x02100
 264 #define NVREG_TXRXCTL_DESC_3    0x02200
 265 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 266 #define NVREG_TXRXCTL_VLANINS   0x00080
 267         NvRegMIIStatus = 0x180,
 268 #define NVREG_MIISTAT_ERROR             0x0001
 269 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 270 #define NVREG_MIISTAT_MASK              0x000f
 271 #define NVREG_MIISTAT_MASK2             0x000f
 272         NvRegUnknownSetupReg4 = 0x184,
 273 #define NVREG_UNKSETUP4_VAL     8
 274
 275         NvRegAdapterControl = 0x188,
 276 #define NVREG_ADAPTCTL_START    0x02
 277 #define NVREG_ADAPTCTL_LINKUP   0x04
 278 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 279 #define NVREG_ADAPTCTL_RUNNING  0x100000
 280 #define NVREG_ADAPTCTL_PHYSHIFT 24
 281         NvRegMIISpeed = 0x18c,
 282 #define NVREG_MIISPEED_BIT8     (1<<8)
 283 #define NVREG_MIIDELAY  5
 284         NvRegMIIControl = 0x190,
 285 #define NVREG_MIICTL_INUSE      0x08000
 286 #define NVREG_MIICTL_WRITE      0x00400
 287 #define NVREG_MIICTL_ADDRSHIFT  5
 288         NvRegMIIData = 0x194,
 289         NvRegWakeUpFlags = 0x200,
 290 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 291 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 292 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 293 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 294 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 295 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 296 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 297 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 298 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 299 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 300 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 301
 302         NvRegPatternCRC = 0x204,
 303         NvRegPatternMask = 0x208,
 304         NvRegPowerCap = 0x268,
 305 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 306 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 307 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 308         NvRegPowerState = 0x26c,
 309 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 310 #define NVREG_POWERSTATE_VALID          0x0100
 311 #define NVREG_POWERSTATE_MASK           0x0003
 312 #define NVREG_POWERSTATE_D0             0x0000
 313 #define NVREG_POWERSTATE_D1             0x0001
 314 #define NVREG_POWERSTATE_D2             0x0002
 315 #define NVREG_POWERSTATE_D3             0x0003
 316         NvRegVlanControl = 0x300,
 317 #define NVREG_VLANCONTROL_ENABLE        0x2000
 318 };
 319
 320 /* Big endian: should work, but is untested */
 321 struct ring_desc {
 322         u32 PacketBuffer;
 323         u32 FlagLen;
 324 };
 325
 326 struct ring_desc_ex {
 327         u32 PacketBufferHigh;
 328         u32 PacketBufferLow;
 329         u32 TxVlan;
 330         u32 FlagLen;
 331 };
 332
 333 typedef union _ring_type {
 334         struct ring_desc* orig;
 335         struct ring_desc_ex* ex;
 336 } ring_type;
 337
 338 #define FLAG_MASK_V1 0xffff0000
 339 #define FLAG_MASK_V2 0xffffc000
 340 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 341 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 342
 343 #define NV_TX_LASTPACKET        (1<<16)
 344 #define NV_TX_RETRYERROR        (1<<19)
 345 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 346 #define NV_TX_DEFERRED          (1<<26)
 347 #define NV_TX_CARRIERLOST       (1<<27)
 348 #define NV_TX_LATECOLLISION     (1<<28)
 349 #define NV_TX_UNDERFLOW         (1<<29)
 350 #define NV_TX_ERROR             (1<<30)
 351 #define NV_TX_VALID             (1<<31)
 352
 353 #define NV_TX2_LASTPACKET       (1<<29)
 354 #define NV_TX2_RETRYERROR       (1<<18)
 355 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 356 #define NV_TX2_DEFERRED         (1<<25)
 357 #define NV_TX2_CARRIERLOST      (1<<26)
 358 #define NV_TX2_LATECOLLISION    (1<<27)
 359 #define NV_TX2_UNDERFLOW        (1<<28)
 360 /* error and valid are the same for both */
 361 #define NV_TX2_ERROR            (1<<30)
 362 #define NV_TX2_VALID            (1<<31)
 363 #define NV_TX2_TSO              (1<<28)
 364 #define NV_TX2_TSO_SHIFT        14
 365 #define NV_TX2_TSO_MAX_SHIFT    14
 366 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 367 #define NV_TX2_CHECKSUM_L3      (1<<27)
 368 #define NV_TX2_CHECKSUM_L4      (1<<26)
 369
 370 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 371
 372 #define NV_RX_DESCRIPTORVALID   (1<<16)
 373 #define NV_RX_MISSEDFRAME       (1<<17)
 374 #define NV_RX_SUBSTRACT1        (1<<18)
 375 #define NV_RX_ERROR1            (1<<23)
 376 #define NV_RX_ERROR2            (1<<24)
 377 #define NV_RX_ERROR3            (1<<25)
 378 #define NV_RX_ERROR4            (1<<26)
 379 #define NV_RX_CRCERR            (1<<27)
 380 #define NV_RX_OVERFLOW          (1<<28)
 381 #define NV_RX_FRAMINGERR        (1<<29)
 382 #define NV_RX_ERROR             (1<<30)
 383 #define NV_RX_AVAIL             (1<<31)
 384
 385 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 386 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 387 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 388 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 389 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 390 #define NV_RX2_SUBSTRACT1       (1<<25)
 391 #define NV_RX2_ERROR1           (1<<18)
 392 #define NV_RX2_ERROR2           (1<<19)
 393 #define NV_RX2_ERROR3           (1<<20)
 394 #define NV_RX2_ERROR4           (1<<21)
 395 #define NV_RX2_CRCERR           (1<<22)
 396 #define NV_RX2_OVERFLOW         (1<<23)
 397 #define NV_RX2_FRAMINGERR       (1<<24)
 398 /* error and avail are the same for both */
 399 #define NV_RX2_ERROR            (1<<30)
 400 #define NV_RX2_AVAIL            (1<<31)
 401
 402 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 403 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 404
 405 /* Miscelaneous hardware related defines: */
 406 #define NV_PCI_REGSZ            0x270
 407
 408 /* various timeout delays: all in usec */
 409 #define NV_TXRX_RESET_DELAY     4
 410 #define NV_TXSTOP_DELAY1        10
 411 #define NV_TXSTOP_DELAY1MAX     500000
 412 #define NV_TXSTOP_DELAY2        100
 413 #define NV_RXSTOP_DELAY1        10
 414 #define NV_RXSTOP_DELAY1MAX     500000
 415 #define NV_RXSTOP_DELAY2        100
 416 #define NV_SETUP5_DELAY         5
 417 #define NV_SETUP5_DELAYMAX      50000
 418 #define NV_POWERUP_DELAY        5
 419 #define NV_POWERUP_DELAYMAX     5000
 420 #define NV_MIIBUSY_DELAY        50
 421 #define NV_MIIPHY_DELAY 10
 422 #define NV_MIIPHY_DELAYMAX      10000
 423
 424 #define NV_WAKEUPPATTERNS       5
 425 #define NV_WAKEUPMASKENTRIES    4
 426
 427 /* General driver defaults */
 428 #define NV_WATCHDOG_TIMEO       (5*HZ)
 429
 430 #define RX_RING         128
 431 #define TX_RING         256
 432 /*
 433  * If your nic mysteriously hangs then try to reduce the limits
 434  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 435  * last valid ring entry. But this would be impossible to
 436  * implement - probably a disassembly error.
 437  */
 438 #define TX_LIMIT_STOP   255
 439 #define TX_LIMIT_START  254
 440
 441 /* rx/tx mac addr + type + vlan + align + slack*/
 442 #define NV_RX_HEADERS           (64)
 443 /* even more slack. */
 444 #define NV_RX_ALLOC_PAD         (64)
 445
 446 /* maximum mtu size */
 447 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 448 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 449
 450 #define OOM_REFILL      (1+HZ/20)
 451 #define POLL_WAIT       (1+HZ/100)
 452 #define LINK_TIMEOUT    (3*HZ)
 453
 454 /*
 455  * desc_ver values:
 456  * The nic supports three different descriptor types:
 457  * - DESC_VER_1: Original
 458  * - DESC_VER_2: support for jumbo frames.
 459  * - DESC_VER_3: 64-bit format.
 460  */
 461 #define DESC_VER_1      1
 462 #define DESC_VER_2      2
 463 #define DESC_VER_3      3
 464
 465 /* PHY defines */
 466 #define PHY_OUI_MARVELL 0x5043
 467 #define PHY_OUI_CICADA  0x03f1
 468 #define PHYID1_OUI_MASK 0x03ff
 469 #define PHYID1_OUI_SHFT 6
 470 #define PHYID2_OUI_MASK 0xfc00
 471 #define PHYID2_OUI_SHFT 10
 472 #define PHY_INIT1       0x0f000
 473 #define PHY_INIT2       0x0e00
 474 #define PHY_INIT3       0x01000
 475 #define PHY_INIT4       0x0200
 476 #define PHY_INIT5       0x0004
 477 #define PHY_INIT6       0x02000
 478 #define PHY_GIGABIT     0x0100
 479
 480 #define PHY_TIMEOUT     0x1
 481 #define PHY_ERROR       0x2
 482
 483 #define PHY_100 0x1
 484 #define PHY_1000        0x2
 485 #define PHY_HALF        0x100
 486
 487 /* FIXME: MII defines that should be added to <linux/mii.h> */
 488 #define MII_1000BT_CR   0x09
 489 #define MII_1000BT_SR   0x0a
 490 #define ADVERTISE_1000FULL      0x0200
 491 #define ADVERTISE_1000HALF      0x0100
 492 #define LPA_1000FULL    0x0800
 493 #define LPA_1000HALF    0x0400
 494
 495
 496 /*
 497  * SMP locking:
 498  * All hardware access under dev->priv->lock, except the performance
 499  * critical parts:
 500  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 501  *      by the arch code for interrupts.
 502  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 503  *      needs dev->priv->lock :-(
 504  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 505  */
 506
 507 /* in dev: base, irq */
 508 struct fe_priv {
 509         spinlock_t lock;
 510
 511         /* General data:
 512          * Locking: spin_lock(&np->lock); */
 513         struct net_device_stats stats;
 514         int in_shutdown;
 515         u32 linkspeed;
 516         int duplex;
 517         int autoneg;
 518         int fixed_mode;
 519         int phyaddr;
 520         int wolenabled;
 521         unsigned int phy_oui;
 522         u16 gigabit;
 523
 524         /* General data: RO fields */
 525         dma_addr_t ring_addr;
 526         struct pci_dev *pci_dev;
 527         u32 orig_mac[2];
 528         u32 irqmask;
 529         u32 desc_ver;
 530         u32 txrxctl_bits;
 531         u32 vlanctl_bits;
 532
 533         void __iomem *base;
 534
 535         /* rx specific fields.
 536          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 537          */
 538         ring_type rx_ring;
 539         unsigned int cur_rx, refill_rx;
 540         struct sk_buff *rx_skbuff[RX_RING];
 541         dma_addr_t rx_dma[RX_RING];
 542         unsigned int rx_buf_sz;
 543         unsigned int pkt_limit;
 544         struct timer_list oom_kick;
 545         struct timer_list nic_poll;
 546
 547         /* media detection workaround.
 548          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 549          */
 550         int need_linktimer;
 551         unsigned long link_timeout;
 552         /*
 553          * tx specific fields.
 554          */
 555         ring_type tx_ring;
 556         unsigned int next_tx, nic_tx;
 557         struct sk_buff *tx_skbuff[TX_RING];
 558         dma_addr_t tx_dma[TX_RING];
 559         unsigned int tx_dma_len[TX_RING];
 560         u32 tx_flags;
 561
 562         /* vlan fields */
 563         struct vlan_group *vlangrp;
 564 };
 565
 566 /*
 567  * Maximum number of loops until we assume that a bit in the irq mask
 568  * is stuck. Overridable with module param.
 569  */
 570 static int max_interrupt_work = 5;
 571
 572 /*
 573  * Optimization can be either throuput mode or cpu mode
 574  *
 575  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 576  * CPU Mode: Interrupts are controlled by a timer.
 577  */
 578 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
 579 #define NV_OPTIMIZATION_MODE_CPU        1
 580 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 581
 582 /*
 583  * Poll interval for timer irq
 584  *
 585  * This interval determines how frequent an interrupt is generated.
 586  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 587  * Min = 0, and Max = 65535
 588  */
 589 static int poll_interval = -1;
 590
 591 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 592 {
 593         return netdev_priv(dev);
 594 }
 595
 596 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 597 {
 598         return ((struct fe_priv *)netdev_priv(dev))->base;
 599 }
 600
 601 static inline void pci_push(u8 __iomem *base)
 602 {
 603         /* force out pending posted writes */
 604         readl(base);
 605 }
 606
 607 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 608 {
 609         return le32_to_cpu(prd->FlagLen)
 610                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 611 }
 612
 613 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 614 {
 615         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 616 }
 617
 618 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 619                                 int delay, int delaymax, const char *msg)
 620 {
 621         u8 __iomem *base = get_hwbase(dev);
 622
 623         pci_push(base);
 624         do {
 625                 udelay(delay);
 626                 delaymax -= delay;
 627                 if (delaymax < 0) {
 628                         if (msg)
 629                                 printk(msg);
 630                         return 1;
 631                 }
 632         } while ((readl(base + offset) & mask) != target);
 633         return 0;
 634 }
 635
 636 #define MII_READ        (-1)
 637 /* mii_rw: read/write a register on the PHY.
 638  *
 639  * Caller must guarantee serialization
 640  */
 641 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 642 {
 643         u8 __iomem *base = get_hwbase(dev);
 644         u32 reg;
 645         int retval;
 646
 647         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 648
 649         reg = readl(base + NvRegMIIControl);
 650         if (reg & NVREG_MIICTL_INUSE) {
 651                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 652                 udelay(NV_MIIBUSY_DELAY);
 653         }
 654
 655         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 656         if (value != MII_READ) {
 657                 writel(value, base + NvRegMIIData);
 658                 reg |= NVREG_MIICTL_WRITE;
 659         }
 660         writel(reg, base + NvRegMIIControl);
 661
 662         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 663                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 664                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 665                                 dev->name, miireg, addr);
 666                 retval = -1;
 667         } else if (value != MII_READ) {
 668                 /* it was a write operation - fewer failures are detectable */
 669                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 670                                 dev->name, value, miireg, addr);
 671                 retval = 0;
 672         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 673                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 674                                 dev->name, miireg, addr);
 675                 retval = -1;
 676         } else {
 677                 retval = readl(base + NvRegMIIData);
 678                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 679                                 dev->name, miireg, addr, retval);
 680         }
 681
 682         return retval;
 683 }
 684
 685 static int phy_reset(struct net_device *dev)
 686 {
 687         struct fe_priv *np = netdev_priv(dev);
 688         u32 miicontrol;
 689         unsigned int tries = 0;
 690
 691         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 692         miicontrol |= BMCR_RESET;
 693         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 694                 return -1;
 695         }
 696
 697         /* wait for 500ms */
 698         msleep(500);
 699
 700         /* must wait till reset is deasserted */
 701         while (miicontrol & BMCR_RESET) {
 702                 msleep(10);
 703                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 704                 /* FIXME: 100 tries seem excessive */
 705                 if (tries++ > 100)
 706                         return -1;
 707         }
 708         return 0;
 709 }
 710
 711 static int phy_init(struct net_device *dev)
 712 {
 713         struct fe_priv *np = get_nvpriv(dev);
 714         u8 __iomem *base = get_hwbase(dev);
 715         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
 716
 717         /* set advertise register */
 718         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
 719         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
 720         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
 721                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
 722                 return PHY_ERROR;
 723         }
 724
 725         /* get phy interface type */
 726         phyinterface = readl(base + NvRegPhyInterface);
 727
 728         /* see if gigabit phy */
 729         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 730         if (mii_status & PHY_GIGABIT) {
 731                 np->gigabit = PHY_GIGABIT;
 732                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
 733                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 734                 if (phyinterface & PHY_RGMII)
 735                         mii_control_1000 |= ADVERTISE_1000FULL;
 736                 else
 737                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 738
 739                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 740                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 741                         return PHY_ERROR;
 742                 }
 743         }
 744         else
 745                 np->gigabit = 0;
 746
 747         /* reset the phy */
 748         if (phy_reset(dev)) {
 749                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
 750                 return PHY_ERROR;
 751         }
 752
 753         /* phy vendor specific configuration */
 754         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
 755                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
 756                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 757                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 758                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
 759                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 760                         return PHY_ERROR;
 761                 }
 762                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
 763                 phy_reserved |= PHY_INIT5;
 764                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 765                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 766                         return PHY_ERROR;
 767                 }
 768         }
 769         if (np->phy_oui == PHY_OUI_CICADA) {
 770                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
 771                 phy_reserved |= PHY_INIT6;
 772                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
 773                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 774                         return PHY_ERROR;
 775                 }
 776         }
 777
 778         /* restart auto negotiation */
 779         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 780         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 781         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
 782                 return PHY_ERROR;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static void nv_start_rx(struct net_device *dev)
 789 {
 790         struct fe_priv *np = netdev_priv(dev);
 791         u8 __iomem *base = get_hwbase(dev);
 792
 793         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
 794         /* Already running? Stop it. */
 795         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 796                 writel(0, base + NvRegReceiverControl);
 797                 pci_push(base);
 798         }
 799         writel(np->linkspeed, base + NvRegLinkSpeed);
 800         pci_push(base);
 801         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 802         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
 803                                 dev->name, np->duplex, np->linkspeed);
 804         pci_push(base);
 805 }
 806
 807 static void nv_stop_rx(struct net_device *dev)
 808 {
 809         u8 __iomem *base = get_hwbase(dev);
 810
 811         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
 812         writel(0, base + NvRegReceiverControl);
 813         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 814                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 815                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
 816
 817         udelay(NV_RXSTOP_DELAY2);
 818         writel(0, base + NvRegLinkSpeed);
 819 }
 820
 821 static void nv_start_tx(struct net_device *dev)
 822 {
 823         u8 __iomem *base = get_hwbase(dev);
 824
 825         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
 826         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 827         pci_push(base);
 828 }
 829
 830 static void nv_stop_tx(struct net_device *dev)
 831 {
 832         u8 __iomem *base = get_hwbase(dev);
 833
 834         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
 835         writel(0, base + NvRegTransmitterControl);
 836         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 837                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 838                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
 839
 840         udelay(NV_TXSTOP_DELAY2);
 841         writel(0, base + NvRegUnknownTransmitterReg);
 842 }
 843
 844 static void nv_txrx_reset(struct net_device *dev)
 845 {
 846         struct fe_priv *np = netdev_priv(dev);
 847         u8 __iomem *base = get_hwbase(dev);
 848
 849         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
 850         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
 851         pci_push(base);
 852         udelay(NV_TXRX_RESET_DELAY);
 853         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
 854         pci_push(base);
 855 }
 856
 857 /*
 858  * nv_get_stats: dev->get_stats function
 859  * Get latest stats value from the nic.
 860  * Called with read_lock(&dev_base_lock) held for read -
 861  * only synchronized against unregister_netdevice.
 862  */
 863 static struct net_device_stats *nv_get_stats(struct net_device *dev)
 864 {
 865         struct fe_priv *np = netdev_priv(dev);
 866
 867         /* It seems that the nic always generates interrupts and doesn't
 868          * accumulate errors internally. Thus the current values in np->stats
 869          * are already up to date.
 870          */
 871         return &np->stats;
 872 }
 873
 874 /*
 875  * nv_alloc_rx: fill rx ring entries.
 876  * Return 1 if the allocations for the skbs failed and the
 877  * rx engine is without Available descriptors
 878  */
 879 static int nv_alloc_rx(struct net_device *dev)
 880 {
 881         struct fe_priv *np = netdev_priv(dev);
 882         unsigned int refill_rx = np->refill_rx;
 883         int nr;
 884
 885         while (np->cur_rx != refill_rx) {
 886                 struct sk_buff *skb;
 887
 888                 nr = refill_rx % RX_RING;
 889                 if (np->rx_skbuff[nr] == NULL) {
 890
 891                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
 892                         if (!skb)
 893                                 break;
 894
 895                         skb->dev = dev;
 896                         np->rx_skbuff[nr] = skb;
 897                 } else {
 898                         skb = np->rx_skbuff[nr];
 899                 }
 900                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
 901                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
 902                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 903                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
 904                         wmb();
 905                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
 906                 } else {
 907                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
 908                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
 909                         wmb();
 910                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
 911                 }
 912                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
 913                                         dev->name, refill_rx);
 914                 refill_rx++;
 915         }
 916         np->refill_rx = refill_rx;
 917         if (np->cur_rx - refill_rx == RX_RING)
 918                 return 1;
 919         return 0;
 920 }
 921
 922 static void nv_do_rx_refill(unsigned long data)
 923 {
 924         struct net_device *dev = (struct net_device *) data;
 925         struct fe_priv *np = netdev_priv(dev);
 926
 927         disable_irq(dev->irq);
 928         if (nv_alloc_rx(dev)) {
 929                 spin_lock(&np->lock);
 930                 if (!np->in_shutdown)
 931                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
 932                 spin_unlock(&np->lock);
 933         }
 934         enable_irq(dev->irq);
 935 }
 936
 937 static void nv_init_rx(struct net_device *dev)
 938 {
 939         struct fe_priv *np = netdev_priv(dev);
 940         int i;
 941
 942         np->cur_rx = RX_RING;
 943         np->refill_rx = 0;
 944         for (i = 0; i < RX_RING; i++)
 945                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 946                         np->rx_ring.orig[i].FlagLen = 0;
 947                 else
 948                         np->rx_ring.ex[i].FlagLen = 0;
 949 }
 950
 951 static void nv_init_tx(struct net_device *dev)
 952 {
 953         struct fe_priv *np = netdev_priv(dev);
 954         int i;
 955
 956         np->next_tx = np->nic_tx = 0;
 957         for (i = 0; i < TX_RING; i++) {
 958                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 959                         np->tx_ring.orig[i].FlagLen = 0;
 960                 else
 961                         np->tx_ring.ex[i].FlagLen = 0;
 962                 np->tx_skbuff[i] = NULL;
 963                 np->tx_dma[i] = 0;
 964         }
 965 }
 966
 967 static int nv_init_ring(struct net_device *dev)
 968 {
 969         nv_init_tx(dev);
 970         nv_init_rx(dev);
 971         return nv_alloc_rx(dev);
 972 }
 973
 974 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
 975 {
 976         struct fe_priv *np = netdev_priv(dev);
 977
 978         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
 979                 dev->name, skbnr);
 980
 981         if (np->tx_dma[skbnr]) {
 982                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
 983                                np->tx_dma_len[skbnr],
 984                                PCI_DMA_TODEVICE);
 985                 np->tx_dma[skbnr] = 0;
 986         }
 987
 988         if (np->tx_skbuff[skbnr]) {
 989                 dev_kfree_skb_irq(np->tx_skbuff[skbnr]);
 990                 np->tx_skbuff[skbnr] = NULL;
 991                 return 1;
 992         } else {
 993                 return 0;
 994         }
 995 }
 996
 997 static void nv_drain_tx(struct net_device *dev)
 998 {
 999         struct fe_priv *np = netdev_priv(dev);
1000         unsigned int i;
1001
1002         for (i = 0; i < TX_RING; i++) {
1003                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1004                         np->tx_ring.orig[i].FlagLen = 0;
1005                 else
1006                         np->tx_ring.ex[i].FlagLen = 0;
1007                 if (nv_release_txskb(dev, i))
1008                         np->stats.tx_dropped++;
1009         }
1010 }
1011
1012 static void nv_drain_rx(struct net_device *dev)
1013 {
1014         struct fe_priv *np = netdev_priv(dev);
1015         int i;
1016         for (i = 0; i < RX_RING; i++) {
1017                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1018                         np->rx_ring.orig[i].FlagLen = 0;
1019                 else
1020                         np->rx_ring.ex[i].FlagLen = 0;
1021                 wmb();
1022                 if (np->rx_skbuff[i]) {
1023                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1024                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1025                                                 PCI_DMA_FROMDEVICE);
1026                         dev_kfree_skb(np->rx_skbuff[i]);
1027                         np->rx_skbuff[i] = NULL;
1028                 }
1029         }
1030 }
1031
1032 static void drain_ring(struct net_device *dev)
1033 {
1034         nv_drain_tx(dev);
1035         nv_drain_rx(dev);
1036 }
1037
1038 /*
1039  * nv_start_xmit: dev->hard_start_xmit function
1040  * Called with dev->xmit_lock held.
1041  */
1042 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1043 {
1044         struct fe_priv *np = netdev_priv(dev);
1045         u32 tx_flags = 0;
1046         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1047         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1048         unsigned int nr = (np->next_tx - 1) % TX_RING;
1049         unsigned int start_nr = np->next_tx % TX_RING;
1050         unsigned int i;
1051         u32 offset = 0;
1052         u32 bcnt;
1053         u32 size = skb->len-skb->data_len;
1054         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1055         u32 tx_flags_vlan = 0;
1056
1057         /* add fragments to entries count */
1058         for (i = 0; i < fragments; i++) {
1059                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1060                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1061         }
1062
1063         spin_lock_irq(&np->lock);
1064
1065         if ((np->next_tx - np->nic_tx + entries - 1) > TX_LIMIT_STOP) {
1066                 spin_unlock_irq(&np->lock);
1067                 netif_stop_queue(dev);
1068                 return NETDEV_TX_BUSY;
1069         }
1070
1071         /* setup the header buffer */
1072         do {
1073                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1074                 nr = (nr + 1) % TX_RING;
1075
1076                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1077                                                 PCI_DMA_TODEVICE);
1078                 np->tx_dma_len[nr] = bcnt;
1079
1080                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1081                         np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1082                         np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1083                 } else {
1084                         np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1085                         np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1086                         np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1087                 }
1088                 tx_flags = np->tx_flags;
1089                 offset += bcnt;
1090                 size -= bcnt;
1091         } while(size);
1092
1093         /* setup the fragments */
1094         for (i = 0; i < fragments; i++) {
1095                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1096                 u32 size = frag->size;
1097                 offset = 0;
1098
1099                 do {
1100                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1101                         nr = (nr + 1) % TX_RING;
1102
1103                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1104                                                       PCI_DMA_TODEVICE);
1105                         np->tx_dma_len[nr] = bcnt;
1106
1107                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1108                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1109                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1110                         } else {
1111                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1112                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1113                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1114                         }
1115                         offset += bcnt;
1116                         size -= bcnt;
1117                 } while (size);
1118         }
1119
1120         /* set last fragment flag  */
1121         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1122                 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1123         } else {
1124                 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1125         }
1126
1127         np->tx_skbuff[nr] = skb;
1128
1129 #ifdef NETIF_F_TSO
1130         if (skb_shinfo(skb)->tso_size)
1131                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1132         else
1133 #endif
1134         tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1135
1136         /* vlan tag */
1137         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1138                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1139         }
1140
1141         /* set tx flags */
1142         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1143                 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1144         } else {
1145                 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1146                 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1147         }
1148
1149         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1150                 dev->name, np->next_tx, entries, tx_flags_extra);
1151         {
1152                 int j;
1153                 for (j=0; j<64; j++) {
1154                         if ((j%16) == 0)
1155                                 dprintk("\n%03x:", j);
1156                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1157                 }
1158                 dprintk("\n");
1159         }
1160
1161         np->next_tx += entries;
1162
1163         dev->trans_start = jiffies;
1164         spin_unlock_irq(&np->lock);
1165         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1166         pci_push(get_hwbase(dev));
1167         return NETDEV_TX_OK;
1168 }
1169
1170 /*
1171  * nv_tx_done: check for completed packets, release the skbs.
1172  *
1173  * Caller must own np->lock.
1174  */
1175 static void nv_tx_done(struct net_device *dev)
1176 {
1177         struct fe_priv *np = netdev_priv(dev);
1178         u32 Flags;
1179         unsigned int i;
1180         struct sk_buff *skb;
1181
1182         while (np->nic_tx != np->next_tx) {
1183                 i = np->nic_tx % TX_RING;
1184
1185                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1186                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1187                 else
1188                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1189
1190                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1191                                         dev->name, np->nic_tx, Flags);
1192                 if (Flags & NV_TX_VALID)
1193                         break;
1194                 if (np->desc_ver == DESC_VER_1) {
1195                         if (Flags & NV_TX_LASTPACKET) {
1196                                 skb = np->tx_skbuff[i];
1197                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1198                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1199                                         if (Flags & NV_TX_UNDERFLOW)
1200                                                 np->stats.tx_fifo_errors++;
1201                                         if (Flags & NV_TX_CARRIERLOST)
1202                                                 np->stats.tx_carrier_errors++;
1203                                         np->stats.tx_errors++;
1204                                 } else {
1205                                         np->stats.tx_packets++;
1206                                         np->stats.tx_bytes += skb->len;
1207                                 }
1208                         }
1209                 } else {
1210                         if (Flags & NV_TX2_LASTPACKET) {
1211                                 skb = np->tx_skbuff[i];
1212                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1213                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1214                                         if (Flags & NV_TX2_UNDERFLOW)
1215                                                 np->stats.tx_fifo_errors++;
1216                                         if (Flags & NV_TX2_CARRIERLOST)
1217                                                 np->stats.tx_carrier_errors++;
1218                                         np->stats.tx_errors++;
1219                                 } else {
1220                                         np->stats.tx_packets++;
1221                                         np->stats.tx_bytes += skb->len;
1222                                 }
1223                         }
1224                 }
1225                 nv_release_txskb(dev, i);
1226                 np->nic_tx++;
1227         }
1228         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1229                 netif_wake_queue(dev);
1230 }
1231
1232 /*
1233  * nv_tx_timeout: dev->tx_timeout function
1234  * Called with dev->xmit_lock held.
1235  */
1236 static void nv_tx_timeout(struct net_device *dev)
1237 {
1238         struct fe_priv *np = netdev_priv(dev);
1239         u8 __iomem *base = get_hwbase(dev);
1240
1241         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1242                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1243
1244         {
1245                 int i;
1246
1247                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1248                                 dev->name, (unsigned long)np->ring_addr,
1249                                 np->next_tx, np->nic_tx);
1250                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1251                 for (i=0;i<0x400;i+= 32) {
1252                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1253                                         i,
1254                                         readl(base + i + 0), readl(base + i + 4),
1255                                         readl(base + i + 8), readl(base + i + 12),
1256                                         readl(base + i + 16), readl(base + i + 20),
1257                                         readl(base + i + 24), readl(base + i + 28));
1258                 }
1259                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1260                 for (i=0;i<TX_RING;i+= 4) {
1261                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1262                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1263                                        i,
1264                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1265                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1266                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1267                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1268                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1269                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1270                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1271                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1272                         } else {
1273                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1274                                        i,
1275                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1276                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1277                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1278                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1279                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1280                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1281                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1282                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1283                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1284                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1285                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1286                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1287                         }
1288                 }
1289         }
1290
1291         spin_lock_irq(&np->lock);
1292
1293         /* 1) stop tx engine */
1294         nv_stop_tx(dev);
1295
1296         /* 2) check that the packets were not sent already: */
1297         nv_tx_done(dev);
1298
1299         /* 3) if there are dead entries: clear everything */
1300         if (np->next_tx != np->nic_tx) {
1301                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1302                 nv_drain_tx(dev);
1303                 np->next_tx = np->nic_tx = 0;
1304                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1305                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1306                 else
1307                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1308                 netif_wake_queue(dev);
1309         }
1310
1311         /* 4) restart tx engine */
1312         nv_start_tx(dev);
1313         spin_unlock_irq(&np->lock);
1314 }
1315
1316 /*
1317  * Called when the nic notices a mismatch between the actual data len on the
1318  * wire and the len indicated in the 802 header
1319  */
1320 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1321 {
1322         int hdrlen;     /* length of the 802 header */
1323         int protolen;   /* length as stored in the proto field */
1324
1325         /* 1) calculate len according to header */
1326         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1327                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1328                 hdrlen = VLAN_HLEN;
1329         } else {
1330                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1331                 hdrlen = ETH_HLEN;
1332         }
1333         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1334                                 dev->name, datalen, protolen, hdrlen);
1335         if (protolen > ETH_DATA_LEN)
1336                 return datalen; /* Value in proto field not a len, no checks possible */
1337
1338         protolen += hdrlen;
1339         /* consistency checks: */
1340         if (datalen > ETH_ZLEN) {
1341                 if (datalen >= protolen) {
1342                         /* more data on wire than in 802 header, trim of
1343                          * additional data.
1344                          */
1345                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1346                                         dev->name, protolen);
1347                         return protolen;
1348                 } else {
1349                         /* less data on wire than mentioned in header.
1350                          * Discard the packet.
1351                          */
1352                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1353                                         dev->name);
1354                         return -1;
1355                 }
1356         } else {
1357                 /* short packet. Accept only if 802 values are also short */
1358                 if (protolen > ETH_ZLEN) {
1359                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1360                                         dev->name);
1361                         return -1;
1362                 }
1363                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1364                                 dev->name, datalen);
1365                 return datalen;
1366         }
1367 }
1368
1369 static void nv_rx_process(struct net_device *dev)
1370 {
1371         struct fe_priv *np = netdev_priv(dev);
1372         u32 Flags;
1373         u32 vlanflags = 0;
1374
1375
1376         for (;;) {
1377                 struct sk_buff *skb;
1378                 int len;
1379                 int i;
1380                 if (np->cur_rx - np->refill_rx >= RX_RING)
1381                         break;  /* we scanned the whole ring - do not continue */
1382
1383                 i = np->cur_rx % RX_RING;
1384                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1385                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1386                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1387                 } else {
1388                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1389                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1390                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1391                 }
1392
1393                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1394                                         dev->name, np->cur_rx, Flags);
1395
1396                 if (Flags & NV_RX_AVAIL)
1397                         break;  /* still owned by hardware, */
1398
1399                 /*
1400                  * the packet is for us - immediately tear down the pci mapping.
1401                  * TODO: check if a prefetch of the first cacheline improves
1402                  * the performance.
1403                  */
1404                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1405                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1406                                 PCI_DMA_FROMDEVICE);
1407
1408                 {
1409                         int j;
1410                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1411                         for (j=0; j<64; j++) {
1412                                 if ((j%16) == 0)
1413                                         dprintk("\n%03x:", j);
1414                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1415                         }
1416                         dprintk("\n");
1417                 }
1418                 /* look at what we actually got: */
1419                 if (np->desc_ver == DESC_VER_1) {
1420                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1421                                 goto next_pkt;
1422
1423                         if (Flags & NV_RX_ERROR) {
1424                                 if (Flags & NV_RX_MISSEDFRAME) {
1425                                         np->stats.rx_missed_errors++;
1426                                         np->stats.rx_errors++;
1427                                         goto next_pkt;
1428                                 }
1429                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1430                                         np->stats.rx_errors++;
1431                                         goto next_pkt;
1432                                 }
1433                                 if (Flags & NV_RX_CRCERR) {
1434                                         np->stats.rx_crc_errors++;
1435                                         np->stats.rx_errors++;
1436                                         goto next_pkt;
1437                                 }
1438                                 if (Flags & NV_RX_OVERFLOW) {
1439                                         np->stats.rx_over_errors++;
1440                                         np->stats.rx_errors++;
1441                                         goto next_pkt;
1442                                 }
1443                                 if (Flags & NV_RX_ERROR4) {
1444                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1445                                         if (len < 0) {
1446                                                 np->stats.rx_errors++;
1447                                                 goto next_pkt;
1448                                         }
1449                                 }
1450                                 /* framing errors are soft errors. */
1451                                 if (Flags & NV_RX_FRAMINGERR) {
1452                                         if (Flags & NV_RX_SUBSTRACT1) {
1453                                                 len--;
1454                                         }
1455                                 }
1456                         }
1457                 } else {
1458                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1459                                 goto next_pkt;
1460
1461                         if (Flags & NV_RX2_ERROR) {
1462                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1463                                         np->stats.rx_errors++;
1464                                         goto next_pkt;
1465                                 }
1466                                 if (Flags & NV_RX2_CRCERR) {
1467                                         np->stats.rx_crc_errors++;
1468                                         np->stats.rx_errors++;
1469                                         goto next_pkt;
1470                                 }
1471                                 if (Flags & NV_RX2_OVERFLOW) {
1472                                         np->stats.rx_over_errors++;
1473                                         np->stats.rx_errors++;
1474                                         goto next_pkt;
1475                                 }
1476                                 if (Flags & NV_RX2_ERROR4) {
1477                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1478                                         if (len < 0) {
1479                                                 np->stats.rx_errors++;
1480                                                 goto next_pkt;
1481                                         }
1482                                 }
1483                                 /* framing errors are soft errors */
1484                                 if (Flags & NV_RX2_FRAMINGERR) {
1485                                         if (Flags & NV_RX2_SUBSTRACT1) {
1486                                                 len--;
1487                                         }
1488                                 }
1489                         }
1490                         Flags &= NV_RX2_CHECKSUMMASK;
1491                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1492                                         Flags == NV_RX2_CHECKSUMOK2 ||
1493                                         Flags == NV_RX2_CHECKSUMOK3) {
1494                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1495                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1496                         } else {
1497                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1498                         }
1499                 }
1500                 /* got a valid packet - forward it to the network core */
1501                 skb = np->rx_skbuff[i];
1502                 np->rx_skbuff[i] = NULL;
1503
1504                 skb_put(skb, len);
1505                 skb->protocol = eth_type_trans(skb, dev);
1506                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1507                                         dev->name, np->cur_rx, len, skb->protocol);
1508                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1509                         vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1510                 } else {
1511                         netif_rx(skb);
1512                 }
1513                 dev->last_rx = jiffies;
1514                 np->stats.rx_packets++;
1515                 np->stats.rx_bytes += len;
1516 next_pkt:
1517                 np->cur_rx++;
1518         }
1519 }
1520
1521 static void set_bufsize(struct net_device *dev)
1522 {
1523         struct fe_priv *np = netdev_priv(dev);
1524
1525         if (dev->mtu <= ETH_DATA_LEN)
1526                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1527         else
1528                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1529 }
1530
1531 /*
1532  * nv_change_mtu: dev->change_mtu function
1533  * Called with dev_base_lock held for read.
1534  */
1535 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1536 {
1537         struct fe_priv *np = netdev_priv(dev);
1538         int old_mtu;
1539
1540         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1541                 return -EINVAL;
1542
1543         old_mtu = dev->mtu;
1544         dev->mtu = new_mtu;
1545
1546         /* return early if the buffer sizes will not change */
1547         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1548                 return 0;
1549         if (old_mtu == new_mtu)
1550                 return 0;
1551
1552         /* synchronized against open : rtnl_lock() held by caller */
1553         if (netif_running(dev)) {
1554                 u8 __iomem *base = get_hwbase(dev);
1555                 /*
1556                  * It seems that the nic preloads valid ring entries into an
1557                  * internal buffer. The procedure for flushing everything is
1558                  * guessed, there is probably a simpler approach.
1559                  * Changing the MTU is a rare event, it shouldn't matter.
1560                  */
1561                 disable_irq(dev->irq);
1562                 spin_lock_bh(&dev->xmit_lock);
1563                 spin_lock(&np->lock);
1564                 /* stop engines */
1565                 nv_stop_rx(dev);
1566                 nv_stop_tx(dev);
1567                 nv_txrx_reset(dev);
1568                 /* drain rx queue */
1569                 nv_drain_rx(dev);
1570                 nv_drain_tx(dev);
1571                 /* reinit driver view of the rx queue */
1572                 nv_init_rx(dev);
1573                 nv_init_tx(dev);
1574                 /* alloc new rx buffers */
1575                 set_bufsize(dev);
1576                 if (nv_alloc_rx(dev)) {
1577                         if (!np->in_shutdown)
1578                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1579                 }
1580                 /* reinit nic view of the rx queue */
1581                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1582                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1583                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1584                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1585                 else
1586                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1587                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1588                         base + NvRegRingSizes);
1589                 pci_push(base);
1590                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1591                 pci_push(base);
1592
1593                 /* restart rx engine */
1594                 nv_start_rx(dev);
1595                 nv_start_tx(dev);
1596                 spin_unlock(&np->lock);
1597                 spin_unlock_bh(&dev->xmit_lock);
1598                 enable_irq(dev->irq);
1599         }
1600         return 0;
1601 }
1602
1603 static void nv_copy_mac_to_hw(struct net_device *dev)
1604 {
1605         u8 __iomem *base = get_hwbase(dev);
1606         u32 mac[2];
1607
1608         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1609                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1610         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1611
1612         writel(mac[0], base + NvRegMacAddrA);
1613         writel(mac[1], base + NvRegMacAddrB);
1614 }
1615
1616 /*
1617  * nv_set_mac_address: dev->set_mac_address function
1618  * Called with rtnl_lock() held.
1619  */
1620 static int nv_set_mac_address(struct net_device *dev, void *addr)
1621 {
1622         struct fe_priv *np = netdev_priv(dev);
1623         struct sockaddr *macaddr = (struct sockaddr*)addr;
1624
1625         if(!is_valid_ether_addr(macaddr->sa_data))
1626                 return -EADDRNOTAVAIL;
1627
1628         /* synchronized against open : rtnl_lock() held by caller */
1629         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1630
1631         if (netif_running(dev)) {
1632                 spin_lock_bh(&dev->xmit_lock);
1633                 spin_lock_irq(&np->lock);
1634
1635                 /* stop rx engine */
1636                 nv_stop_rx(dev);
1637
1638                 /* set mac address */
1639                 nv_copy_mac_to_hw(dev);
1640
1641                 /* restart rx engine */
1642                 nv_start_rx(dev);
1643                 spin_unlock_irq(&np->lock);
1644                 spin_unlock_bh(&dev->xmit_lock);
1645         } else {
1646                 nv_copy_mac_to_hw(dev);
1647         }
1648         return 0;
1649 }
1650
1651 /*
1652  * nv_set_multicast: dev->set_multicast function
1653  * Called with dev->xmit_lock held.
1654  */
1655 static void nv_set_multicast(struct net_device *dev)
1656 {
1657         struct fe_priv *np = netdev_priv(dev);
1658         u8 __iomem *base = get_hwbase(dev);
1659         u32 addr[2];
1660         u32 mask[2];
1661         u32 pff;
1662
1663         memset(addr, 0, sizeof(addr));
1664         memset(mask, 0, sizeof(mask));
1665
1666         if (dev->flags & IFF_PROMISC) {
1667                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1668                 pff = NVREG_PFF_PROMISC;
1669         } else {
1670                 pff = NVREG_PFF_MYADDR;
1671
1672                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1673                         u32 alwaysOff[2];
1674                         u32 alwaysOn[2];
1675
1676                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1677                         if (dev->flags & IFF_ALLMULTI) {
1678                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1679                         } else {
1680                                 struct dev_mc_list *walk;
1681
1682                                 walk = dev->mc_list;
1683                                 while (walk != NULL) {
1684                                         u32 a, b;
1685                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1686                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1687                                         alwaysOn[0] &= a;
1688                                         alwaysOff[0] &= ~a;
1689                                         alwaysOn[1] &= b;
1690                                         alwaysOff[1] &= ~b;
1691                                         walk = walk->next;
1692                                 }
1693                         }
1694                         addr[0] = alwaysOn[0];
1695                         addr[1] = alwaysOn[1];
1696                         mask[0] = alwaysOn[0] | alwaysOff[0];
1697                         mask[1] = alwaysOn[1] | alwaysOff[1];
1698                 }
1699         }
1700         addr[0] |= NVREG_MCASTADDRA_FORCE;
1701         pff |= NVREG_PFF_ALWAYS;
1702         spin_lock_irq(&np->lock);
1703         nv_stop_rx(dev);
1704         writel(addr[0], base + NvRegMulticastAddrA);
1705         writel(addr[1], base + NvRegMulticastAddrB);
1706         writel(mask[0], base + NvRegMulticastMaskA);
1707         writel(mask[1], base + NvRegMulticastMaskB);
1708         writel(pff, base + NvRegPacketFilterFlags);
1709         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1710                 dev->name);
1711         nv_start_rx(dev);
1712         spin_unlock_irq(&np->lock);
1713 }
1714
1715 /**
1716  * nv_update_linkspeed: Setup the MAC according to the link partner
1717  * @dev: Network device to be configured
1718  *
1719  * The function queries the PHY and checks if there is a link partner.
1720  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1721  * set to 10 MBit HD.
1722  *
1723  * The function returns 0 if there is no link partner and 1 if there is
1724  * a good link partner.
1725  */
1726 static int nv_update_linkspeed(struct net_device *dev)
1727 {
1728         struct fe_priv *np = netdev_priv(dev);
1729         u8 __iomem *base = get_hwbase(dev);
1730         int adv, lpa;
1731         int newls = np->linkspeed;
1732         int newdup = np->duplex;
1733         int mii_status;
1734         int retval = 0;
1735         u32 control_1000, status_1000, phyreg;
1736
1737         /* BMSR_LSTATUS is latched, read it twice:
1738          * we want the current value.
1739          */
1740         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1741         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1742
1743         if (!(mii_status & BMSR_LSTATUS)) {
1744                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1745                                 dev->name);
1746                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1747                 newdup = 0;
1748                 retval = 0;
1749                 goto set_speed;
1750         }
1751
1752         if (np->autoneg == 0) {
1753                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1754                                 dev->name, np->fixed_mode);
1755                 if (np->fixed_mode & LPA_100FULL) {
1756                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1757                         newdup = 1;
1758                 } else if (np->fixed_mode & LPA_100HALF) {
1759                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1760                         newdup = 0;
1761                 } else if (np->fixed_mode & LPA_10FULL) {
1762                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1763                         newdup = 1;
1764                 } else {
1765                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1766                         newdup = 0;
1767                 }
1768                 retval = 1;
1769                 goto set_speed;
1770         }
1771         /* check auto negotiation is complete */
1772         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1773                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1774                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1775                 newdup = 0;
1776                 retval = 0;
1777                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1778                 goto set_speed;
1779         }
1780
1781         retval = 1;
1782         if (np->gigabit == PHY_GIGABIT) {
1783                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1784                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1785
1786                 if ((control_1000 & ADVERTISE_1000FULL) &&
1787                         (status_1000 & LPA_1000FULL)) {
1788                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1789                                 dev->name);
1790                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1791                         newdup = 1;
1792                         goto set_speed;
1793                 }
1794         }
1795
1796         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1797         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1798         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1799                                 dev->name, adv, lpa);
1800
1801         /* FIXME: handle parallel detection properly */
1802         lpa = lpa & adv;
1803         if (lpa & LPA_100FULL) {
1804                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1805                 newdup = 1;
1806         } else if (lpa & LPA_100HALF) {
1807                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1808                 newdup = 0;
1809         } else if (lpa & LPA_10FULL) {
1810                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1811                 newdup = 1;
1812         } else if (lpa & LPA_10HALF) {
1813                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1814                 newdup = 0;
1815         } else {
1816                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1817                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1818                 newdup = 0;
1819         }
1820
1821 set_speed:
1822         if (np->duplex == newdup && np->linkspeed == newls)
1823                 return retval;
1824
1825         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1826                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1827
1828         np->duplex = newdup;
1829         np->linkspeed = newls;
1830
1831         if (np->gigabit == PHY_GIGABIT) {
1832                 phyreg = readl(base + NvRegRandomSeed);
1833                 phyreg &= ~(0x3FF00);
1834                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1835                         phyreg |= NVREG_RNDSEED_FORCE3;
1836                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1837                         phyreg |= NVREG_RNDSEED_FORCE2;
1838                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1839                         phyreg |= NVREG_RNDSEED_FORCE;
1840                 writel(phyreg, base + NvRegRandomSeed);
1841         }
1842
1843         phyreg = readl(base + NvRegPhyInterface);
1844         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1845         if (np->duplex == 0)
1846                 phyreg |= PHY_HALF;
1847         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1848                 phyreg |= PHY_100;
1849         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1850                 phyreg |= PHY_1000;
1851         writel(phyreg, base + NvRegPhyInterface);
1852
1853         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1854                 base + NvRegMisc1);
1855         pci_push(base);
1856         writel(np->linkspeed, base + NvRegLinkSpeed);
1857         pci_push(base);
1858
1859         return retval;
1860 }
1861
1862 static void nv_linkchange(struct net_device *dev)
1863 {
1864         if (nv_update_linkspeed(dev)) {
1865                 if (!netif_carrier_ok(dev)) {
1866                         netif_carrier_on(dev);
1867                         printk(KERN_INFO "%s: link up.\n", dev->name);
1868                         nv_start_rx(dev);
1869                 }
1870         } else {
1871                 if (netif_carrier_ok(dev)) {
1872                         netif_carrier_off(dev);
1873                         printk(KERN_INFO "%s: link down.\n", dev->name);
1874                         nv_stop_rx(dev);
1875                 }
1876         }
1877 }
1878
1879 static void nv_link_irq(struct net_device *dev)
1880 {
1881         u8 __iomem *base = get_hwbase(dev);
1882         u32 miistat;
1883
1884         miistat = readl(base + NvRegMIIStatus);
1885         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1886         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1887
1888         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1889                 nv_linkchange(dev);
1890         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1891 }
1892
1893 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1894 {
1895         struct net_device *dev = (struct net_device *) data;
1896         struct fe_priv *np = netdev_priv(dev);
1897         u8 __iomem *base = get_hwbase(dev);
1898         u32 events;
1899         int i;
1900
1901         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1902
1903         for (i=0; ; i++) {
1904                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1905                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1906                 pci_push(base);
1907                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1908                 if (!(events & np->irqmask))
1909                         break;
1910
1911                 spin_lock(&np->lock);
1912                 nv_tx_done(dev);
1913                 spin_unlock(&np->lock);
1914
1915                 nv_rx_process(dev);
1916                 if (nv_alloc_rx(dev)) {
1917                         spin_lock(&np->lock);
1918                         if (!np->in_shutdown)
1919                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1920                         spin_unlock(&np->lock);
1921                 }
1922
1923                 if (events & NVREG_IRQ_LINK) {
1924                         spin_lock(&np->lock);
1925                         nv_link_irq(dev);
1926                         spin_unlock(&np->lock);
1927                 }
1928                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1929                         spin_lock(&np->lock);
1930                         nv_linkchange(dev);
1931                         spin_unlock(&np->lock);
1932                         np->link_timeout = jiffies + LINK_TIMEOUT;
1933                 }
1934                 if (events & (NVREG_IRQ_TX_ERR)) {
1935                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1936                                                 dev->name, events);
1937                 }
1938                 if (events & (NVREG_IRQ_UNKNOWN)) {
1939                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1940                                                 dev->name, events);
1941                 }
1942                 if (i > max_interrupt_work) {
1943                         spin_lock(&np->lock);
1944                         /* disable interrupts on the nic */
1945                         writel(0, base + NvRegIrqMask);
1946                         pci_push(base);
1947
1948                         if (!np->in_shutdown)
1949                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1950                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1951                         spin_unlock(&np->lock);
1952                         break;
1953                 }
1954
1955         }
1956         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1957
1958         return IRQ_RETVAL(i);
1959 }
1960
1961 static void nv_do_nic_poll(unsigned long data)
1962 {
1963         struct net_device *dev = (struct net_device *) data;
1964         struct fe_priv *np = netdev_priv(dev);
1965         u8 __iomem *base = get_hwbase(dev);
1966
1967         disable_irq(dev->irq);
1968         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1969         /*
1970          * reenable interrupts on the nic, we have to do this before calling
1971          * nv_nic_irq because that may decide to do otherwise
1972          */
1973         writel(np->irqmask, base + NvRegIrqMask);
1974         pci_push(base);
1975         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1976         enable_irq(dev->irq);
1977 }
1978
1979 #ifdef CONFIG_NET_POLL_CONTROLLER
1980 static void nv_poll_controller(struct net_device *dev)
1981 {
1982         nv_do_nic_poll((unsigned long) dev);
1983 }
1984 #endif
1985
1986 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1987 {
1988         struct fe_priv *np = netdev_priv(dev);
1989         strcpy(info->driver, "forcedeth");
1990         strcpy(info->version, FORCEDETH_VERSION);
1991         strcpy(info->bus_info, pci_name(np->pci_dev));
1992 }
1993
1994 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1995 {
1996         struct fe_priv *np = netdev_priv(dev);
1997         wolinfo->supported = WAKE_MAGIC;
1998
1999         spin_lock_irq(&np->lock);
2000         if (np->wolenabled)
2001                 wolinfo->wolopts = WAKE_MAGIC;
2002         spin_unlock_irq(&np->lock);
2003 }
2004
2005 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2006 {
2007         struct fe_priv *np = netdev_priv(dev);
2008         u8 __iomem *base = get_hwbase(dev);
2009
2010         spin_lock_irq(&np->lock);
2011         if (wolinfo->wolopts == 0) {
2012                 writel(0, base + NvRegWakeUpFlags);
2013                 np->wolenabled = 0;
2014         }
2015         if (wolinfo->wolopts & WAKE_MAGIC) {
2016                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
2017                 np->wolenabled = 1;
2018         }
2019         spin_unlock_irq(&np->lock);
2020         return 0;
2021 }
2022
2023 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2024 {
2025         struct fe_priv *np = netdev_priv(dev);
2026         int adv;
2027
2028         spin_lock_irq(&np->lock);
2029         ecmd->port = PORT_MII;
2030         if (!netif_running(dev)) {
2031                 /* We do not track link speed / duplex setting if the
2032                  * interface is disabled. Force a link check */
2033                 nv_update_linkspeed(dev);
2034         }
2035         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2036                 case NVREG_LINKSPEED_10:
2037                         ecmd->speed = SPEED_10;
2038                         break;
2039                 case NVREG_LINKSPEED_100:
2040                         ecmd->speed = SPEED_100;
2041                         break;
2042                 case NVREG_LINKSPEED_1000:
2043                         ecmd->speed = SPEED_1000;
2044                         break;
2045         }
2046         ecmd->duplex = DUPLEX_HALF;
2047         if (np->duplex)
2048                 ecmd->duplex = DUPLEX_FULL;
2049
2050         ecmd->autoneg = np->autoneg;
2051
2052         ecmd->advertising = ADVERTISED_MII;
2053         if (np->autoneg) {
2054                 ecmd->advertising |= ADVERTISED_Autoneg;
2055                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2056         } else {
2057                 adv = np->fixed_mode;
2058         }
2059         if (adv & ADVERTISE_10HALF)
2060                 ecmd->advertising |= ADVERTISED_10baseT_Half;
2061         if (adv & ADVERTISE_10FULL)
2062                 ecmd->advertising |= ADVERTISED_10baseT_Full;
2063         if (adv & ADVERTISE_100HALF)
2064                 ecmd->advertising |= ADVERTISED_100baseT_Half;
2065         if (adv & ADVERTISE_100FULL)
2066                 ecmd->advertising |= ADVERTISED_100baseT_Full;
2067         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
2068                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2069                 if (adv & ADVERTISE_1000FULL)
2070                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
2071         }
2072
2073         ecmd->supported = (SUPPORTED_Autoneg |
2074                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2075                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2076                 SUPPORTED_MII);
2077         if (np->gigabit == PHY_GIGABIT)
2078                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2079
2080         ecmd->phy_address = np->phyaddr;
2081         ecmd->transceiver = XCVR_EXTERNAL;
2082
2083         /* ignore maxtxpkt, maxrxpkt for now */
2084         spin_unlock_irq(&np->lock);
2085         return 0;
2086 }
2087
2088 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2089 {
2090         struct fe_priv *np = netdev_priv(dev);
2091
2092         if (ecmd->port != PORT_MII)
2093                 return -EINVAL;
2094         if (ecmd->transceiver != XCVR_EXTERNAL)
2095                 return -EINVAL;
2096         if (ecmd->phy_address != np->phyaddr) {
2097                 /* TODO: support switching between multiple phys. Should be
2098                  * trivial, but not enabled due to lack of test hardware. */
2099                 return -EINVAL;
2100         }
2101         if (ecmd->autoneg == AUTONEG_ENABLE) {
2102                 u32 mask;
2103
2104                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2105                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2106                 if (np->gigabit == PHY_GIGABIT)
2107                         mask |= ADVERTISED_1000baseT_Full;
2108
2109                 if ((ecmd->advertising & mask) == 0)
2110                         return -EINVAL;
2111
2112         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2113                 /* Note: autonegotiation disable, speed 1000 intentionally
2114                  * forbidden - noone should need that. */
2115
2116                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2117                         return -EINVAL;
2118                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2119                         return -EINVAL;
2120         } else {
2121                 return -EINVAL;
2122         }
2123
2124         spin_lock_irq(&np->lock);
2125         if (ecmd->autoneg == AUTONEG_ENABLE) {
2126                 int adv, bmcr;
2127
2128                 np->autoneg = 1;
2129
2130                 /* advertise only what has been requested */
2131                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2132                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2133                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2134                         adv |= ADVERTISE_10HALF;
2135                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2136                         adv |= ADVERTISE_10FULL;
2137                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2138                         adv |= ADVERTISE_100HALF;
2139                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2140                         adv |= ADVERTISE_100FULL;
2141                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2142
2143                 if (np->gigabit == PHY_GIGABIT) {
2144                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2145                         adv &= ~ADVERTISE_1000FULL;
2146                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2147                                 adv |= ADVERTISE_1000FULL;
2148                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2149                 }
2150
2151                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2152                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2153                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2154
2155         } else {
2156                 int adv, bmcr;
2157
2158                 np->autoneg = 0;
2159
2160                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2161                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2162                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2163                         adv |= ADVERTISE_10HALF;
2164                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2165                         adv |= ADVERTISE_10FULL;
2166                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2167                         adv |= ADVERTISE_100HALF;
2168                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2169                         adv |= ADVERTISE_100FULL;
2170                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2171                 np->fixed_mode = adv;
2172
2173                 if (np->gigabit == PHY_GIGABIT) {
2174                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2175                         adv &= ~ADVERTISE_1000FULL;
2176                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2177                 }
2178
2179                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2180                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2181                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2182                         bmcr |= BMCR_FULLDPLX;
2183                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2184                         bmcr |= BMCR_SPEED100;
2185                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2186
2187                 if (netif_running(dev)) {
2188                         /* Wait a bit and then reconfigure the nic. */
2189                         udelay(10);
2190                         nv_linkchange(dev);
2191                 }
2192         }
2193         spin_unlock_irq(&np->lock);
2194
2195         return 0;
2196 }
2197
2198 #define FORCEDETH_REGS_VER      1
2199 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
2200
2201 static int nv_get_regs_len(struct net_device *dev)
2202 {
2203         return FORCEDETH_REGS_SIZE;
2204 }
2205
2206 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2207 {
2208         struct fe_priv *np = netdev_priv(dev);
2209         u8 __iomem *base = get_hwbase(dev);
2210         u32 *rbuf = buf;
2211         int i;
2212
2213         regs->version = FORCEDETH_REGS_VER;
2214         spin_lock_irq(&np->lock);
2215         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2216                 rbuf[i] = readl(base + i*sizeof(u32));
2217         spin_unlock_irq(&np->lock);
2218 }
2219
2220 static int nv_nway_reset(struct net_device *dev)
2221 {
2222         struct fe_priv *np = netdev_priv(dev);
2223         int ret;
2224
2225         spin_lock_irq(&np->lock);
2226         if (np->autoneg) {
2227                 int bmcr;
2228
2229                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2230                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2231                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2232
2233                 ret = 0;
2234         } else {
2235                 ret = -EINVAL;
2236         }
2237         spin_unlock_irq(&np->lock);
2238
2239         return ret;
2240 }
2241
2242 static struct ethtool_ops ops = {
2243         .get_drvinfo = nv_get_drvinfo,
2244         .get_link = ethtool_op_get_link,
2245         .get_wol = nv_get_wol,
2246         .set_wol = nv_set_wol,
2247         .get_settings = nv_get_settings,
2248         .set_settings = nv_set_settings,
2249         .get_regs_len = nv_get_regs_len,
2250         .get_regs = nv_get_regs,
2251         .nway_reset = nv_nway_reset,
2252 };
2253
2254 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2255 {
2256         struct fe_priv *np = get_nvpriv(dev);
2257
2258         spin_lock_irq(&np->lock);
2259
2260         /* save vlan group */
2261         np->vlangrp = grp;
2262
2263         if (grp) {
2264                 /* enable vlan on MAC */
2265                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
2266         } else {
2267                 /* disable vlan on MAC */
2268                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
2269                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
2270         }
2271
2272         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2273
2274         spin_unlock_irq(&np->lock);
2275 };
2276
2277 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
2278 {
2279         /* nothing to do */
2280 };
2281
2282 static int nv_open(struct net_device *dev)
2283 {
2284         struct fe_priv *np = netdev_priv(dev);
2285         u8 __iomem *base = get_hwbase(dev);
2286         int ret, oom, i;
2287
2288         dprintk(KERN_DEBUG "nv_open: begin\n");
2289
2290         /* 1) erase previous misconfiguration */
2291         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2292         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2293         writel(0, base + NvRegMulticastAddrB);
2294         writel(0, base + NvRegMulticastMaskA);
2295         writel(0, base + NvRegMulticastMaskB);
2296         writel(0, base + NvRegPacketFilterFlags);
2297
2298         writel(0, base + NvRegTransmitterControl);
2299         writel(0, base + NvRegReceiverControl);
2300
2301         writel(0, base + NvRegAdapterControl);
2302
2303         /* 2) initialize descriptor rings */
2304         set_bufsize(dev);
2305         oom = nv_init_ring(dev);
2306
2307         writel(0, base + NvRegLinkSpeed);
2308         writel(0, base + NvRegUnknownTransmitterReg);
2309         nv_txrx_reset(dev);
2310         writel(0, base + NvRegUnknownSetupReg6);
2311
2312         np->in_shutdown = 0;
2313
2314         /* 3) set mac address */
2315         nv_copy_mac_to_hw(dev);
2316
2317         /* 4) give hw rings */
2318         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2319         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2320                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2321         else
2322                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2323         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2324                 base + NvRegRingSizes);
2325
2326         /* 5) continue setup */
2327         writel(np->linkspeed, base + NvRegLinkSpeed);
2328         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2329         writel(np->txrxctl_bits, base + NvRegTxRxControl);
2330         writel(np->vlanctl_bits, base + NvRegVlanControl);
2331         pci_push(base);
2332         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2333         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2334                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2335                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2336
2337         writel(0, base + NvRegUnknownSetupReg4);
2338         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2339         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2340
2341         /* 6) continue setup */
2342         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2343         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2344         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2345         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2346
2347         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2348         get_random_bytes(&i, sizeof(i));
2349         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2350         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2351         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2352         if (poll_interval == -1) {
2353                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2354                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
2355                 else
2356                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
2357         }
2358         else
2359                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
2360         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2361         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2362                         base + NvRegAdapterControl);
2363         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2364         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2365         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2366
2367         i = readl(base + NvRegPowerState);
2368         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2369                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2370
2371         pci_push(base);
2372         udelay(10);
2373         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2374
2375         writel(0, base + NvRegIrqMask);
2376         pci_push(base);
2377         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2378         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2379         pci_push(base);
2380
2381         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2382         if (ret)
2383                 goto out_drain;
2384
2385         /* ask for interrupts */
2386         writel(np->irqmask, base + NvRegIrqMask);
2387
2388         spin_lock_irq(&np->lock);
2389         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2390         writel(0, base + NvRegMulticastAddrB);
2391         writel(0, base + NvRegMulticastMaskA);
2392         writel(0, base + NvRegMulticastMaskB);
2393         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2394         /* One manual link speed update: Interrupts are enabled, future link
2395          * speed changes cause interrupts and are handled by nv_link_irq().
2396          */
2397         {
2398                 u32 miistat;
2399                 miistat = readl(base + NvRegMIIStatus);
2400                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2401                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2402         }
2403         /* set linkspeed to invalid value, thus force nv_update_linkspeed
2404          * to init hw */
2405         np->linkspeed = 0;
2406         ret = nv_update_linkspeed(dev);
2407         nv_start_rx(dev);
2408         nv_start_tx(dev);
2409         netif_start_queue(dev);
2410         if (ret) {
2411                 netif_carrier_on(dev);
2412         } else {
2413                 printk("%s: no link during initialization.\n", dev->name);
2414                 netif_carrier_off(dev);
2415         }
2416         if (oom)
2417                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2418         spin_unlock_irq(&np->lock);
2419
2420         return 0;
2421 out_drain:
2422         drain_ring(dev);
2423         return ret;
2424 }
2425
2426 static int nv_close(struct net_device *dev)
2427 {
2428         struct fe_priv *np = netdev_priv(dev);
2429         u8 __iomem *base;
2430
2431         spin_lock_irq(&np->lock);
2432         np->in_shutdown = 1;
2433         spin_unlock_irq(&np->lock);
2434         synchronize_irq();
2435
2436         del_timer_sync(&np->oom_kick);
2437         del_timer_sync(&np->nic_poll);
2438
2439         netif_stop_queue(dev);
2440         spin_lock_irq(&np->lock);
2441         nv_stop_tx(dev);
2442         nv_stop_rx(dev);
2443         nv_txrx_reset(dev);
2444
2445         /* disable interrupts on the nic or we will lock up */
2446         base = get_hwbase(dev);
2447         writel(0, base + NvRegIrqMask);
2448         pci_push(base);
2449         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2450
2451         spin_unlock_irq(&np->lock);
2452
2453         free_irq(dev->irq, dev);
2454
2455         drain_ring(dev);
2456
2457         if (np->wolenabled)
2458                 nv_start_rx(dev);
2459
2460         /* special op: write back the misordered MAC address - otherwise
2461          * the next nv_probe would see a wrong address.
2462          */
2463         writel(np->orig_mac[0], base + NvRegMacAddrA);
2464         writel(np->orig_mac[1], base + NvRegMacAddrB);
2465
2466         /* FIXME: power down nic */
2467
2468         return 0;
2469 }
2470
2471 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2472 {
2473         struct net_device *dev;
2474         struct fe_priv *np;
2475         unsigned long addr;
2476         u8 __iomem *base;
2477         int err, i;
2478
2479         dev = alloc_etherdev(sizeof(struct fe_priv));
2480         err = -ENOMEM;
2481         if (!dev)
2482                 goto out;
2483
2484         np = netdev_priv(dev);
2485         np->pci_dev = pci_dev;
2486         spin_lock_init(&np->lock);
2487         SET_MODULE_OWNER(dev);
2488         SET_NETDEV_DEV(dev, &pci_dev->dev);
2489
2490         init_timer(&np->oom_kick);
2491         np->oom_kick.data = (unsigned long) dev;
2492         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2493         init_timer(&np->nic_poll);
2494         np->nic_poll.data = (unsigned long) dev;
2495         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2496
2497         err = pci_enable_device(pci_dev);
2498         if (err) {
2499                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2500                                 err, pci_name(pci_dev));
2501                 goto out_free;
2502         }
2503
2504         pci_set_master(pci_dev);
2505
2506         err = pci_request_regions(pci_dev, DRV_NAME);
2507         if (err < 0)
2508                 goto out_disable;
2509
2510         err = -EINVAL;
2511         addr = 0;
2512         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2513                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2514                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2515                                 pci_resource_len(pci_dev, i),
2516                                 pci_resource_flags(pci_dev, i));
2517                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2518                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2519                         addr = pci_resource_start(pci_dev, i);
2520                         break;
2521                 }
2522         }
2523         if (i == DEVICE_COUNT_RESOURCE) {
2524                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2525                                         pci_name(pci_dev));
2526                 goto out_relreg;
2527         }
2528
2529         /* handle different descriptor versions */
2530         if (id->driver_data & DEV_HAS_HIGH_DMA) {
2531                 /* packet format 3: supports 40-bit addressing */
2532                 np->desc_ver = DESC_VER_3;
2533                 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2534                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2535                                         pci_name(pci_dev));
2536                 } else {
2537                         dev->features |= NETIF_F_HIGHDMA;
2538                 }
2539                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2540         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2541                 /* packet format 2: supports jumbo frames */
2542                 np->desc_ver = DESC_VER_2;
2543                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2544         } else {
2545                 /* original packet format */
2546                 np->desc_ver = DESC_VER_1;
2547                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2548         }
2549
2550         np->pkt_limit = NV_PKTLIMIT_1;
2551         if (id->driver_data & DEV_HAS_LARGEDESC)
2552                 np->pkt_limit = NV_PKTLIMIT_2;
2553
2554         if (id->driver_data & DEV_HAS_CHECKSUM) {
2555                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2556                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2557 #ifdef NETIF_F_TSO
2558                 dev->features |= NETIF_F_TSO;
2559 #endif
2560         }
2561
2562         np->vlanctl_bits = 0;
2563         if (id->driver_data & DEV_HAS_VLAN) {
2564                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
2565                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
2566                 dev->vlan_rx_register = nv_vlan_rx_register;
2567                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
2568         }
2569
2570         err = -ENOMEM;
2571         np->base = ioremap(addr, NV_PCI_REGSZ);
2572         if (!np->base)
2573                 goto out_relreg;
2574         dev->base_addr = (unsigned long)np->base;
2575
2576         dev->irq = pci_dev->irq;
2577
2578         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2579                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2580                                         sizeof(struct ring_desc) * (RX_RING + TX_RING),
2581                                         &np->ring_addr);
2582                 if (!np->rx_ring.orig)
2583                         goto out_unmap;
2584                 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2585         } else {
2586                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2587                                         sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2588                                         &np->ring_addr);
2589                 if (!np->rx_ring.ex)
2590                         goto out_unmap;
2591                 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2592         }
2593
2594         dev->open = nv_open;
2595         dev->stop = nv_close;
2596         dev->hard_start_xmit = nv_start_xmit;
2597         dev->get_stats = nv_get_stats;
2598         dev->change_mtu = nv_change_mtu;
2599         dev->set_mac_address = nv_set_mac_address;
2600         dev->set_multicast_list = nv_set_multicast;
2601 #ifdef CONFIG_NET_POLL_CONTROLLER
2602         dev->poll_controller = nv_poll_controller;
2603 #endif
2604         SET_ETHTOOL_OPS(dev, &ops);
2605         dev->tx_timeout = nv_tx_timeout;
2606         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2607
2608         pci_set_drvdata(pci_dev, dev);
2609
2610         /* read the mac address */
2611         base = get_hwbase(dev);
2612         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2613         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2614
2615         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2616         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2617         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2618         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2619         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2620         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2621
2622         if (!is_valid_ether_addr(dev->dev_addr)) {
2623                 /*
2624                  * Bad mac address. At least one bios sets the mac address
2625                  * to 01:23:45:67:89:ab
2626                  */
2627                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2628                         pci_name(pci_dev),
2629                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2630                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2631                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2632                 dev->dev_addr[0] = 0x00;
2633                 dev->dev_addr[1] = 0x00;
2634                 dev->dev_addr[2] = 0x6c;
2635                 get_random_bytes(&dev->dev_addr[3], 3);
2636         }
2637
2638         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2639                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2640                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2641
2642         /* disable WOL */
2643         writel(0, base + NvRegWakeUpFlags);
2644         np->wolenabled = 0;
2645
2646         if (np->desc_ver == DESC_VER_1) {
2647                 np->tx_flags = NV_TX_VALID;
2648         } else {
2649                 np->tx_flags = NV_TX2_VALID;
2650         }
2651         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2652                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
2653         else
2654                 np->irqmask = NVREG_IRQMASK_CPU;
2655
2656         if (id->driver_data & DEV_NEED_TIMERIRQ)
2657                 np->irqmask |= NVREG_IRQ_TIMER;
2658         if (id->driver_data & DEV_NEED_LINKTIMER) {
2659                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2660                 np->need_linktimer = 1;
2661                 np->link_timeout = jiffies + LINK_TIMEOUT;
2662         } else {
2663                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2664                 np->need_linktimer = 0;
2665         }
2666
2667         /* find a suitable phy */
2668         for (i = 1; i <= 32; i++) {
2669                 int id1, id2;
2670                 int phyaddr = i & 0x1F;
2671
2672                 spin_lock_irq(&np->lock);
2673                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
2674                 spin_unlock_irq(&np->lock);
2675                 if (id1 < 0 || id1 == 0xffff)
2676                         continue;
2677                 spin_lock_irq(&np->lock);
2678                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
2679                 spin_unlock_irq(&np->lock);
2680                 if (id2 < 0 || id2 == 0xffff)
2681                         continue;
2682
2683                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2684                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2685                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2686                         pci_name(pci_dev), id1, id2, phyaddr);
2687                 np->phyaddr = phyaddr;
2688                 np->phy_oui = id1 | id2;
2689                 break;
2690         }
2691         if (i == 33) {
2692                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2693                        pci_name(pci_dev));
2694                 goto out_freering;
2695         }
2696
2697         /* reset it */
2698         phy_init(dev);
2699
2700         /* set default link speed settings */
2701         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2702         np->duplex = 0;
2703         np->autoneg = 1;
2704
2705         err = register_netdev(dev);
2706         if (err) {
2707                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2708                 goto out_freering;
2709         }
2710         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2711                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2712                         pci_name(pci_dev));
2713
2714         return 0;
2715
2716 out_freering:
2717         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2718                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2719                                     np->rx_ring.orig, np->ring_addr);
2720         else
2721                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2722                                     np->rx_ring.ex, np->ring_addr);
2723         pci_set_drvdata(pci_dev, NULL);
2724 out_unmap:
2725         iounmap(get_hwbase(dev));
2726 out_relreg:
2727         pci_release_regions(pci_dev);
2728 out_disable:
2729         pci_disable_device(pci_dev);
2730 out_free:
2731         free_netdev(dev);
2732 out:
2733         return err;
2734 }
2735
2736 static void __devexit nv_remove(struct pci_dev *pci_dev)
2737 {
2738         struct net_device *dev = pci_get_drvdata(pci_dev);
2739         struct fe_priv *np = netdev_priv(dev);
2740
2741         unregister_netdev(dev);
2742
2743         /* free all structures */
2744         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2745                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2746         else
2747                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2748         iounmap(get_hwbase(dev));
2749         pci_release_regions(pci_dev);
2750         pci_disable_device(pci_dev);
2751         free_netdev(dev);
2752         pci_set_drvdata(pci_dev, NULL);
2753 }
2754
2755 static struct pci_device_id pci_tbl[] = {
2756         {       /* nForce Ethernet Controller */
2757                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2758                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2759         },
2760         {       /* nForce2 Ethernet Controller */
2761                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2762                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2763         },
2764         {       /* nForce3 Ethernet Controller */
2765                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2766                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2767         },
2768         {       /* nForce3 Ethernet Controller */
2769                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2770                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2771         },
2772         {       /* nForce3 Ethernet Controller */
2773                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2774                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2775         },
2776         {       /* nForce3 Ethernet Controller */
2777                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2778                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2779         },
2780         {       /* nForce3 Ethernet Controller */
2781                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2782                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2783         },
2784         {       /* CK804 Ethernet Controller */
2785                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2786                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2787         },
2788         {       /* CK804 Ethernet Controller */
2789                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2790                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2791         },
2792         {       /* MCP04 Ethernet Controller */
2793                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2794                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2795         },
2796         {       /* MCP04 Ethernet Controller */
2797                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2798                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2799         },
2800         {       /* MCP51 Ethernet Controller */
2801                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2802                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2803         },
2804         {       /* MCP51 Ethernet Controller */
2805                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2806                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2807         },
2808         {       /* MCP55 Ethernet Controller */
2809                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2810                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN,
2811         },
2812         {       /* MCP55 Ethernet Controller */
2813                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2814                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN,
2815         },
2816         {0,},
2817 };
2818
2819 static struct pci_driver driver = {
2820         .name = "forcedeth",
2821         .id_table = pci_tbl,
2822         .probe = nv_probe,
2823         .remove = __devexit_p(nv_remove),
2824 };
2825
2826
2827 static int __init init_nic(void)
2828 {
2829         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2830         return pci_module_init(&driver);
2831 }
2832
2833 static void __exit exit_nic(void)
2834 {
2835         pci_unregister_driver(&driver);
2836 }
2837
2838 module_param(max_interrupt_work, int, 0);
2839 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2840 module_param(optimization_mode, int, 0);
2841 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
2842 module_param(poll_interval, int, 0);
2843 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
2844
2845 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2846 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2847 MODULE_LICENSE("GPL");
2848
2849 MODULE_DEVICE_TABLE(pci, pci_tbl);
2850
2851 module_init(init_nic);
2852 module_exit(exit_nic);