drivers/net/sb1250-mac.c

   1 /*
   2  * Copyright (C) 2001,2002,2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 /*
  20   This driver is designed for the Broadcom SiByte SOC built-in
  21   Ethernet controllers.
  22
  23   Written by Mitch Lichtenberg at Broadcom Corp.
  24 */
  25
  26
  27
  28 #define CONFIG_SBMAC_COALESCE
  29
  30 /* A few user-configurable values.
  31    These may be modified when a driver module is loaded. */
  32
  33 static int debug = 1;                   /* 1 normal messages, 0 quiet .. 7 verbose. */
  34 static int noisy_mii = 1;               /* mii status msgs */
  35
  36 /* Used to pass the media type, etc.
  37    Both 'options[]' and 'full_duplex[]' should exist for driver
  38    interoperability.
  39    The media type is usually passed in 'options[]'.
  40 */
  41
  42 #define MAX_UNITS 3             /* More are supported, limit only on options */
  43 #ifdef MODULE
  44 static int options[MAX_UNITS] = {-1, -1, -1};
  45 static int full_duplex[MAX_UNITS] = {-1, -1, -1};
  46 #endif
  47
  48 #ifdef CONFIG_SBMAC_COALESCE
  49 static int int_pktcnt = 0;
  50 static int int_timeout = 0;
  51 #endif
  52
  53 /* Operational parameters that usually are not changed. */
  54
  55 /* Time in jiffies before concluding the transmitter is hung. */
  56 #define TX_TIMEOUT  (2*HZ)
  57
  58 #if !defined(__OPTIMIZE__)  ||  !defined(__KERNEL__)
  59 #warning  You must compile this file with the correct options!
  60 #warning  See the last lines of the source file.
  61 #error  You must compile this driver with "-O".
  62 #endif
  63
  64 #include <linux/module.h>
  65 #include <linux/kernel.h>
  66 #include <linux/string.h>
  67 #include <linux/timer.h>
  68 #include <linux/errno.h>
  69 #include <linux/ioport.h>
  70 #include <linux/slab.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/netdevice.h>
  73 #include <linux/etherdevice.h>
  74 #include <linux/skbuff.h>
  75 #include <linux/init.h>
  76 #include <linux/config.h>
  77 #include <asm/processor.h>              /* Processor type for cache alignment. */
  78 #include <asm/bitops.h>
  79 #include <asm/io.h>
  80 #include <asm/cache.h>
  81
  82 /* This is only here until the firmware is ready.  In that case,
  83    the firmware leaves the ethernet address in the register for us. */
  84 #ifdef CONFIG_SIBYTE_STANDALONE
  85 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
  86 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
  87 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
  88 #endif
  89
  90
  91 /* These identify the driver base version and may not be removed. */
  92 #if 0
  93 static char version1[] __devinitdata =
  94 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
  95 #endif
  96
  97
  98
  99 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
 100 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
 101 MODULE_LICENSE("GPL");
 102 MODULE_PARM(debug, "i");
 103 MODULE_PARM(noisy_mii, "i");
 104 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
 105 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
 106
 107 MODULE_PARM(int_pktcnt, "i");
 108 MODULE_PARM(int_timeout, "i");
 109
 110 #include <asm/sibyte/sb1250.h>
 111 #include <asm/sibyte/sb1250_defs.h>
 112 #include <asm/sibyte/sb1250_regs.h>
 113 #include <asm/sibyte/sb1250_mac.h>
 114 #include <asm/sibyte/sb1250_dma.h>
 115 #include <asm/sibyte/sb1250_int.h>
 116 #include <asm/sibyte/sb1250_scd.h>
 117 #include <asm/sibyte/64bit.h>
 118
 119
 120 /**********************************************************************
 121  *  Simple types
 122  ********************************************************************* */
 123
 124
 125 typedef unsigned long sbmac_port_t;
 126
 127 typedef enum { sbmac_speed_auto, sbmac_speed_10,
 128                sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
 129
 130 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
 131                sbmac_duplex_full } sbmac_duplex_t;
 132
 133 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
 134                sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
 135
 136 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
 137                sbmac_state_broken } sbmac_state_t;
 138
 139
 140 /**********************************************************************
 141  *  Macros
 142  ********************************************************************* */
 143
 144
 145 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
 146                           (d)->sbdma_dscrtable : (d)->f+1)
 147
 148
 149 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
 150
 151 #define SBMAC_READCSR(t)        in64((unsigned long)t)
 152 #define SBMAC_WRITECSR(t,v)     out64(v, (unsigned long)t)
 153
 154
 155 #define SBMAC_MAX_TXDESCR       32
 156 #define SBMAC_MAX_RXDESCR       32
 157
 158 #define ETHER_ALIGN     2
 159 #define ETHER_ADDR_LEN  6
 160 #define ENET_PACKET_SIZE        1518
 161 /*#define ENET_PACKET_SIZE      9216 */
 162
 163 /**********************************************************************
 164  *  DMA Descriptor structure
 165  ********************************************************************* */
 166
 167 typedef struct sbdmadscr_s {
 168         uint64_t  dscr_a;
 169         uint64_t  dscr_b;
 170 } sbdmadscr_t;
 171
 172 typedef unsigned long paddr_t;
 173
 174 /**********************************************************************
 175  *  DMA Controller structure
 176  ********************************************************************* */
 177
 178 typedef struct sbmacdma_s {
 179
 180         /*
 181          * This stuff is used to identify the channel and the registers
 182          * associated with it.
 183          */
 184
 185         struct sbmac_softc *sbdma_eth;          /* back pointer to associated MAC */
 186         int              sbdma_channel; /* channel number */
 187         int              sbdma_txdir;       /* direction (1=transmit) */
 188         int              sbdma_maxdescr;        /* total # of descriptors in ring */
 189 #ifdef CONFIG_SBMAC_COALESCE
 190         int              sbdma_int_pktcnt;  /* # descriptors rx/tx before interrupt*/
 191         int              sbdma_int_timeout; /* # usec rx/tx interrupt */
 192 #endif
 193
 194         sbmac_port_t     sbdma_config0; /* DMA config register 0 */
 195         sbmac_port_t     sbdma_config1; /* DMA config register 1 */
 196         sbmac_port_t     sbdma_dscrbase;        /* Descriptor base address */
 197         sbmac_port_t     sbdma_dscrcnt;     /* Descriptor count register */
 198         sbmac_port_t     sbdma_curdscr; /* current descriptor address */
 199
 200         /*
 201          * This stuff is for maintenance of the ring
 202          */
 203
 204         sbdmadscr_t     *sbdma_dscrtable;       /* base of descriptor table */
 205         sbdmadscr_t     *sbdma_dscrtable_end; /* end of descriptor table */
 206
 207         struct sk_buff **sbdma_ctxtable;    /* context table, one per descr */
 208
 209         paddr_t          sbdma_dscrtable_phys; /* and also the phys addr */
 210         sbdmadscr_t     *sbdma_addptr;  /* next dscr for sw to add */
 211         sbdmadscr_t     *sbdma_remptr;  /* next dscr for sw to remove */
 212 } sbmacdma_t;
 213
 214
 215 /**********************************************************************
 216  *  Ethernet softc structure
 217  ********************************************************************* */
 218
 219 struct sbmac_softc {
 220
 221         /*
 222          * Linux-specific things
 223          */
 224
 225         struct net_device *sbm_dev;             /* pointer to linux device */
 226         spinlock_t sbm_lock;            /* spin lock */
 227         struct timer_list sbm_timer;            /* for monitoring MII */
 228         struct net_device_stats sbm_stats;
 229         int sbm_devflags;                       /* current device flags */
 230
 231         int          sbm_phy_oldbmsr;
 232         int          sbm_phy_oldanlpar;
 233         int          sbm_phy_oldk1stsr;
 234         int          sbm_phy_oldlinkstat;
 235         int sbm_buffersize;
 236
 237         unsigned char sbm_phys[2];
 238
 239         /*
 240          * Controller-specific things
 241          */
 242
 243         unsigned long   sbm_base;          /* MAC's base address */
 244         sbmac_state_t    sbm_state;         /* current state */
 245
 246         sbmac_port_t     sbm_macenable; /* MAC Enable Register */
 247         sbmac_port_t     sbm_maccfg;    /* MAC Configuration Register */
 248         sbmac_port_t     sbm_fifocfg;   /* FIFO configuration register */
 249         sbmac_port_t     sbm_framecfg;  /* Frame configuration register */
 250         sbmac_port_t     sbm_rxfilter;  /* receive filter register */
 251         sbmac_port_t     sbm_isr;               /* Interrupt status register */
 252         sbmac_port_t     sbm_imr;               /* Interrupt mask register */
 253         sbmac_port_t     sbm_mdio;              /* MDIO register */
 254
 255         sbmac_speed_t    sbm_speed;             /* current speed */
 256         sbmac_duplex_t   sbm_duplex;    /* current duplex */
 257         sbmac_fc_t       sbm_fc;                /* current flow control setting */
 258
 259         unsigned char    sbm_hwaddr[ETHER_ADDR_LEN];
 260
 261         sbmacdma_t       sbm_txdma;             /* for now, only use channel 0 */
 262         sbmacdma_t       sbm_rxdma;
 263         int              rx_hw_checksum;
 264         int              sbe_idx;
 265 };
 266
 267
 268 /**********************************************************************
 269  *  Externs
 270  ********************************************************************* */
 271
 272 /**********************************************************************
 273  *  Prototypes
 274  ********************************************************************* */
 275
 276 static void sbdma_initctx(sbmacdma_t *d,
 277                           struct sbmac_softc *s,
 278                           int chan,
 279                           int txrx,
 280                           int maxdescr);
 281 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
 282 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
 283 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
 284 static void sbdma_emptyring(sbmacdma_t *d);
 285 static void sbdma_fillring(sbmacdma_t *d);
 286 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 287 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 288 static int sbmac_initctx(struct sbmac_softc *s);
 289 static void sbmac_channel_start(struct sbmac_softc *s);
 290 static void sbmac_channel_stop(struct sbmac_softc *s);
 291 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
 292 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
 293 static uint64_t sbmac_addr2reg(unsigned char *ptr);
 294 static void sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
 295 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
 296 static void sbmac_setmulti(struct sbmac_softc *sc);
 297 static int sbmac_init(struct net_device *dev, int idx);
 298 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
 299 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
 300
 301 static int sbmac_open(struct net_device *dev);
 302 static void sbmac_timer(unsigned long data);
 303 static void sbmac_tx_timeout (struct net_device *dev);
 304 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
 305 static void sbmac_set_rx_mode(struct net_device *dev);
 306 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 307 static int sbmac_close(struct net_device *dev);
 308 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
 309
 310 static void sbmac_mii_sync(struct sbmac_softc *s);
 311 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
 312 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
 313 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 314                             unsigned int regval);
 315
 316
 317 /**********************************************************************
 318  *  Globals
 319  ********************************************************************* */
 320
 321 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
 322
 323
 324 /**********************************************************************
 325  *  MDIO constants
 326  ********************************************************************* */
 327
 328 #define MII_COMMAND_START       0x01
 329 #define MII_COMMAND_READ        0x02
 330 #define MII_COMMAND_WRITE       0x01
 331 #define MII_COMMAND_ACK         0x02
 332
 333 #define BMCR_RESET     0x8000
 334 #define BMCR_LOOPBACK  0x4000
 335 #define BMCR_SPEED0    0x2000
 336 #define BMCR_ANENABLE  0x1000
 337 #define BMCR_POWERDOWN 0x0800
 338 #define BMCR_ISOLATE   0x0400
 339 #define BMCR_RESTARTAN 0x0200
 340 #define BMCR_DUPLEX    0x0100
 341 #define BMCR_COLTEST   0x0080
 342 #define BMCR_SPEED1    0x0040
 343 #define BMCR_SPEED1000  BMCR_SPEED1
 344 #define BMCR_SPEED100   BMCR_SPEED0
 345 #define BMCR_SPEED10    0
 346
 347 #define BMSR_100BT4     0x8000
 348 #define BMSR_100BT_FDX  0x4000
 349 #define BMSR_100BT_HDX  0x2000
 350 #define BMSR_10BT_FDX   0x1000
 351 #define BMSR_10BT_HDX   0x0800
 352 #define BMSR_100BT2_FDX 0x0400
 353 #define BMSR_100BT2_HDX 0x0200
 354 #define BMSR_1000BT_XSR 0x0100
 355 #define BMSR_PRESUP     0x0040
 356 #define BMSR_ANCOMPLT   0x0020
 357 #define BMSR_REMFAULT   0x0010
 358 #define BMSR_AUTONEG    0x0008
 359 #define BMSR_LINKSTAT   0x0004
 360 #define BMSR_JABDETECT  0x0002
 361 #define BMSR_EXTCAPAB   0x0001
 362
 363 #define PHYIDR1         0x2000
 364 #define PHYIDR2         0x5C60
 365
 366 #define ANAR_NP         0x8000
 367 #define ANAR_RF         0x2000
 368 #define ANAR_ASYPAUSE   0x0800
 369 #define ANAR_PAUSE      0x0400
 370 #define ANAR_T4         0x0200
 371 #define ANAR_TXFD       0x0100
 372 #define ANAR_TXHD       0x0080
 373 #define ANAR_10FD       0x0040
 374 #define ANAR_10HD       0x0020
 375 #define ANAR_PSB        0x0001
 376
 377 #define ANLPAR_NP       0x8000
 378 #define ANLPAR_ACK      0x4000
 379 #define ANLPAR_RF       0x2000
 380 #define ANLPAR_ASYPAUSE 0x0800
 381 #define ANLPAR_PAUSE    0x0400
 382 #define ANLPAR_T4       0x0200
 383 #define ANLPAR_TXFD     0x0100
 384 #define ANLPAR_TXHD     0x0080
 385 #define ANLPAR_10FD     0x0040
 386 #define ANLPAR_10HD     0x0020
 387 #define ANLPAR_PSB      0x0001  /* 802.3 */
 388
 389 #define ANER_PDF        0x0010
 390 #define ANER_LPNPABLE   0x0008
 391 #define ANER_NPABLE     0x0004
 392 #define ANER_PAGERX     0x0002
 393 #define ANER_LPANABLE   0x0001
 394
 395 #define ANNPTR_NP       0x8000
 396 #define ANNPTR_MP       0x2000
 397 #define ANNPTR_ACK2     0x1000
 398 #define ANNPTR_TOGTX    0x0800
 399 #define ANNPTR_CODE     0x0008
 400
 401 #define ANNPRR_NP       0x8000
 402 #define ANNPRR_MP       0x2000
 403 #define ANNPRR_ACK3     0x1000
 404 #define ANNPRR_TOGTX    0x0800
 405 #define ANNPRR_CODE     0x0008
 406
 407 #define K1TCR_TESTMODE  0x0000
 408 #define K1TCR_MSMCE     0x1000
 409 #define K1TCR_MSCV      0x0800
 410 #define K1TCR_RPTR      0x0400
 411 #define K1TCR_1000BT_FDX 0x200
 412 #define K1TCR_1000BT_HDX 0x100
 413
 414 #define K1STSR_MSMCFLT  0x8000
 415 #define K1STSR_MSCFGRES 0x4000
 416 #define K1STSR_LRSTAT   0x2000
 417 #define K1STSR_RRSTAT   0x1000
 418 #define K1STSR_LP1KFD   0x0800
 419 #define K1STSR_LP1KHD   0x0400
 420 #define K1STSR_LPASMDIR 0x0200
 421
 422 #define K1SCR_1KX_FDX   0x8000
 423 #define K1SCR_1KX_HDX   0x4000
 424 #define K1SCR_1KT_FDX   0x2000
 425 #define K1SCR_1KT_HDX   0x1000
 426
 427 #define STRAP_PHY1      0x0800
 428 #define STRAP_NCMODE    0x0400
 429 #define STRAP_MANMSCFG  0x0200
 430 #define STRAP_ANENABLE  0x0100
 431 #define STRAP_MSVAL     0x0080
 432 #define STRAP_1KHDXADV  0x0010
 433 #define STRAP_1KFDXADV  0x0008
 434 #define STRAP_100ADV    0x0004
 435 #define STRAP_SPEEDSEL  0x0000
 436 #define STRAP_SPEED100  0x0001
 437
 438 #define PHYSUP_SPEED1000 0x10
 439 #define PHYSUP_SPEED100  0x08
 440 #define PHYSUP_SPEED10   0x00
 441 #define PHYSUP_LINKUP    0x04
 442 #define PHYSUP_FDX       0x02
 443
 444 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
 445 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
 446 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
 447 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
 448
 449
 450 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
 451
 452 #define ENABLE          1
 453 #define DISABLE         0
 454
 455 /**********************************************************************
 456  *  SBMAC_MII_SYNC(s)
 457  *
 458  *  Synchronize with the MII - send a pattern of bits to the MII
 459  *  that will guarantee that it is ready to accept a command.
 460  *
 461  *  Input parameters:
 462  *         s - sbmac structure
 463  *
 464  *  Return value:
 465  *         nothing
 466  ********************************************************************* */
 467
 468 static void sbmac_mii_sync(struct sbmac_softc *s)
 469 {
 470         int cnt;
 471         uint64_t bits;
 472         int mac_mdio_genc;
 473
 474         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 475
 476         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
 477
 478         SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 479
 480         for (cnt = 0; cnt < 32; cnt++) {
 481                 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
 482                 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 483         }
 484 }
 485
 486 /**********************************************************************
 487  *  SBMAC_MII_SENDDATA(s,data,bitcnt)
 488  *
 489  *  Send some bits to the MII.  The bits to be sent are right-
 490  *  justified in the 'data' parameter.
 491  *
 492  *  Input parameters:
 493  *         s - sbmac structure
 494  *         data - data to send
 495  *         bitcnt - number of bits to send
 496  ********************************************************************* */
 497
 498 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
 499 {
 500         int i;
 501         uint64_t bits;
 502         unsigned int curmask;
 503         int mac_mdio_genc;
 504
 505         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 506
 507         bits = M_MAC_MDIO_DIR_OUTPUT;
 508         SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 509
 510         curmask = 1 << (bitcnt - 1);
 511
 512         for (i = 0; i < bitcnt; i++) {
 513                 if (data & curmask)
 514                         bits |= M_MAC_MDIO_OUT;
 515                 else bits &= ~M_MAC_MDIO_OUT;
 516                 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 517                 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
 518                 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 519                 curmask >>= 1;
 520         }
 521 }
 522
 523
 524
 525 /**********************************************************************
 526  *  SBMAC_MII_READ(s,phyaddr,regidx)
 527  *
 528  *  Read a PHY register.
 529  *
 530  *  Input parameters:
 531  *         s - sbmac structure
 532  *         phyaddr - PHY's address
 533  *         regidx = index of register to read
 534  *
 535  *  Return value:
 536  *         value read, or 0 if an error occurred.
 537  ********************************************************************* */
 538
 539 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
 540 {
 541         int idx;
 542         int error;
 543         int regval;
 544         int mac_mdio_genc;
 545
 546         /*
 547          * Synchronize ourselves so that the PHY knows the next
 548          * thing coming down is a command
 549          */
 550
 551         sbmac_mii_sync(s);
 552
 553         /*
 554          * Send the data to the PHY.  The sequence is
 555          * a "start" command (2 bits)
 556          * a "read" command (2 bits)
 557          * the PHY addr (5 bits)
 558          * the register index (5 bits)
 559          */
 560
 561         sbmac_mii_senddata(s,MII_COMMAND_START, 2);
 562         sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
 563         sbmac_mii_senddata(s,phyaddr, 5);
 564         sbmac_mii_senddata(s,regidx, 5);
 565
 566         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 567
 568         /*
 569          * Switch the port around without a clock transition.
 570          */
 571         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 572
 573         /*
 574          * Send out a clock pulse to signal we want the status
 575          */
 576
 577         SBMAC_WRITECSR(s->sbm_mdio,
 578                        M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
 579         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 580
 581         /*
 582          * If an error occurred, the PHY will signal '1' back
 583          */
 584         error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN;
 585
 586         /*
 587          * Issue an 'idle' clock pulse, but keep the direction
 588          * the same.
 589          */
 590         SBMAC_WRITECSR(s->sbm_mdio,
 591                        M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
 592         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 593
 594         regval = 0;
 595
 596         for (idx = 0; idx < 16; idx++) {
 597                 regval <<= 1;
 598
 599                 if (error == 0) {
 600                         if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN)
 601                                 regval |= 1;
 602                 }
 603
 604                 SBMAC_WRITECSR(s->sbm_mdio,
 605                                M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc);
 606                 SBMAC_WRITECSR(s->sbm_mdio,
 607                                M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 608         }
 609
 610         /* Switch back to output */
 611         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
 612
 613         if (error == 0)
 614                 return regval;
 615         return 0;
 616 }
 617
 618
 619 /**********************************************************************
 620  *  SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
 621  *
 622  *  Write a value to a PHY register.
 623  *
 624  *  Input parameters:
 625  *         s - sbmac structure
 626  *         phyaddr - PHY to use
 627  *         regidx - register within the PHY
 628  *         regval - data to write to register
 629  *
 630  *  Return value:
 631  *         nothing
 632  ********************************************************************* */
 633
 634 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 635                             unsigned int regval)
 636 {
 637         int mac_mdio_genc;
 638
 639         sbmac_mii_sync(s);
 640
 641         sbmac_mii_senddata(s,MII_COMMAND_START,2);
 642         sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
 643         sbmac_mii_senddata(s,phyaddr, 5);
 644         sbmac_mii_senddata(s,regidx, 5);
 645         sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
 646         sbmac_mii_senddata(s,regval,16);
 647
 648         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 649
 650         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
 651 }
 652
 653
 654
 655 /**********************************************************************
 656  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
 657  *
 658  *  Initialize a DMA channel context.  Since there are potentially
 659  *  eight DMA channels per MAC, it's nice to do this in a standard
 660  *  way.
 661  *
 662  *  Input parameters:
 663  *         d - sbmacdma_t structure (DMA channel context)
 664  *         s - sbmac_softc structure (pointer to a MAC)
 665  *         chan - channel number (0..1 right now)
 666  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
 667  *      maxdescr - number of descriptors
 668  *
 669  *  Return value:
 670  *         nothing
 671  ********************************************************************* */
 672
 673 static void sbdma_initctx(sbmacdma_t *d,
 674                           struct sbmac_softc *s,
 675                           int chan,
 676                           int txrx,
 677                           int maxdescr)
 678 {
 679         /*
 680          * Save away interesting stuff in the structure
 681          */
 682
 683         d->sbdma_eth       = s;
 684         d->sbdma_channel   = chan;
 685         d->sbdma_txdir     = txrx;
 686
 687 #if 0
 688         /* RMON clearing */
 689         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
 690 #endif
 691
 692         SBMAC_WRITECSR(KSEG1ADDR(
 693         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
 694         SBMAC_WRITECSR(KSEG1ADDR(
 695         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
 696         SBMAC_WRITECSR(KSEG1ADDR(
 697         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
 698         SBMAC_WRITECSR(KSEG1ADDR(
 699         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
 700         SBMAC_WRITECSR(KSEG1ADDR(
 701         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
 702         SBMAC_WRITECSR(KSEG1ADDR(
 703         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
 704         SBMAC_WRITECSR(KSEG1ADDR(
 705         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
 706         SBMAC_WRITECSR(KSEG1ADDR(
 707         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
 708         SBMAC_WRITECSR(KSEG1ADDR(
 709         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
 710         SBMAC_WRITECSR(KSEG1ADDR(
 711         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
 712         SBMAC_WRITECSR(KSEG1ADDR(
 713         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
 714         SBMAC_WRITECSR(KSEG1ADDR(
 715         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
 716         SBMAC_WRITECSR(KSEG1ADDR(
 717         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
 718         SBMAC_WRITECSR(KSEG1ADDR(
 719         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
 720         SBMAC_WRITECSR(KSEG1ADDR(
 721         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
 722         SBMAC_WRITECSR(KSEG1ADDR(
 723         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
 724         SBMAC_WRITECSR(KSEG1ADDR(
 725         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
 726         SBMAC_WRITECSR(KSEG1ADDR(
 727         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
 728         SBMAC_WRITECSR(KSEG1ADDR(
 729         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
 730         SBMAC_WRITECSR(KSEG1ADDR(
 731         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
 732         SBMAC_WRITECSR(KSEG1ADDR(
 733         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
 734
 735         /*
 736          * initialize register pointers
 737          */
 738
 739         d->sbdma_config0 =
 740                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
 741         d->sbdma_config1 =
 742                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
 743         d->sbdma_dscrbase =
 744                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
 745         d->sbdma_dscrcnt =
 746                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
 747         d->sbdma_curdscr =
 748                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
 749
 750         /*
 751          * Allocate memory for the ring
 752          */
 753
 754         d->sbdma_maxdescr = maxdescr;
 755
 756         d->sbdma_dscrtable = (sbdmadscr_t *)
 757                 kmalloc(d->sbdma_maxdescr*sizeof(sbdmadscr_t), GFP_KERNEL);
 758
 759         memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
 760
 761         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
 762
 763         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
 764
 765         /*
 766          * And context table
 767          */
 768
 769         d->sbdma_ctxtable = (struct sk_buff **)
 770                 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
 771
 772         memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
 773
 774 #ifdef CONFIG_SBMAC_COALESCE
 775         /*
 776          * Setup Rx/Tx DMA coalescing defaults
 777          */
 778
 779         if ( int_pktcnt ) {
 780                 d->sbdma_int_pktcnt = int_pktcnt;
 781         } else {
 782                 d->sbdma_int_pktcnt = 1;
 783         }
 784
 785         if ( int_timeout ) {
 786                 d->sbdma_int_timeout = int_timeout;
 787         } else {
 788                 d->sbdma_int_timeout = 0;
 789         }
 790 #endif
 791
 792 }
 793
 794 /**********************************************************************
 795  *  SBDMA_CHANNEL_START(d)
 796  *
 797  *  Initialize the hardware registers for a DMA channel.
 798  *
 799  *  Input parameters:
 800  *         d - DMA channel to init (context must be previously init'd
 801  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
 802  *
 803  *  Return value:
 804  *         nothing
 805  ********************************************************************* */
 806
 807 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
 808 {
 809         /*
 810          * Turn on the DMA channel
 811          */
 812
 813 #ifdef CONFIG_SBMAC_COALESCE
 814         SBMAC_WRITECSR(d->sbdma_config1,
 815                        V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
 816                        0);
 817         SBMAC_WRITECSR(d->sbdma_config0,
 818                        M_DMA_EOP_INT_EN |
 819                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 820                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
 821                        0);
 822 #else
 823         SBMAC_WRITECSR(d->sbdma_config1,0);
 824         SBMAC_WRITECSR(d->sbdma_config0,
 825                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 826                        0);
 827 #endif
 828
 829         SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
 830
 831         /*
 832          * Initialize ring pointers
 833          */
 834
 835         d->sbdma_addptr = d->sbdma_dscrtable;
 836         d->sbdma_remptr = d->sbdma_dscrtable;
 837 }
 838
 839 /**********************************************************************
 840  *  SBDMA_CHANNEL_STOP(d)
 841  *
 842  *  Initialize the hardware registers for a DMA channel.
 843  *
 844  *  Input parameters:
 845  *         d - DMA channel to init (context must be previously init'd
 846  *
 847  *  Return value:
 848  *         nothing
 849  ********************************************************************* */
 850
 851 static void sbdma_channel_stop(sbmacdma_t *d)
 852 {
 853         /*
 854          * Turn off the DMA channel
 855          */
 856
 857         SBMAC_WRITECSR(d->sbdma_config1,0);
 858
 859         SBMAC_WRITECSR(d->sbdma_dscrbase,0);
 860
 861         SBMAC_WRITECSR(d->sbdma_config0,0);
 862
 863         /*
 864          * Zero ring pointers
 865          */
 866
 867         d->sbdma_addptr = 0;
 868         d->sbdma_remptr = 0;
 869 }
 870
 871 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
 872 {
 873         unsigned long addr;
 874         unsigned long newaddr;
 875
 876         addr = (unsigned long) skb->data;
 877
 878         newaddr = (addr + power2 - 1) & ~(power2 - 1);
 879
 880         skb_reserve(skb,newaddr-addr+offset);
 881 }
 882
 883
 884 /**********************************************************************
 885  *  SBDMA_ADD_RCVBUFFER(d,sb)
 886  *
 887  *  Add a buffer to the specified DMA channel.   For receive channels,
 888  *  this queues a buffer for inbound packets.
 889  *
 890  *  Input parameters:
 891  *         d - DMA channel descriptor
 892  *         sb - sk_buff to add, or NULL if we should allocate one
 893  *
 894  *  Return value:
 895  *         0 if buffer could not be added (ring is full)
 896  *         1 if buffer added successfully
 897  ********************************************************************* */
 898
 899
 900 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
 901 {
 902         sbdmadscr_t *dsc;
 903         sbdmadscr_t *nextdsc;
 904         struct sk_buff *sb_new = NULL;
 905         int pktsize = ENET_PACKET_SIZE;
 906
 907         /* get pointer to our current place in the ring */
 908
 909         dsc = d->sbdma_addptr;
 910         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 911
 912         /*
 913          * figure out if the ring is full - if the next descriptor
 914          * is the same as the one that we're going to remove from
 915          * the ring, the ring is full
 916          */
 917
 918         if (nextdsc == d->sbdma_remptr) {
 919                 return -ENOSPC;
 920         }
 921
 922         /*
 923          * Allocate a sk_buff if we don't already have one.
 924          * If we do have an sk_buff, reset it so that it's empty.
 925          *
 926          * Note: sk_buffs don't seem to be guaranteed to have any sort
 927          * of alignment when they are allocated.  Therefore, allocate enough
 928          * extra space to make sure that:
 929          *
 930          *    1. the data does not start in the middle of a cache line.
 931          *    2. The data does not end in the middle of a cache line
 932          *    3. The buffer can be aligned such that the IP addresses are
 933          *       naturally aligned.
 934          *
 935          *  Remember, the SOCs MAC writes whole cache lines at a time,
 936          *  without reading the old contents first.  So, if the sk_buff's
 937          *  data portion starts in the middle of a cache line, the SOC
 938          *  DMA will trash the beginning (and ending) portions.
 939          */
 940
 941         if (sb == NULL) {
 942                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
 943                 if (sb_new == NULL) {
 944                         printk(KERN_INFO "%s: sk_buff allocation failed\n",
 945                                d->sbdma_eth->sbm_dev->name);
 946                         return -ENOBUFS;
 947                 }
 948
 949                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
 950
 951                 /* mark skbuff owned by our device */
 952                 sb_new->dev = d->sbdma_eth->sbm_dev;
 953         }
 954         else {
 955                 sb_new = sb;
 956                 /*
 957                  * nothing special to reinit buffer, it's already aligned
 958                  * and sb->data already points to a good place.
 959                  */
 960         }
 961
 962         /*
 963          * fill in the descriptor
 964          */
 965
 966 #ifdef CONFIG_SBMAC_COALESCE
 967         /*
 968          * Do not interrupt per DMA transfer.
 969          */
 970         dsc->dscr_a = virt_to_phys(sb_new->tail) |
 971                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 972                 0;
 973 #else
 974         dsc->dscr_a = virt_to_phys(sb_new->tail) |
 975                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 976                 M_DMA_DSCRA_INTERRUPT;
 977 #endif
 978
 979         /* receiving: no options */
 980         dsc->dscr_b = 0;
 981
 982         /*
 983          * fill in the context
 984          */
 985
 986         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
 987
 988         /*
 989          * point at next packet
 990          */
 991
 992         d->sbdma_addptr = nextdsc;
 993
 994         /*
 995          * Give the buffer to the DMA engine.
 996          */
 997
 998         SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
 999
1000         return 0;                                       /* we did it */
1001 }
1002
1003 /**********************************************************************
1004  *  SBDMA_ADD_TXBUFFER(d,sb)
1005  *
1006  *  Add a transmit buffer to the specified DMA channel, causing a
1007  *  transmit to start.
1008  *
1009  *  Input parameters:
1010  *         d - DMA channel descriptor
1011  *         sb - sk_buff to add
1012  *
1013  *  Return value:
1014  *         0 transmit queued successfully
1015  *         otherwise error code
1016  ********************************************************************* */
1017
1018
1019 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1020 {
1021         sbdmadscr_t *dsc;
1022         sbdmadscr_t *nextdsc;
1023         uint64_t phys;
1024         uint64_t ncb;
1025         int length;
1026
1027         /* get pointer to our current place in the ring */
1028
1029         dsc = d->sbdma_addptr;
1030         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1031
1032         /*
1033          * figure out if the ring is full - if the next descriptor
1034          * is the same as the one that we're going to remove from
1035          * the ring, the ring is full
1036          */
1037
1038         if (nextdsc == d->sbdma_remptr) {
1039                 return -ENOSPC;
1040         }
1041
1042         /*
1043          * Under Linux, it's not necessary to copy/coalesce buffers
1044          * like it is on NetBSD.  We think they're all contiguous,
1045          * but that may not be true for GBE.
1046          */
1047
1048         length = sb->len;
1049
1050         /*
1051          * fill in the descriptor.  Note that the number of cache
1052          * blocks in the descriptor is the number of blocks
1053          * *spanned*, so we need to add in the offset (if any)
1054          * while doing the calculation.
1055          */
1056
1057         phys = virt_to_phys(sb->data);
1058         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1059
1060         dsc->dscr_a = phys |
1061                 V_DMA_DSCRA_A_SIZE(ncb) |
1062 #ifndef CONFIG_SBMAC_COALESCE
1063                 M_DMA_DSCRA_INTERRUPT |
1064 #endif
1065                 M_DMA_ETHTX_SOP;
1066
1067         /* transmitting: set outbound options and length */
1068
1069         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1070                 V_DMA_DSCRB_PKT_SIZE(length);
1071
1072         /*
1073          * fill in the context
1074          */
1075
1076         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1077
1078         /*
1079          * point at next packet
1080          */
1081
1082         d->sbdma_addptr = nextdsc;
1083
1084         /*
1085          * Give the buffer to the DMA engine.
1086          */
1087
1088         SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1089
1090         return 0;                                       /* we did it */
1091 }
1092
1093
1094
1095
1096 /**********************************************************************
1097  *  SBDMA_EMPTYRING(d)
1098  *
1099  *  Free all allocated sk_buffs on the specified DMA channel;
1100  *
1101  *  Input parameters:
1102  *         d  - DMA channel
1103  *
1104  *  Return value:
1105  *         nothing
1106  ********************************************************************* */
1107
1108 static void sbdma_emptyring(sbmacdma_t *d)
1109 {
1110         int idx;
1111         struct sk_buff *sb;
1112
1113         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1114                 sb = d->sbdma_ctxtable[idx];
1115                 if (sb) {
1116                         dev_kfree_skb(sb);
1117                         d->sbdma_ctxtable[idx] = NULL;
1118                 }
1119         }
1120 }
1121
1122
1123 /**********************************************************************
1124  *  SBDMA_FILLRING(d)
1125  *
1126  *  Fill the specified DMA channel (must be receive channel)
1127  *  with sk_buffs
1128  *
1129  *  Input parameters:
1130  *         d - DMA channel
1131  *
1132  *  Return value:
1133  *         nothing
1134  ********************************************************************* */
1135
1136 static void sbdma_fillring(sbmacdma_t *d)
1137 {
1138         int idx;
1139
1140         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1141                 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1142                         break;
1143         }
1144 }
1145
1146
1147 /**********************************************************************
1148  *  SBDMA_RX_PROCESS(sc,d)
1149  *
1150  *  Process "completed" receive buffers on the specified DMA channel.
1151  *  Note that this isn't really ideal for priority channels, since
1152  *  it processes all of the packets on a given channel before
1153  *  returning.
1154  *
1155  *  Input parameters:
1156  *         sc - softc structure
1157  *         d - DMA channel context
1158  *
1159  *  Return value:
1160  *         nothing
1161  ********************************************************************* */
1162
1163 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1164 {
1165         int curidx;
1166         int hwidx;
1167         sbdmadscr_t *dsc;
1168         struct sk_buff *sb;
1169         int len;
1170
1171         for (;;) {
1172                 /*
1173                  * figure out where we are (as an index) and where
1174                  * the hardware is (also as an index)
1175                  *
1176                  * This could be done faster if (for example) the
1177                  * descriptor table was page-aligned and contiguous in
1178                  * both virtual and physical memory -- you could then
1179                  * just compare the low-order bits of the virtual address
1180                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1181                  */
1182
1183                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1184                 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1185                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1186
1187                 /*
1188                  * If they're the same, that means we've processed all
1189                  * of the descriptors up to (but not including) the one that
1190                  * the hardware is working on right now.
1191                  */
1192
1193                 if (curidx == hwidx)
1194                         break;
1195
1196                 /*
1197                  * Otherwise, get the packet's sk_buff ptr back
1198                  */
1199
1200                 dsc = &(d->sbdma_dscrtable[curidx]);
1201                 sb = d->sbdma_ctxtable[curidx];
1202                 d->sbdma_ctxtable[curidx] = NULL;
1203
1204                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1205
1206                 /*
1207                  * Check packet status.  If good, process it.
1208                  * If not, silently drop it and put it back on the
1209                  * receive ring.
1210                  */
1211
1212                 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1213
1214                         /*
1215                          * Add a new buffer to replace the old one.  If we fail
1216                          * to allocate a buffer, we're going to drop this
1217                          * packet and put it right back on the receive ring.
1218                          */
1219
1220                         if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1221                                 sc->sbm_stats.rx_dropped++;
1222                                 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1223                         } else {
1224                                 /*
1225                                  * Set length into the packet
1226                                  */
1227                                 skb_put(sb,len);
1228
1229                                 /*
1230                                  * Buffer has been replaced on the
1231                                  * receive ring.  Pass the buffer to
1232                                  * the kernel
1233                                  */
1234                                 sc->sbm_stats.rx_bytes += len;
1235                                 sc->sbm_stats.rx_packets++;
1236                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1237                                 /* Check hw IPv4/TCP checksum if supported */
1238                                 if (sc->rx_hw_checksum == ENABLE) {
1239                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1240                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1241                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1242                                                 /* don't need to set sb->csum */
1243                                         } else {
1244                                                 sb->ip_summed = CHECKSUM_NONE;
1245                                         }
1246                                 }
1247
1248                                 netif_rx(sb);
1249                         }
1250                 } else {
1251                         /*
1252                          * Packet was mangled somehow.  Just drop it and
1253                          * put it back on the receive ring.
1254                          */
1255                         sc->sbm_stats.rx_errors++;
1256                         sbdma_add_rcvbuffer(d,sb);
1257                 }
1258
1259
1260                 /*
1261                  * .. and advance to the next buffer.
1262                  */
1263
1264                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1265
1266         }
1267 }
1268
1269
1270
1271 /**********************************************************************
1272  *  SBDMA_TX_PROCESS(sc,d)
1273  *
1274  *  Process "completed" transmit buffers on the specified DMA channel.
1275  *  This is normally called within the interrupt service routine.
1276  *  Note that this isn't really ideal for priority channels, since
1277  *  it processes all of the packets on a given channel before
1278  *  returning.
1279  *
1280  *  Input parameters:
1281  *      sc - softc structure
1282  *         d - DMA channel context
1283  *
1284  *  Return value:
1285  *         nothing
1286  ********************************************************************* */
1287
1288 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1289 {
1290         int curidx;
1291         int hwidx;
1292         sbdmadscr_t *dsc;
1293         struct sk_buff *sb;
1294         unsigned long flags;
1295
1296         spin_lock_irqsave(&(sc->sbm_lock), flags);
1297
1298         for (;;) {
1299                 /*
1300                  * figure out where we are (as an index) and where
1301                  * the hardware is (also as an index)
1302                  *
1303                  * This could be done faster if (for example) the
1304                  * descriptor table was page-aligned and contiguous in
1305                  * both virtual and physical memory -- you could then
1306                  * just compare the low-order bits of the virtual address
1307                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1308                  */
1309
1310                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1311                 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1312                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1313
1314                 /*
1315                  * If they're the same, that means we've processed all
1316                  * of the descriptors up to (but not including) the one that
1317                  * the hardware is working on right now.
1318                  */
1319
1320                 if (curidx == hwidx)
1321                         break;
1322
1323                 /*
1324                  * Otherwise, get the packet's sk_buff ptr back
1325                  */
1326
1327                 dsc = &(d->sbdma_dscrtable[curidx]);
1328                 sb = d->sbdma_ctxtable[curidx];
1329                 d->sbdma_ctxtable[curidx] = NULL;
1330
1331                 /*
1332                  * Stats
1333                  */
1334
1335                 sc->sbm_stats.tx_bytes += sb->len;
1336                 sc->sbm_stats.tx_packets++;
1337
1338                 /*
1339                  * for transmits, we just free buffers.
1340                  */
1341
1342                 dev_kfree_skb_irq(sb);
1343
1344                 /*
1345                  * .. and advance to the next buffer.
1346                  */
1347
1348                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1349
1350         }
1351
1352         /*
1353          * Decide if we should wake up the protocol or not.
1354          * Other drivers seem to do this when we reach a low
1355          * watermark on the transmit queue.
1356          */
1357
1358         netif_wake_queue(d->sbdma_eth->sbm_dev);
1359
1360         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1361
1362 }
1363
1364
1365
1366 /**********************************************************************
1367  *  SBMAC_INITCTX(s)
1368  *
1369  *  Initialize an Ethernet context structure - this is called
1370  *  once per MAC on the 1250.  Memory is allocated here, so don't
1371  *  call it again from inside the ioctl routines that bring the
1372  *  interface up/down
1373  *
1374  *  Input parameters:
1375  *         s - sbmac context structure
1376  *
1377  *  Return value:
1378  *         0
1379  ********************************************************************* */
1380
1381 static int sbmac_initctx(struct sbmac_softc *s)
1382 {
1383
1384         /*
1385          * figure out the addresses of some ports
1386          */
1387
1388         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1389         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1390         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1391         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1392         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1393         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1394         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1395         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1396
1397         s->sbm_phys[0]   = 1;
1398         s->sbm_phys[1]   = 0;
1399
1400         s->sbm_phy_oldbmsr = 0;
1401         s->sbm_phy_oldanlpar = 0;
1402         s->sbm_phy_oldk1stsr = 0;
1403         s->sbm_phy_oldlinkstat = 0;
1404
1405         /*
1406          * Initialize the DMA channels.  Right now, only one per MAC is used
1407          * Note: Only do this _once_, as it allocates memory from the kernel!
1408          */
1409
1410         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1411         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1412
1413         /*
1414          * initial state is OFF
1415          */
1416
1417         s->sbm_state = sbmac_state_off;
1418
1419         /*
1420          * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1421          */
1422
1423         s->sbm_speed = sbmac_speed_10;
1424         s->sbm_duplex = sbmac_duplex_half;
1425         s->sbm_fc = sbmac_fc_disabled;
1426
1427         return 0;
1428 }
1429
1430
1431 static void sbdma_uninitctx(struct sbmacdma_s *d)
1432 {
1433         if (d->sbdma_dscrtable) {
1434                 kfree(d->sbdma_dscrtable);
1435                 d->sbdma_dscrtable = NULL;
1436         }
1437
1438         if (d->sbdma_ctxtable) {
1439                 kfree(d->sbdma_ctxtable);
1440                 d->sbdma_ctxtable = NULL;
1441         }
1442 }
1443
1444
1445 static void sbmac_uninitctx(struct sbmac_softc *sc)
1446 {
1447         sbdma_uninitctx(&(sc->sbm_txdma));
1448         sbdma_uninitctx(&(sc->sbm_rxdma));
1449 }
1450
1451
1452 /**********************************************************************
1453  *  SBMAC_CHANNEL_START(s)
1454  *
1455  *  Start packet processing on this MAC.
1456  *
1457  *  Input parameters:
1458  *         s - sbmac structure
1459  *
1460  *  Return value:
1461  *         nothing
1462  ********************************************************************* */
1463
1464 static void sbmac_channel_start(struct sbmac_softc *s)
1465 {
1466         uint64_t reg;
1467         sbmac_port_t port;
1468         uint64_t cfg,fifo,framecfg;
1469         int idx, th_value;
1470
1471         /*
1472          * Don't do this if running
1473          */
1474
1475         if (s->sbm_state == sbmac_state_on)
1476                 return;
1477
1478         /*
1479          * Bring the controller out of reset, but leave it off.
1480          */
1481
1482         SBMAC_WRITECSR(s->sbm_macenable,0);
1483
1484         /*
1485          * Ignore all received packets
1486          */
1487
1488         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1489
1490         /*
1491          * Calculate values for various control registers.
1492          */
1493
1494         cfg = M_MAC_RETRY_EN |
1495                 M_MAC_TX_HOLD_SOP_EN |
1496                 V_MAC_TX_PAUSE_CNT_16K |
1497                 M_MAC_AP_STAT_EN |
1498                 M_MAC_FAST_SYNC |
1499                 M_MAC_SS_EN |
1500                 0;
1501
1502         /*
1503          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1504          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1505          * Use a larger RD_THRSH for gigabit
1506          */
1507         if (periph_rev >= 2)
1508                 th_value = 64;
1509         else
1510                 th_value = 28;
1511
1512         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1513                 ((s->sbm_speed == sbmac_speed_1000)
1514                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1515                 V_MAC_TX_RL_THRSH(4) |
1516                 V_MAC_RX_PL_THRSH(4) |
1517                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1518                 V_MAC_RX_PL_THRSH(4) |
1519                 V_MAC_RX_RL_THRSH(8) |
1520                 0;
1521
1522         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1523                 V_MAC_MAX_FRAMESZ_DEFAULT |
1524                 V_MAC_BACKOFF_SEL(1);
1525
1526         /*
1527          * Clear out the hash address map
1528          */
1529
1530         port = s->sbm_base + R_MAC_HASH_BASE;
1531         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1532                 SBMAC_WRITECSR(port,0);
1533                 port += sizeof(uint64_t);
1534         }
1535
1536         /*
1537          * Clear out the exact-match table
1538          */
1539
1540         port = s->sbm_base + R_MAC_ADDR_BASE;
1541         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1542                 SBMAC_WRITECSR(port,0);
1543                 port += sizeof(uint64_t);
1544         }
1545
1546         /*
1547          * Clear out the DMA Channel mapping table registers
1548          */
1549
1550         port = s->sbm_base + R_MAC_CHUP0_BASE;
1551         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1552                 SBMAC_WRITECSR(port,0);
1553                 port += sizeof(uint64_t);
1554         }
1555
1556
1557         port = s->sbm_base + R_MAC_CHLO0_BASE;
1558         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1559                 SBMAC_WRITECSR(port,0);
1560                 port += sizeof(uint64_t);
1561         }
1562
1563         /*
1564          * Program the hardware address.  It goes into the hardware-address
1565          * register as well as the first filter register.
1566          */
1567
1568         reg = sbmac_addr2reg(s->sbm_hwaddr);
1569
1570         port = s->sbm_base + R_MAC_ADDR_BASE;
1571         SBMAC_WRITECSR(port,reg);
1572         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1573
1574 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1575         /*
1576          * Pass1 SOCs do not receive packets addressed to the
1577          * destination address in the R_MAC_ETHERNET_ADDR register.
1578          * Set the value to zero.
1579          */
1580         SBMAC_WRITECSR(port,0);
1581 #else
1582         SBMAC_WRITECSR(port,reg);
1583 #endif
1584
1585         /*
1586          * Set the receive filter for no packets, and write values
1587          * to the various config registers
1588          */
1589
1590         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1591         SBMAC_WRITECSR(s->sbm_imr,0);
1592         SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1593         SBMAC_WRITECSR(s->sbm_fifocfg,fifo);
1594         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1595
1596         /*
1597          * Initialize DMA channels (rings should be ok now)
1598          */
1599
1600         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1601         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1602
1603         /*
1604          * Configure the speed, duplex, and flow control
1605          */
1606
1607         sbmac_set_speed(s,s->sbm_speed);
1608         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1609
1610         /*
1611          * Fill the receive ring
1612          */
1613
1614         sbdma_fillring(&(s->sbm_rxdma));
1615
1616         /*
1617          * Turn on the rest of the bits in the enable register
1618          */
1619
1620         SBMAC_WRITECSR(s->sbm_macenable,
1621                        M_MAC_RXDMA_EN0 |
1622                        M_MAC_TXDMA_EN0 |
1623                        M_MAC_RX_ENABLE |
1624                        M_MAC_TX_ENABLE);
1625
1626
1627
1628
1629 #ifdef CONFIG_SBMAC_COALESCE
1630         /*
1631          * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1632          */
1633         SBMAC_WRITECSR(s->sbm_imr,
1634                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1635                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
1636 #else
1637         /*
1638          * Accept any kind of interrupt on TX and RX DMA channel 0
1639          */
1640         SBMAC_WRITECSR(s->sbm_imr,
1641                        (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1642                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
1643 #endif
1644
1645         /*
1646          * Enable receiving unicasts and broadcasts
1647          */
1648
1649         SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);
1650
1651         /*
1652          * we're running now.
1653          */
1654
1655         s->sbm_state = sbmac_state_on;
1656
1657         /*
1658          * Program multicast addresses
1659          */
1660
1661         sbmac_setmulti(s);
1662
1663         /*
1664          * If channel was in promiscuous mode before, turn that on
1665          */
1666
1667         if (s->sbm_devflags & IFF_PROMISC) {
1668                 sbmac_promiscuous_mode(s,1);
1669         }
1670
1671 }
1672
1673
1674 /**********************************************************************
1675  *  SBMAC_CHANNEL_STOP(s)
1676  *
1677  *  Stop packet processing on this MAC.
1678  *
1679  *  Input parameters:
1680  *         s - sbmac structure
1681  *
1682  *  Return value:
1683  *         nothing
1684  ********************************************************************* */
1685
1686 static void sbmac_channel_stop(struct sbmac_softc *s)
1687 {
1688         /* don't do this if already stopped */
1689
1690         if (s->sbm_state == sbmac_state_off)
1691                 return;
1692
1693         /* don't accept any packets, disable all interrupts */
1694
1695         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1696         SBMAC_WRITECSR(s->sbm_imr,0);
1697
1698         /* Turn off ticker */
1699
1700         /* XXX */
1701
1702         /* turn off receiver and transmitter */
1703
1704         SBMAC_WRITECSR(s->sbm_macenable,0);
1705
1706         /* We're stopped now. */
1707
1708         s->sbm_state = sbmac_state_off;
1709
1710         /*
1711          * Stop DMA channels (rings should be ok now)
1712          */
1713
1714         sbdma_channel_stop(&(s->sbm_rxdma));
1715         sbdma_channel_stop(&(s->sbm_txdma));
1716
1717         /* Empty the receive and transmit rings */
1718
1719         sbdma_emptyring(&(s->sbm_rxdma));
1720         sbdma_emptyring(&(s->sbm_txdma));
1721
1722 }
1723
1724 /**********************************************************************
1725  *  SBMAC_SET_CHANNEL_STATE(state)
1726  *
1727  *  Set the channel's state ON or OFF
1728  *
1729  *  Input parameters:
1730  *         state - new state
1731  *
1732  *  Return value:
1733  *         old state
1734  ********************************************************************* */
1735 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1736                                              sbmac_state_t state)
1737 {
1738         sbmac_state_t oldstate = sc->sbm_state;
1739
1740         /*
1741          * If same as previous state, return
1742          */
1743
1744         if (state == oldstate) {
1745                 return oldstate;
1746         }
1747
1748         /*
1749          * If new state is ON, turn channel on
1750          */
1751
1752         if (state == sbmac_state_on) {
1753                 sbmac_channel_start(sc);
1754         }
1755         else {
1756                 sbmac_channel_stop(sc);
1757         }
1758
1759         /*
1760          * Return previous state
1761          */
1762
1763         return oldstate;
1764 }
1765
1766
1767 /**********************************************************************
1768  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1769  *
1770  *  Turn on or off promiscuous mode
1771  *
1772  *  Input parameters:
1773  *         sc - softc
1774  *      onoff - 1 to turn on, 0 to turn off
1775  *
1776  *  Return value:
1777  *         nothing
1778  ********************************************************************* */
1779
1780 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1781 {
1782         uint64_t reg;
1783
1784         if (sc->sbm_state != sbmac_state_on)
1785                 return;
1786
1787         if (onoff) {
1788                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1789                 reg |= M_MAC_ALLPKT_EN;
1790                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1791         }
1792         else {
1793                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1794                 reg &= ~M_MAC_ALLPKT_EN;
1795                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1796         }
1797 }
1798
1799 /**********************************************************************
1800  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1801  *
1802  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1803  *
1804  *  Input parameters:
1805  *         sc - softc
1806  *
1807  *  Return value:
1808  *         nothing
1809  ********************************************************************* */
1810
1811 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1812 {
1813         uint64_t reg;
1814
1815         /* Hard code the off set to 15 for now */
1816         reg = SBMAC_READCSR(sc->sbm_rxfilter);
1817         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1818         SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1819
1820         /* read system identification to determine revision */
1821         if (periph_rev >= 2) {
1822                 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
1823                        sc->sbm_dev->name);
1824                 sc->rx_hw_checksum = ENABLE;
1825         } else {
1826                 sc->rx_hw_checksum = DISABLE;
1827         }
1828 }
1829
1830
1831 /**********************************************************************
1832  *  SBMAC_ADDR2REG(ptr)
1833  *
1834  *  Convert six bytes into the 64-bit register value that
1835  *  we typically write into the SBMAC's address/mcast registers
1836  *
1837  *  Input parameters:
1838  *         ptr - pointer to 6 bytes
1839  *
1840  *  Return value:
1841  *         register value
1842  ********************************************************************* */
1843
1844 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1845 {
1846         uint64_t reg = 0;
1847
1848         ptr += 6;
1849
1850         reg |= (uint64_t) *(--ptr);
1851         reg <<= 8;
1852         reg |= (uint64_t) *(--ptr);
1853         reg <<= 8;
1854         reg |= (uint64_t) *(--ptr);
1855         reg <<= 8;
1856         reg |= (uint64_t) *(--ptr);
1857         reg <<= 8;
1858         reg |= (uint64_t) *(--ptr);
1859         reg <<= 8;
1860         reg |= (uint64_t) *(--ptr);
1861
1862         return reg;
1863 }
1864
1865
1866 /**********************************************************************
1867  *  SBMAC_SET_SPEED(s,speed)
1868  *
1869  *  Configure LAN speed for the specified MAC.
1870  *  Warning: must be called when MAC is off!
1871  *
1872  *  Input parameters:
1873  *         s - sbmac structure
1874  *         speed - speed to set MAC to (see sbmac_speed_t enum)
1875  *
1876  *  Return value:
1877  *         1 if successful
1878  *      0 indicates invalid parameters
1879  ********************************************************************* */
1880
1881 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1882 {
1883         uint64_t cfg;
1884         uint64_t framecfg;
1885
1886         /*
1887          * Save new current values
1888          */
1889
1890         s->sbm_speed = speed;
1891
1892         if (s->sbm_state == sbmac_state_on)
1893                 return 0;       /* save for next restart */
1894
1895         /*
1896          * Read current register values
1897          */
1898
1899         cfg = SBMAC_READCSR(s->sbm_maccfg);
1900         framecfg = SBMAC_READCSR(s->sbm_framecfg);
1901
1902         /*
1903          * Mask out the stuff we want to change
1904          */
1905
1906         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1907         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1908                       M_MAC_SLOT_SIZE);
1909
1910         /*
1911          * Now add in the new bits
1912          */
1913
1914         switch (speed) {
1915         case sbmac_speed_10:
1916                 framecfg |= V_MAC_IFG_RX_10 |
1917                         V_MAC_IFG_TX_10 |
1918                         K_MAC_IFG_THRSH_10 |
1919                         V_MAC_SLOT_SIZE_10;
1920                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1921                 break;
1922
1923         case sbmac_speed_100:
1924                 framecfg |= V_MAC_IFG_RX_100 |
1925                         V_MAC_IFG_TX_100 |
1926                         V_MAC_IFG_THRSH_100 |
1927                         V_MAC_SLOT_SIZE_100;
1928                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1929                 break;
1930
1931         case sbmac_speed_1000:
1932                 framecfg |= V_MAC_IFG_RX_1000 |
1933                         V_MAC_IFG_TX_1000 |
1934                         V_MAC_IFG_THRSH_1000 |
1935                         V_MAC_SLOT_SIZE_1000;
1936                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1937                 break;
1938
1939         case sbmac_speed_auto:          /* XXX not implemented */
1940                 /* fall through */
1941         default:
1942                 return 0;
1943         }
1944
1945         /*
1946          * Send the bits back to the hardware
1947          */
1948
1949         SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1950         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1951
1952         return 1;
1953 }
1954
1955 /**********************************************************************
1956  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1957  *
1958  *  Set Ethernet duplex and flow control options for this MAC
1959  *  Warning: must be called when MAC is off!
1960  *
1961  *  Input parameters:
1962  *         s - sbmac structure
1963  *         duplex - duplex setting (see sbmac_duplex_t)
1964  *         fc - flow control setting (see sbmac_fc_t)
1965  *
1966  *  Return value:
1967  *         1 if ok
1968  *         0 if an invalid parameter combination was specified
1969  ********************************************************************* */
1970
1971 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1972 {
1973         uint64_t cfg;
1974
1975         /*
1976          * Save new current values
1977          */
1978
1979         s->sbm_duplex = duplex;
1980         s->sbm_fc = fc;
1981
1982         if (s->sbm_state == sbmac_state_on)
1983                 return 0;       /* save for next restart */
1984
1985         /*
1986          * Read current register values
1987          */
1988
1989         cfg = SBMAC_READCSR(s->sbm_maccfg);
1990
1991         /*
1992          * Mask off the stuff we're about to change
1993          */
1994
1995         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1996
1997
1998         switch (duplex) {
1999         case sbmac_duplex_half:
2000                 switch (fc) {
2001                 case sbmac_fc_disabled:
2002                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2003                         break;
2004
2005                 case sbmac_fc_collision:
2006                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2007                         break;
2008
2009                 case sbmac_fc_carrier:
2010                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2011                         break;
2012
2013                 case sbmac_fc_auto:             /* XXX not implemented */
2014                         /* fall through */
2015                 case sbmac_fc_frame:            /* not valid in half duplex */
2016                 default:                        /* invalid selection */
2017                         return 0;
2018                 }
2019                 break;
2020
2021         case sbmac_duplex_full:
2022                 switch (fc) {
2023                 case sbmac_fc_disabled:
2024                         cfg |= V_MAC_FC_CMD_DISABLED;
2025                         break;
2026
2027                 case sbmac_fc_frame:
2028                         cfg |= V_MAC_FC_CMD_ENABLED;
2029                         break;
2030
2031                 case sbmac_fc_collision:        /* not valid in full duplex */
2032                 case sbmac_fc_carrier:          /* not valid in full duplex */
2033                 case sbmac_fc_auto:             /* XXX not implemented */
2034                         /* fall through */
2035                 default:
2036                         return 0;
2037                 }
2038                 break;
2039         case sbmac_duplex_auto:
2040                 /* XXX not implemented */
2041                 break;
2042         }
2043
2044         /*
2045          * Send the bits back to the hardware
2046          */
2047
2048         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
2049
2050         return 1;
2051 }
2052
2053
2054
2055
2056 /**********************************************************************
2057  *  SBMAC_INTR()
2058  *
2059  *  Interrupt handler for MAC interrupts
2060  *
2061  *  Input parameters:
2062  *         MAC structure
2063  *
2064  *  Return value:
2065  *         nothing
2066  ********************************************************************* */
2067 static void sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2068 {
2069         struct net_device *dev = (struct net_device *) dev_instance;
2070         struct sbmac_softc *sc = (struct sbmac_softc *) (dev->priv);
2071         uint64_t isr;
2072
2073         for (;;) {
2074
2075                 /*
2076                  * Read the ISR (this clears the bits in the real
2077                  * register, except for counter addr)
2078                  */
2079
2080                 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2081
2082                 if (isr == 0)
2083                         break;
2084
2085                 /*
2086                  * Transmits on channel 0
2087                  */
2088
2089                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2090                         sbdma_tx_process(sc,&(sc->sbm_txdma));
2091                 }
2092
2093                 /*
2094                  * Receives on channel 0
2095                  */
2096
2097                 /*
2098                  * It's important to test all the bits (or at least the
2099                  * EOP_SEEN bit) when deciding to do the RX process
2100                  * particularly when coalescing, to make sure we
2101                  * take care of the following:
2102                  *
2103                  * If you have some packets waiting (have been received
2104                  * but no interrupt) and get a TX interrupt before
2105                  * the RX timer or counter expires, reading the ISR
2106                  * above will clear the timer and counter, and you
2107                  * won't get another interrupt until a packet shows
2108                  * up to start the timer again.  Testing
2109                  * EOP_SEEN here takes care of this case.
2110                  * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2111                  */
2112
2113
2114                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2115                         sbdma_rx_process(sc,&(sc->sbm_rxdma));
2116                 }
2117         }
2118 }
2119
2120
2121 /**********************************************************************
2122  *  SBMAC_START_TX(skb,dev)
2123  *
2124  *  Start output on the specified interface.  Basically, we
2125  *  queue as many buffers as we can until the ring fills up, or
2126  *  we run off the end of the queue, whichever comes first.
2127  *
2128  *  Input parameters:
2129  *
2130  *
2131  *  Return value:
2132  *         nothing
2133  ********************************************************************* */
2134 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2135 {
2136         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2137
2138         /* lock eth irq */
2139         spin_lock_irq (&sc->sbm_lock);
2140
2141         /*
2142          * Put the buffer on the transmit ring.  If we
2143          * don't have room, stop the queue.
2144          */
2145
2146         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2147                 /* XXX save skb that we could not send */
2148                 netif_stop_queue(dev);
2149                 spin_unlock_irq(&sc->sbm_lock);
2150
2151                 return 1;
2152         }
2153
2154         dev->trans_start = jiffies;
2155
2156         spin_unlock_irq (&sc->sbm_lock);
2157
2158         return 0;
2159 }
2160
2161 /**********************************************************************
2162  *  SBMAC_SETMULTI(sc)
2163  *
2164  *  Reprogram the multicast table into the hardware, given
2165  *  the list of multicasts associated with the interface
2166  *  structure.
2167  *
2168  *  Input parameters:
2169  *         sc - softc
2170  *
2171  *  Return value:
2172  *         nothing
2173  ********************************************************************* */
2174
2175 static void sbmac_setmulti(struct sbmac_softc *sc)
2176 {
2177         uint64_t reg;
2178         sbmac_port_t port;
2179         int idx;
2180         struct dev_mc_list *mclist;
2181         struct net_device *dev = sc->sbm_dev;
2182
2183         /*
2184          * Clear out entire multicast table.  We do this by nuking
2185          * the entire hash table and all the direct matches except
2186          * the first one, which is used for our station address
2187          */
2188
2189         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2190                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2191                 SBMAC_WRITECSR(port,0);
2192         }
2193
2194         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2195                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2196                 SBMAC_WRITECSR(port,0);
2197         }
2198
2199         /*
2200          * Clear the filter to say we don't want any multicasts.
2201          */
2202
2203         reg = SBMAC_READCSR(sc->sbm_rxfilter);
2204         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2205         SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2206
2207         if (dev->flags & IFF_ALLMULTI) {
2208                 /*
2209                  * Enable ALL multicasts.  Do this by inverting the
2210                  * multicast enable bit.
2211                  */
2212                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2213                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2214                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2215                 return;
2216         }
2217
2218
2219         /*
2220          * Progam new multicast entries.  For now, only use the
2221          * perfect filter.  In the future we'll need to use the
2222          * hash filter if the perfect filter overflows
2223          */
2224
2225         /* XXX only using perfect filter for now, need to use hash
2226          * XXX if the table overflows */
2227
2228         idx = 1;                /* skip station address */
2229         mclist = dev->mc_list;
2230         while (mclist && (idx < MAC_ADDR_COUNT)) {
2231                 reg = sbmac_addr2reg(mclist->dmi_addr);
2232                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2233                 SBMAC_WRITECSR(port,reg);
2234                 idx++;
2235                 mclist = mclist->next;
2236         }
2237
2238         /*
2239          * Enable the "accept multicast bits" if we programmed at least one
2240          * multicast.
2241          */
2242
2243         if (idx > 1) {
2244                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2245                 reg |= M_MAC_MCAST_EN;
2246                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2247         }
2248 }
2249
2250
2251
2252 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2253 /**********************************************************************
2254  *  SBMAC_PARSE_XDIGIT(str)
2255  *
2256  *  Parse a hex digit, returning its value
2257  *
2258  *  Input parameters:
2259  *         str - character
2260  *
2261  *  Return value:
2262  *         hex value, or -1 if invalid
2263  ********************************************************************* */
2264
2265 static int sbmac_parse_xdigit(char str)
2266 {
2267         int digit;
2268
2269         if ((str >= '0') && (str <= '9'))
2270                 digit = str - '0';
2271         else if ((str >= 'a') && (str <= 'f'))
2272                 digit = str - 'a' + 10;
2273         else if ((str >= 'A') && (str <= 'F'))
2274                 digit = str - 'A' + 10;
2275         else
2276                 return -1;
2277
2278         return digit;
2279 }
2280
2281 /**********************************************************************
2282  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2283  *
2284  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2285  *  Ethernet address.
2286  *
2287  *  Input parameters:
2288  *         str - string
2289  *         hwaddr - pointer to hardware address
2290  *
2291  *  Return value:
2292  *         0 if ok, else -1
2293  ********************************************************************* */
2294
2295 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2296 {
2297         int digit1,digit2;
2298         int idx = 6;
2299
2300         while (*str && (idx > 0)) {
2301                 digit1 = sbmac_parse_xdigit(*str);
2302                 if (digit1 < 0)
2303                         return -1;
2304                 str++;
2305                 if (!*str)
2306                         return -1;
2307
2308                 if ((*str == ':') || (*str == '-')) {
2309                         digit2 = digit1;
2310                         digit1 = 0;
2311                 }
2312                 else {
2313                         digit2 = sbmac_parse_xdigit(*str);
2314                         if (digit2 < 0)
2315                                 return -1;
2316                         str++;
2317                 }
2318
2319                 *hwaddr++ = (digit1 << 4) | digit2;
2320                 idx--;
2321
2322                 if (*str == '-')
2323                         str++;
2324                 if (*str == ':')
2325                         str++;
2326         }
2327         return 0;
2328 }
2329 #endif
2330
2331 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2332 {
2333         if (new_mtu >  ENET_PACKET_SIZE)
2334                 return -EINVAL;
2335         _dev->mtu = new_mtu;
2336         printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2337         return 0;
2338 }
2339
2340 /**********************************************************************
2341  *  SBMAC_INIT(dev)
2342  *
2343  *  Attach routine - init hardware and hook ourselves into linux
2344  *
2345  *  Input parameters:
2346  *         dev - net_device structure
2347  *
2348  *  Return value:
2349  *         status
2350  ********************************************************************* */
2351
2352 static int sbmac_init(struct net_device *dev, int idx)
2353 {
2354         struct sbmac_softc *sc;
2355         unsigned char *eaddr;
2356         uint64_t ea_reg;
2357         int i;
2358
2359         sc = (struct sbmac_softc *)dev->priv;
2360
2361         /* Determine controller base address */
2362
2363         sc->sbm_base = KSEG1ADDR(dev->base_addr);
2364         sc->sbm_dev = dev;
2365         sc->sbe_idx = idx;
2366
2367         eaddr = sc->sbm_hwaddr;
2368
2369         /*
2370          * Read the ethernet address.  The firwmare left this programmed
2371          * for us in the ethernet address register for each mac.
2372          */
2373
2374         ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2375         SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0);
2376         for (i = 0; i < 6; i++) {
2377                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2378                 ea_reg >>= 8;
2379         }
2380
2381         for (i = 0; i < 6; i++) {
2382                 dev->dev_addr[i] = eaddr[i];
2383         }
2384
2385
2386         /*
2387          * Init packet size
2388          */
2389
2390         sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2391
2392         /*
2393          * Initialize context (get pointers to registers and stuff), then
2394          * allocate the memory for the descriptor tables.
2395          */
2396
2397         sbmac_initctx(sc);
2398
2399
2400         /*
2401          * Display Ethernet address (this is called during the config
2402          * process so we need to finish off the config message that
2403          * was being displayed)
2404          */
2405         printk(KERN_INFO
2406                "%s: SiByte Ethernet at 0x%08lX, address: %02X-%02X-%02X-%02X-%02X-%02X\n",
2407                dev->name, dev->base_addr,
2408                eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2409
2410         /*
2411          * Set up Linux device callins
2412          */
2413
2414         spin_lock_init(&(sc->sbm_lock));
2415
2416         ether_setup(dev);
2417         dev->open               = sbmac_open;
2418         dev->hard_start_xmit    = sbmac_start_tx;
2419         dev->stop               = sbmac_close;
2420         dev->get_stats          = sbmac_get_stats;
2421         dev->set_multicast_list = sbmac_set_rx_mode;
2422         dev->do_ioctl           = sbmac_mii_ioctl;
2423         dev->tx_timeout         = sbmac_tx_timeout;
2424         dev->watchdog_timeo     = TX_TIMEOUT;
2425
2426         dev->change_mtu         = sb1250_change_mtu;
2427
2428         /* This is needed for PASS2 for Rx H/W checksum feature */
2429         sbmac_set_iphdr_offset(sc);
2430
2431         return 0;
2432 }
2433
2434
2435 static int sbmac_open(struct net_device *dev)
2436 {
2437         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2438
2439         MOD_INC_USE_COUNT;
2440
2441         if (debug > 1) {
2442                 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2443         }
2444
2445         /*
2446          * map/route interrupt (clear status first, in case something
2447          * weird is pending; we haven't initialized the mac registers
2448          * yet)
2449          */
2450
2451         SBMAC_READCSR(sc->sbm_isr);
2452         if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev)) {
2453                 MOD_DEC_USE_COUNT;
2454                 return -EBUSY;
2455         }
2456
2457         /*
2458          * Configure default speed
2459          */
2460
2461         sbmac_mii_poll(sc,noisy_mii);
2462
2463         /*
2464          * Turn on the channel
2465          */
2466
2467         sbmac_set_channel_state(sc,sbmac_state_on);
2468
2469         /*
2470          * XXX Station address is in dev->dev_addr
2471          */
2472
2473         if (dev->if_port == 0)
2474                 dev->if_port = 0;
2475
2476         netif_start_queue(dev);
2477
2478         sbmac_set_rx_mode(dev);
2479
2480         /* Set the timer to check for link beat. */
2481         init_timer(&sc->sbm_timer);
2482         sc->sbm_timer.expires = jiffies + 2;
2483         sc->sbm_timer.data = (unsigned long)dev;
2484         sc->sbm_timer.function = &sbmac_timer;
2485         add_timer(&sc->sbm_timer);
2486
2487         return 0;
2488 }
2489
2490
2491
2492 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2493 {
2494     int bmsr,bmcr,k1stsr,anlpar;
2495     int chg;
2496     char buffer[100];
2497     char *p = buffer;
2498
2499     /* Read the mode status and mode control registers. */
2500     bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2501     bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2502
2503     /* get the link partner status */
2504     anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2505
2506     /* if supported, read the 1000baseT register */
2507     if (bmsr & BMSR_1000BT_XSR) {
2508         k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2509         }
2510     else {
2511         k1stsr = 0;
2512         }
2513
2514     chg = 0;
2515
2516     if ((bmsr & BMSR_LINKSTAT) == 0) {
2517         /*
2518          * If link status is down, clear out old info so that when
2519          * it comes back up it will force us to reconfigure speed
2520          */
2521         s->sbm_phy_oldbmsr = 0;
2522         s->sbm_phy_oldanlpar = 0;
2523         s->sbm_phy_oldk1stsr = 0;
2524         return 0;
2525         }
2526
2527     if ((s->sbm_phy_oldbmsr != bmsr) ||
2528         (s->sbm_phy_oldanlpar != anlpar) ||
2529         (s->sbm_phy_oldk1stsr != k1stsr)) {
2530         if (debug > 1) {
2531             printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x  k1stsr:%x/%x\n",
2532                s->sbm_dev->name,
2533                s->sbm_phy_oldbmsr,bmsr,
2534                s->sbm_phy_oldanlpar,anlpar,
2535                s->sbm_phy_oldk1stsr,k1stsr);
2536             }
2537         s->sbm_phy_oldbmsr = bmsr;
2538         s->sbm_phy_oldanlpar = anlpar;
2539         s->sbm_phy_oldk1stsr = k1stsr;
2540         chg = 1;
2541         }
2542
2543     if (chg == 0)
2544             return 0;
2545
2546     p += sprintf(p,"Link speed: ");
2547
2548     if (k1stsr & K1STSR_LP1KFD) {
2549         s->sbm_speed = sbmac_speed_1000;
2550         s->sbm_duplex = sbmac_duplex_full;
2551         s->sbm_fc = sbmac_fc_frame;
2552         p += sprintf(p,"1000BaseT FDX");
2553         }
2554     else if (k1stsr & K1STSR_LP1KHD) {
2555         s->sbm_speed = sbmac_speed_1000;
2556         s->sbm_duplex = sbmac_duplex_half;
2557         s->sbm_fc = sbmac_fc_disabled;
2558         p += sprintf(p,"1000BaseT HDX");
2559         }
2560     else if (anlpar & ANLPAR_TXFD) {
2561         s->sbm_speed = sbmac_speed_100;
2562         s->sbm_duplex = sbmac_duplex_full;
2563         s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2564         p += sprintf(p,"100BaseT FDX");
2565         }
2566     else if (anlpar & ANLPAR_TXHD) {
2567         s->sbm_speed = sbmac_speed_100;
2568         s->sbm_duplex = sbmac_duplex_half;
2569         s->sbm_fc = sbmac_fc_disabled;
2570         p += sprintf(p,"100BaseT HDX");
2571         }
2572     else if (anlpar & ANLPAR_10FD) {
2573         s->sbm_speed = sbmac_speed_10;
2574         s->sbm_duplex = sbmac_duplex_full;
2575         s->sbm_fc = sbmac_fc_frame;
2576         p += sprintf(p,"10BaseT FDX");
2577         }
2578     else if (anlpar & ANLPAR_10HD) {
2579         s->sbm_speed = sbmac_speed_10;
2580         s->sbm_duplex = sbmac_duplex_half;
2581         s->sbm_fc = sbmac_fc_collision;
2582         p += sprintf(p,"10BaseT HDX");
2583         }
2584     else {
2585         p += sprintf(p,"Unknown");
2586         }
2587
2588     if (noisy) {
2589             printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2590             }
2591
2592     return 1;
2593 }
2594
2595
2596 static void sbmac_timer(unsigned long data)
2597 {
2598         struct net_device *dev = (struct net_device *)data;
2599         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2600         int next_tick = HZ;
2601         int mii_status;
2602
2603         spin_lock_irq (&sc->sbm_lock);
2604
2605         /* make IFF_RUNNING follow the MII status bit "Link established" */
2606         mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2607
2608         if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2609                 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2610                 if (mii_status & BMSR_LINKSTAT) {
2611                         netif_carrier_on(dev);
2612                 }
2613                 else {
2614                         netif_carrier_off(dev);
2615                 }
2616         }
2617
2618         /*
2619          * Poll the PHY to see what speed we should be running at
2620          */
2621
2622         if (sbmac_mii_poll(sc,noisy_mii)) {
2623                 if (sc->sbm_state != sbmac_state_off) {
2624                         /*
2625                          * something changed, restart the channel
2626                          */
2627                         if (debug > 1) {
2628                                 printk("%s: restarting channel because speed changed\n",
2629                                        sc->sbm_dev->name);
2630                         }
2631                         sbmac_channel_stop(sc);
2632                         sbmac_channel_start(sc);
2633                 }
2634         }
2635
2636         spin_unlock_irq (&sc->sbm_lock);
2637
2638         sc->sbm_timer.expires = jiffies + next_tick;
2639         add_timer(&sc->sbm_timer);
2640 }
2641
2642
2643 static void sbmac_tx_timeout (struct net_device *dev)
2644 {
2645         struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv;
2646
2647         spin_lock_irq (&sc->sbm_lock);
2648
2649
2650         dev->trans_start = jiffies;
2651         sc->sbm_stats.tx_errors++;
2652
2653         spin_unlock_irq (&sc->sbm_lock);
2654
2655         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2656 }
2657
2658
2659
2660
2661 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2662 {
2663         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2664         unsigned long flags;
2665
2666         spin_lock_irqsave(&sc->sbm_lock, flags);
2667
2668         /* XXX update other stats here */
2669
2670         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2671
2672         return &sc->sbm_stats;
2673 }
2674
2675
2676
2677 static void sbmac_set_rx_mode(struct net_device *dev)
2678 {
2679         unsigned long flags;
2680         int msg_flag = 0;
2681         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2682
2683         spin_lock_irqsave(&sc->sbm_lock, flags);
2684         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2685                 /*
2686                  * Promiscuous changed.
2687                  */
2688
2689                 if (dev->flags & IFF_PROMISC) {
2690                         /* Unconditionally log net taps. */
2691                         msg_flag = 1;
2692                         sbmac_promiscuous_mode(sc,1);
2693                 }
2694                 else {
2695                         msg_flag = 2;
2696                         sbmac_promiscuous_mode(sc,0);
2697                 }
2698         }
2699         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2700
2701         if (msg_flag) {
2702                 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2703                        dev->name,(msg_flag==1)?"en":"dis");
2704         }
2705
2706         /*
2707          * Program the multicasts.  Do this every time.
2708          */
2709
2710         sbmac_setmulti(sc);
2711
2712 }
2713
2714 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2715 {
2716         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2717         u16 *data = (u16 *)&rq->ifr_data;
2718         unsigned long flags;
2719         int retval;
2720
2721         spin_lock_irqsave(&sc->sbm_lock, flags);
2722         retval = 0;
2723
2724         switch(cmd) {
2725         case SIOCDEVPRIVATE:            /* Get the address of the PHY in use. */
2726                 data[0] = sc->sbm_phys[0] & 0x1f;
2727                 /* Fall Through */
2728         case SIOCDEVPRIVATE+1:          /* Read the specified MII register. */
2729                 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2730                 break;
2731         case SIOCDEVPRIVATE+2:          /* Write the specified MII register */
2732                 if (!capable(CAP_NET_ADMIN)) {
2733                         retval = -EPERM;
2734                         break;
2735                 }
2736                 if (debug > 1) {
2737                     printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2738                        data[0],data[1],data[2]);
2739                     }
2740                 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2741                 break;
2742         default:
2743                 retval = -EOPNOTSUPP;
2744         }
2745
2746         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2747         return retval;
2748 }
2749
2750 static int sbmac_close(struct net_device *dev)
2751 {
2752         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2753         unsigned long flags;
2754
2755         sbmac_set_channel_state(sc,sbmac_state_off);
2756
2757         del_timer_sync(&sc->sbm_timer);
2758
2759         spin_lock_irqsave(&sc->sbm_lock, flags);
2760
2761         netif_stop_queue(dev);
2762
2763         if (debug > 1) {
2764                 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2765         }
2766
2767         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2768
2769         synchronize_irq();
2770         free_irq(dev->irq, dev);
2771
2772         sbdma_emptyring(&(sc->sbm_txdma));
2773         sbdma_emptyring(&(sc->sbm_rxdma));
2774
2775         MOD_DEC_USE_COUNT;
2776
2777         return 0;
2778 }
2779
2780
2781
2782 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2783 static void
2784 sbmac_setup_hwaddr(int chan,char *addr)
2785 {
2786         uint8_t eaddr[6];
2787         uint64_t val;
2788         sbmac_port_t port;
2789
2790         port = A_MAC_CHANNEL_BASE(chan);
2791         sbmac_parse_hwaddr(addr,eaddr);
2792         val = sbmac_addr2reg(eaddr);
2793         SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR),val);
2794         val = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR));
2795 }
2796 #endif
2797
2798 static struct net_device *dev_sbmac[MAX_UNITS] = {0,0,0};
2799
2800 static int __init
2801 sbmac_init_module(void)
2802 {
2803         int idx;
2804         int macidx = 0;
2805         struct net_device *dev;
2806         sbmac_port_t port;
2807         int chip_max_units;
2808
2809         /*
2810          * For bringup when not using the firmware, we can pre-fill
2811          * the MAC addresses using the environment variables
2812          * specified in this file (or maybe from the config file?)
2813          */
2814 #ifdef SBMAC_ETH0_HWADDR
2815         sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2816 #endif
2817 #ifdef SBMAC_ETH1_HWADDR
2818         sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2819 #endif
2820 #ifdef SBMAC_ETH2_HWADDR
2821         sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2822 #endif
2823
2824         /*
2825          * Walk through the Ethernet controllers and find
2826          * those who have their MAC addresses set.
2827          */
2828         switch (soc_type) {
2829         case K_SYS_SOC_TYPE_BCM1250:
2830         case K_SYS_SOC_TYPE_BCM1250_ALT:
2831                 chip_max_units = 3;
2832                 break;
2833         case K_SYS_SOC_TYPE_BCM1120:
2834         case K_SYS_SOC_TYPE_BCM1125:
2835         case K_SYS_SOC_TYPE_BCM1125H:
2836         case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2837                 chip_max_units = 2;
2838                 break;
2839         default:
2840                 chip_max_units = 0;
2841                 break;
2842         }
2843         if (chip_max_units > MAX_UNITS)
2844                 chip_max_units = MAX_UNITS;
2845
2846         for (idx = 0; idx < chip_max_units; idx++) {
2847
2848                 /*
2849                  * This is the base address of the MAC.
2850                  */
2851
2852                 port = A_MAC_CHANNEL_BASE(idx);
2853
2854                 /*
2855                  * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2856                  * value for us by the firmware if we're going to use this MAC.
2857                  * If we find a zero, skip this MAC.
2858                  */
2859
2860                 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR));
2861                 if (sbmac_orig_hwaddr[idx] == 0) {
2862                         printk(KERN_DEBUG "sbmac: not configuring MAC at "
2863                                "%lx\n", port);
2864                     continue;
2865                 }
2866
2867                 /*
2868                  * Okay, cool.  Initialize this MAC.
2869                  */
2870
2871                 dev = init_etherdev(NULL,sizeof(struct sbmac_softc));
2872                 if (!dev)
2873                   return -ENOMEM;       /* return ENOMEM */
2874
2875                 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2876
2877                 dev->irq = K_INT_MAC_0 + idx;
2878                 dev->base_addr = port;
2879                 dev->mem_end = 0;
2880                 /*dev->init = sbmac_init;*/
2881                 sbmac_init(dev, macidx);
2882
2883                 dev_sbmac[macidx] = dev;
2884                 macidx++;
2885         }
2886
2887         /*
2888          * Should we care, 'macidx' is the total number of enabled MACs.
2889          */
2890
2891         return 0;
2892 }
2893
2894
2895 static void __exit
2896 sbmac_cleanup_module(void)
2897 {
2898         int idx;
2899         struct net_device *dev;
2900         sbmac_port_t port;
2901         for (idx = 0; idx < MAX_UNITS; idx++) {
2902                 dev = dev_sbmac[idx];
2903                 if (dev == NULL)
2904                         continue;
2905                 if (dev->priv != NULL) {
2906                         struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv;
2907
2908                         unregister_netdev(dev);
2909
2910                         sbmac_uninitctx(sc);
2911
2912                 }
2913
2914                 port = A_MAC_CHANNEL_BASE(idx);
2915                 SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR), sbmac_orig_hwaddr[idx] );
2916                 kfree(dev);
2917                 dev_sbmac[idx] = NULL;
2918         }
2919 }
2920
2921 module_init(sbmac_init_module);
2922 module_exit(sbmac_cleanup_module);