2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
6 -- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
7 -- All of the components are assembled and instanciated on this board.
12 --logic analyzer reference clock
13 signal dbg_base_clk: out std_logic;
\r
16 pi_base_clk : in std_logic;
17 pi_rst_n : in std_logic;
18 pi_joypad1 : in std_logic_vector(7 downto 0);
19 pi_joypad2 : in std_logic_vector(7 downto 0);
20 po_h_sync_n : out std_logic;
21 po_v_sync_n : out std_logic;
22 po_r : out std_logic_vector(3 downto 0);
23 po_g : out std_logic_vector(3 downto 0);
24 po_b : out std_logic_vector(3 downto 0);
25 pi_nt_v_mirror : in std_logic;
\r
28 po_dbg_cnt : out std_logic_vector (63 downto 0);
\r
29 po_exc_cnt : out std_logic_vector (63 downto 0)
\r
33 architecture rtl of de0_cv_nes is
36 pi_rst_n : in std_logic;
\r
37 pi_base_clk : in std_logic;
\r
38 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
39 pi_rdy : in std_logic;
\r
40 pi_irq_n : in std_logic;
\r
41 pi_nmi_n : in std_logic;
\r
42 po_oe_n : out std_logic;
\r
43 po_we_n : out std_logic;
\r
44 po_addr : out std_logic_vector (15 downto 0);
\r
45 pio_d_io : inout std_logic_vector (7 downto 0);
\r
46 po_exc_cnt : out std_logic_vector (63 downto 0)
\r
50 component clock_selector
\r
52 pi_rst_n : in std_logic;
\r
53 pi_base_clk : in std_logic;
\r
54 po_cpu_en : out std_logic_vector (7 downto 0);
\r
55 po_rnd_en : out std_logic_vector (3 downto 0)
\r
59 component chip_selector
\r
61 pi_rst_n : in std_logic;
\r
62 pi_base_clk : in std_logic;
\r
63 pi_addr : in std_logic_vector (15 downto 0);
\r
64 po_rom_ce_n : out std_logic;
\r
65 po_ram_ce_n : out std_logic;
\r
66 po_ppu_ce_n : out std_logic;
\r
67 po_apu_ce_n : out std_logic
\r
71 component prg_rom port (
\r
72 pi_base_clk : in std_logic;
\r
73 pi_ce_n : in std_logic;
\r
74 pi_oe_n : in std_logic;
\r
75 pi_addr : in std_logic_vector (14 downto 0);
\r
76 po_data : out std_logic_vector (7 downto 0)
\r
81 pi_rst_n : in std_logic;
\r
82 pi_base_clk : in std_logic;
83 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
84 pi_ce_n : in std_logic;
85 pi_oe_n : in std_logic;
\r
86 pi_we_n : in std_logic;
\r
87 pi_cpu_addr : in std_logic_vector (2 downto 0);
88 pio_cpu_d : inout std_logic_vector (7 downto 0);
\r
89 po_vblank_n : out std_logic;
\r
91 po_v_ce_n : out std_logic;
\r
92 po_v_rd_n : out std_logic;
\r
93 po_v_wr_n : out std_logic;
\r
94 po_v_addr : out std_logic_vector (13 downto 0);
\r
95 pio_v_data : inout std_logic_vector (7 downto 0);
\r
97 po_plt_ce_n : out std_logic;
\r
98 po_plt_rd_n : out std_logic;
\r
99 po_plt_wr_n : out std_logic;
\r
100 po_plt_addr : out std_logic_vector (4 downto 0);
\r
101 pio_plt_data : inout std_logic_vector (7 downto 0);
\r
103 po_spr_ce_n : out std_logic;
\r
104 po_spr_rd_n : out std_logic;
\r
105 po_spr_wr_n : out std_logic;
\r
106 po_spr_addr : out std_logic_vector (7 downto 0);
\r
107 po_spr_data : out std_logic_vector (7 downto 0);
\r
109 po_ppu_ctrl : out std_logic_vector (7 downto 0);
\r
110 po_ppu_mask : out std_logic_vector (7 downto 0);
\r
111 pi_ppu_status : in std_logic_vector (7 downto 0);
\r
112 po_ppu_scroll_x : out std_logic_vector (7 downto 0);
\r
113 po_ppu_scroll_y : out std_logic_vector (7 downto 0)
\r
118 generic (abus_size : integer := 16; dbus_size : integer := 8; debug_mem : string := "null-file.bin");
\r
120 pi_base_clk : in std_logic;
\r
121 pi_ce_n : in std_logic;
\r
122 pi_oe_n : in std_logic;
\r
123 pi_we_n : in std_logic;
\r
124 pi_addr : in std_logic_vector (abus_size - 1 downto 0);
\r
125 pio_d_io : inout std_logic_vector (dbus_size - 1 downto 0)
\r
129 component palette_ram
\r
131 pi_base_clk : in std_logic;
\r
132 pi_ce_n : in std_logic;
\r
133 pi_oe_n : in std_logic;
\r
134 pi_we_n : in std_logic;
\r
135 pi_addr : in std_logic_vector (4 downto 0);
\r
136 pio_d_io : inout std_logic_vector (7 downto 0)
\r
142 pi_base_clk : in std_logic;
\r
143 pi_ce_n : in std_logic;
\r
144 pi_oe_n : in std_logic;
\r
145 pi_addr : in std_logic_vector (12 downto 0);
\r
146 po_data : out std_logic_vector (7 downto 0)
\r
150 component v_chip_selector
\r
152 pi_rst_n : in std_logic;
\r
153 pi_base_clk : in std_logic;
\r
154 pi_v_ce_n : in std_logic;
\r
155 pi_v_addr : in std_logic_vector (13 downto 0);
\r
156 pi_nt_v_mirror : in std_logic;
\r
157 po_pt_ce_n : out std_logic;
\r
158 po_nt0_ce_n : out std_logic;
\r
159 po_nt1_ce_n : out std_logic
\r
165 pi_rst_n : in std_logic;
\r
166 pi_base_clk : in std_logic;
\r
167 pi_rnd_en : in std_logic_vector (3 downto 0);
\r
170 pi_ppu_ctrl : in std_logic_vector (7 downto 0);
\r
171 pi_ppu_mask : in std_logic_vector (7 downto 0);
\r
172 po_ppu_status : out std_logic_vector (7 downto 0);
\r
173 pi_ppu_scroll_x : in std_logic_vector (7 downto 0);
\r
174 pi_ppu_scroll_y : in std_logic_vector (7 downto 0);
\r
177 po_v_ce_n : out std_logic;
\r
178 po_v_rd_n : out std_logic;
\r
179 po_v_wr_n : out std_logic;
\r
180 po_v_addr : out std_logic_vector (13 downto 0);
\r
181 pi_v_data : in std_logic_vector (7 downto 0);
\r
184 po_plt_ce_n : out std_logic;
\r
185 po_plt_rd_n : out std_logic;
\r
186 po_plt_wr_n : out std_logic;
\r
187 po_plt_addr : out std_logic_vector (4 downto 0);
\r
188 pi_plt_data : in std_logic_vector (7 downto 0);
\r
191 po_spr_ce_n : out std_logic;
\r
192 po_spr_rd_n : out std_logic;
\r
193 po_spr_wr_n : out std_logic;
\r
194 po_spr_addr : out std_logic_vector (7 downto 0);
\r
195 pi_spr_data : in std_logic_vector (7 downto 0);
\r
198 po_h_sync_n : out std_logic;
\r
199 po_v_sync_n : out std_logic;
\r
200 po_r : out std_logic_vector(3 downto 0);
\r
201 po_g : out std_logic_vector(3 downto 0);
\r
202 po_b : out std_logic_vector(3 downto 0)
\r
208 pi_rst_n : in std_logic;
\r
209 pi_base_clk : in std_logic;
\r
210 pi_cpu_en : in std_logic_vector (7 downto 0);
\r
211 pi_rnd_en : in std_logic_vector (3 downto 0);
\r
212 pi_ce_n : in std_logic;
\r
215 pio_oe_n : inout std_logic;
\r
216 pio_we_n : inout std_logic;
\r
217 pio_cpu_addr : inout std_logic_vector (15 downto 0);
\r
218 pio_cpu_d : inout std_logic_vector (7 downto 0);
\r
219 po_rdy : out std_logic;
\r
222 po_spr_ce_n : out std_logic;
\r
223 po_spr_rd_n : out std_logic;
\r
224 po_spr_wr_n : out std_logic;
\r
225 po_spr_addr : out std_logic_vector (7 downto 0);
\r
226 po_spr_data : out std_logic_vector (7 downto 0)
\r
230 constant ram_2k : integer := 11; --2k = 11 bit width.
\r
231 constant rom_32k : integer := 15; --32k = 15 bit width.
\r
232 constant vram_1k : integer := 10; --1k = 10 bit width.
\r
234 signal wr_cpu_en : std_logic_vector (7 downto 0);
\r
235 signal wr_rnd_en : std_logic_vector (3 downto 0);
\r
237 signal wr_rdy : std_logic;
\r
238 signal wr_irq_n : std_logic;
\r
239 signal wr_nmi_n : std_logic;
\r
240 signal wr_oe_n : std_logic;
\r
241 signal wr_we_n : std_logic;
\r
243 signal wr_addr : std_logic_vector ( 15 downto 0);
\r
244 signal wr_d_io : std_logic_vector ( 7 downto 0);
\r
246 signal wr_rom_ce_n : std_logic;
\r
247 signal wr_ram_ce_n : std_logic;
\r
248 signal wr_ppu_ce_n : std_logic;
\r
249 signal wr_apu_ce_n : std_logic;
\r
251 signal wr_v_ce_n : std_logic;
\r
252 signal wr_v_rd_n : std_logic;
\r
253 signal wr_v_wr_n : std_logic;
\r
254 signal wr_v_addr : std_logic_vector (13 downto 0);
\r
255 signal wr_v_data : std_logic_vector (7 downto 0);
\r
257 signal wr_plt_ce_n : std_logic;
\r
258 signal wr_plt_rd_n : std_logic;
\r
259 signal wr_plt_wr_n : std_logic;
\r
260 signal wr_plt_addr : std_logic_vector (4 downto 0);
\r
261 signal wr_plt_data : std_logic_vector (7 downto 0);
\r
263 signal wr_spr_ce_n : std_logic;
\r
264 signal wr_spr_rd_n : std_logic;
\r
265 signal wr_spr_wr_n : std_logic;
\r
266 signal wr_spr_addr : std_logic_vector (7 downto 0);
\r
267 signal wr_spr_data : std_logic_vector (7 downto 0);
\r
269 signal wr_pt_ce_n : std_logic;
\r
270 signal wr_nt0_ce_n : std_logic;
\r
271 signal wr_nt1_ce_n : std_logic;
\r
273 signal wr_ppu_ctrl : std_logic_vector (7 downto 0);
\r
274 signal wr_ppu_mask : std_logic_vector (7 downto 0);
\r
275 signal wr_ppu_status : std_logic_vector (7 downto 0);
\r
276 signal wr_ppu_scroll_x : std_logic_vector (7 downto 0);
\r
277 signal wr_ppu_scroll_y : std_logic_vector (7 downto 0);
\r
279 signal reg_dbg_cnt : std_logic_vector (63 downto 0);
\r
283 dbg_base_clk <= pi_base_clk;
\r
285 --synchronized clock generator instance
\r
286 clock_selector_inst : clock_selector port map (
\r
293 --mos 6502 cpu instance
\r
294 cpu_inst : mos6502 port map (
\r
308 --chip select (address decode)
\r
309 cs_inst : chip_selector port map (
\r
320 prom_inst : prg_rom port map (
\r
324 wr_addr(14 downto 0),
\r
329 cpu_ram_inst : ram generic map
\r
331 , "mem-before-02bd000000000000.bin"
\r
337 wr_addr(10 downto 0),
\r
342 ppu_inst : ppu port map (
\r
349 wr_addr(2 downto 0),
\r
379 --vram chip select (address decode)
\r
380 vcs_inst : v_chip_selector port map (
\r
391 --name table/attr table #0
\r
392 vram_nt0_inst : ram generic map
\r
393 (vram_1k, 8) port map (
\r
398 wr_v_addr(vram_1k - 1 downto 0),
\r
402 --name table/attr table #1
\r
403 vram_nt1_inst : ram generic map
\r
404 (vram_1k, 8) port map (
\r
409 wr_v_addr(vram_1k - 1 downto 0),
\r
414 vram_plt_inst : palette_ram port map (
\r
424 chr_rom_inst : chr_rom port map (
\r
428 wr_v_addr(12 downto 0),
\r
433 spr_ram_inst : ram generic map
\r
443 --vga render instance
\r
444 render_inst : render port map (
\r
485 apu_inst : apu port map (
\r
509 po_dbg_cnt <= reg_dbg_cnt;
\r
510 deb_cnt_p : process (pi_rst_n, pi_base_clk)
\r
511 use ieee.std_logic_unsigned.all;
\r
512 variable cnt : integer;
\r
514 if (pi_rst_n = '0') then
\r
515 reg_dbg_cnt <= (others => '0');
\r
518 if (rising_edge(pi_base_clk)) then
\r
520 --debug count is half cycle because too fast to capture in st ii.
\r
521 reg_dbg_cnt <= reg_dbg_cnt + 1;
\r
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